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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
sync
 
 

 
 
 jtag
 
 
 
  
      
 
 
 
 
    
 
      
        clk
        jtag_clk
      
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr
        update_dr
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
      
 
      
        select
        select
      
 
 
 
 
    
       
      
 
 
 
 
 
  
 
  
 
 
 syn_jtag
 
 
 
 
  
      
 
 
 
 
    
 
 
 
      
        clk
        syn_clk
      
 
      
        capture_dr
        syn_capture_dr
      
 
      
        shift_dr
        syn_shift_dr
      
 
      
        update_dr
        syn_update_dr
      
 
 
      
        tdi
        syn_tdi
      
 
      
        tdo
        syn_tdo
      
 
      
        select
        syn_select
      
 
 
 
    
 
 
        
      
 
 
 
 
  
 
  
 

 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_sync
    
  

 
 
 
 

 
 
 
 

       
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
 
jtag_clk
wire
in

 
test_logic_reset
wire
in

 
 
capture_dr
wire
in

 
 
shift_dr
wire
in

 
 
update_dr
wire
in

 
tdi
wire
in

 
tdo
wire
out

 
select
wire
in

 
 
 
syn_clk
wire
out

 
syn_capture_dr
wire
out

 
syn_shift_dr
wire
out

 
 
syn_update_dr
wire
out

 
syn_tdi
wire
out

 
 
syn_tdo
wire
in

 
syn_select
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 

 
   
      fs-sim
 
     
        
        ../verilog/sync
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
 
 
 
  
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_sync.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`jtag`
15			`sync`
16	131	jt_eaton
17
18	135	jt_eaton
19	131	jt_eaton
20
21	135	jt_eaton	`jtag`
22
23	131	jt_eaton
24
25	135	jt_eaton
26
27
28	131	jt_eaton
29	135	jt_eaton
30
31
32	131	jt_eaton
33	135	jt_eaton
34			`clk`
35			`jtag_clk`
36
37	131	jt_eaton
38	135	jt_eaton
39			`test_logic_reset`
40			`test_logic_reset`
41
42	131	jt_eaton
43	135	jt_eaton
44			`capture_dr`
45			`capture_dr`
46
47	131	jt_eaton
48	135	jt_eaton
49			`shift_dr`
50			`shift_dr`
51
52	131	jt_eaton
53	135	jt_eaton
54			`update_dr`
55			`update_dr`
56
57	131	jt_eaton
58
59	135	jt_eaton
60			`tdi`
61			`tdi`
62
63	131	jt_eaton
64	135	jt_eaton
65			`tdo`
66			`tdo`
67
68	131	jt_eaton
69	135	jt_eaton
70			`select`
71			`select`
72
73	131	jt_eaton
74
75
76
77	135	jt_eaton
78
79
80	131	jt_eaton
81
82
83	135	jt_eaton
84	131	jt_eaton
85	135	jt_eaton
86	131	jt_eaton
87	135	jt_eaton
88	131	jt_eaton
89
90	135	jt_eaton	`syn_jtag`
91
92	131	jt_eaton
93
94
95	135	jt_eaton
96
97
98	131	jt_eaton
99
100	135	jt_eaton
101
102	131	jt_eaton
103
104
105	135	jt_eaton
106			`clk`
107			`syn_clk`
108
109	131	jt_eaton
110	135	jt_eaton
111			`capture_dr`
112			`syn_capture_dr`
113
114	131	jt_eaton
115	135	jt_eaton
116			`shift_dr`
117			`syn_shift_dr`
118
119	131	jt_eaton
120	135	jt_eaton
121			`update_dr`
122			`syn_update_dr`
123
124	134	jt_eaton
125
126	135	jt_eaton
127			`tdi`
128			`syn_tdi`
129
130	134	jt_eaton
131	135	jt_eaton
132			`tdo`
133			`syn_tdo`
134
135	134	jt_eaton
136	135	jt_eaton
137			`select`
138			`syn_select`
139
140	134	jt_eaton
141
142
143	135	jt_eaton
144	134	jt_eaton
145
146	135	jt_eaton
147
148	131	jt_eaton
149
150	135	jt_eaton
151	134	jt_eaton
152	135	jt_eaton
153	134	jt_eaton
154	135	jt_eaton
155	134	jt_eaton
156	135	jt_eaton
157	134	jt_eaton
158
159	135	jt_eaton
160	134	jt_eaton
161
162
163	131	jt_eaton
164	135	jt_eaton
165			`gen_verilog`
166			`104.0`
167			`none`
168			`:common:`
169			`tools/verilog/gen_verilog`
170
171
172			`destination`
173			`jtag_sync`
174
175
176
177	131	jt_eaton
178
179
180
181	135	jt_eaton
182	131	jt_eaton
183
184
185
186	135	jt_eaton
187
188	131	jt_eaton
189
190	135	jt_eaton
191			`verilog`
192
193
194			`ipxact:library="Testbench"`
195			`ipxact:name="toolflow"`
196			`ipxact:version="verilog"/>`
197
198
199	131	jt_eaton
200
201
202	133	jt_eaton
203	135	jt_eaton
204			`common:common:`
205			`Verilog`
206
207
208			`fs-common`
209
210
211	131	jt_eaton
212
213
214
215	135	jt_eaton
216			`sim:Simulation:`
217			`Verilog`
218
219
220			`fs-sim`
221
222
223	131	jt_eaton
224	135	jt_eaton
225			`syn:Synthesis:`
226			`Verilog`
227
228
229			`fs-syn`
230
231
232	131	jt_eaton
233
234
235	135	jt_eaton
236			`doc`
237
238
239			`ipxact:library="Testbench"`
240			`ipxact:name="toolflow"`
241			`ipxact:version="documentation"/>`
242
243			`:Documentation:`
244			`Verilog`
245
246	131	jt_eaton
247
248
249
250
251
252	135	jt_eaton
253	134	jt_eaton
254
255
256
257
258	135	jt_eaton
259	134	jt_eaton
260	135	jt_eaton	`clk`
261			`wire`
262			`in`
263
264	134	jt_eaton
265
266	135	jt_eaton	`jtag_clk`
267			`wire`
268			`in`
269
270	134	jt_eaton
271	135	jt_eaton	`test_logic_reset`
272			`wire`
273			`in`
274
275	131	jt_eaton
276
277	135	jt_eaton	`capture_dr`
278			`wire`
279			`in`
280
281	131	jt_eaton
282
283	135	jt_eaton	`shift_dr`
284			`wire`
285			`in`
286
287	131	jt_eaton
288
289	135	jt_eaton	`update_dr`
290			`wire`
291			`in`
292
293	131	jt_eaton
294	135	jt_eaton	`tdi`
295			`wire`
296			`in`
297
298	131	jt_eaton
299	135	jt_eaton	`tdo`
300			`wire`
301			`out`
302
303	131	jt_eaton
304	135	jt_eaton	`select`
305			`wire`
306			`in`
307
308	131	jt_eaton
309
310
311	135	jt_eaton	`syn_clk`
312			`wire`
313			`out`
314
315	131	jt_eaton
316	135	jt_eaton	`syn_capture_dr`
317			`wire`
318			`out`
319
320	131	jt_eaton
321	135	jt_eaton	`syn_shift_dr`
322			`wire`
323			`out`
324
325	131	jt_eaton
326
327	135	jt_eaton	`syn_update_dr`
328			`wire`
329			`out`
330
331	131	jt_eaton
332	135	jt_eaton	`syn_tdi`
333			`wire`
334			`out`
335
336	131	jt_eaton
337
338	135	jt_eaton	`syn_tdo`
339			`wire`
340			`in`
341
342	131	jt_eaton
343	135	jt_eaton	`syn_select`
344			`wire`
345			`out`
346
347	131	jt_eaton
348	135	jt_eaton
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365			`fs-sim`
366
367
368
369			`../verilog/sync`
370			`verilogSourcefragment`
371
372
373
374
375
376			`../verilog/copyright`
377			`verilogSourceinclude`
378
379
380
381
382
383			`dest_dir`
384			`../verilog/`
385			`verilogSource`
386			`libraryDir`
387
388
389
390
391
392
393
394
395
396
397			`fs-syn`
398
399
400			`dest_dir`
401			`../verilog/`
402			`verilogSource`
403			`libraryDir`
404
405
406
407
408
409
410
411
412
413			`fs-lint`
414
415			`dest_dir`
416			`../verilog/`
417			`verilogSource`
418			`libraryDir`
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433