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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_tap_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
tap_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_tap_tb
    
  

 
 
 

 
 
 
 
 
 
 

  
 
  INST_LENGTH4
    INST_RETURN4'b1101
    EXTEST4'b0000
    SAMPLE4'b0001
    HIGHZ_MODE4'b0010
    CHIP_ID_ACCESS4'b0011
    CLAMP4'b1000
    RPC_DATA4'b1010
    RPC_ADD4'b1001
    BYPASS4'b1111
    CHIP_ID_VAL32'h12345678
 
 
 
    JTAG_SEL2
    JTAG_USER1_WIDTH8
    JTAG_USER1_RESET8'h12
    JTAG_USER2_WIDTH24
    JTAG_USER2_RESET24'h123456
    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4

 
 
 
        
        
        Bfm
        
        
 
                
        Dut
        
        
 
        
 
 
 
    
 
 
              
              Dut
              Dut
              
 
 
 
              
              Bfm
              Bfm
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
   
      fs-common
 
 
 
 
 
      
        
        ../verilog/tb.rpc_2
        verilogSource
        fragment
      
 
 
   
 
 
   
      fs-sim
 
 
 
 
 
      
        
        ../verilog/common/jtag_tap_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/jtag_tap_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_tap_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`jtag`
15			`tap_tb`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`jtag_tap_tb`
34
35
36
37	131	jt_eaton
38
39
40	135	jt_eaton
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49
50	131	jt_eaton
51	135	jt_eaton	`INST_LENGTH4`
52			`INST_RETURN4'b1101`
53			`EXTEST4'b0000`
54			`SAMPLE4'b0001`
55			`HIGHZ_MODE4'b0010`
56			`CHIP_ID_ACCESS4'b0011`
57			`CLAMP4'b1000`
58			`RPC_DATA4'b1010`
59			`RPC_ADD4'b1001`
60			`BYPASS4'b1111`
61			`CHIP_ID_VAL32'h12345678`
62	131	jt_eaton
63
64	135	jt_eaton
65			`JTAG_SEL2`
66			`JTAG_USER1_WIDTH8`
67			`JTAG_USER1_RESET8'h12`
68			`JTAG_USER2_WIDTH24`
69			`JTAG_USER2_RESET24'h123456`
70			`JTAG_MODEL_DIVCNT 4'h4`
71			`JTAG_MODEL_SIZE 4`
72
73	131	jt_eaton
74
75
76	135	jt_eaton
77
78			`Bfm`
79
80
81	131	jt_eaton
82	135	jt_eaton
83			`Dut`
84
85
86	131	jt_eaton
87	135	jt_eaton
88	131	jt_eaton
89
90
91	135	jt_eaton
92	131	jt_eaton
93	135	jt_eaton
94
95			`Dut`
96			`Dut`
97
98	131	jt_eaton
99
100	135	jt_eaton
101
102			`Bfm`
103			`Bfm`
104
105	131	jt_eaton
106
107	135	jt_eaton
108			`icarus`
109
110
111			`ipxact:library="Testbench"`
112			`ipxact:name="toolflow"`
113			`ipxact:version="icarus"/>`
114
115
116	131	jt_eaton
117
118
119
120	135	jt_eaton
121			`common:common:`
122			`Verilog`
123
124
125			`fs-common`
126
127
128	131	jt_eaton
129
130	135	jt_eaton
131			`sim:Simulation:`
132			`Verilog`
133
134
135			`fs-sim`
136
137
138	131	jt_eaton
139	135	jt_eaton
140			`lint:Lint:`
141			`Verilog`
142
143
144			`fs-lint`
145
146
147	131	jt_eaton
148	135	jt_eaton
149	131	jt_eaton
150
151
152
153	135	jt_eaton
154	131	jt_eaton
155
156
157
158
159	135	jt_eaton
160	131	jt_eaton
161
162	135	jt_eaton
163			`fs-common`
164	131	jt_eaton
165
166
167
168
169	135	jt_eaton
170
171			`../verilog/tb.rpc_2`
172			`verilogSource`
173			`fragment`
174
175	131	jt_eaton
176
177	135	jt_eaton
178	131	jt_eaton
179
180	135	jt_eaton
181			`fs-sim`
182	131	jt_eaton
183
184
185
186
187	135	jt_eaton
188
189			`../verilog/common/jtag_tap_tb`
190			`verilogSourcemodule`
191
192	131	jt_eaton
193
194	135	jt_eaton
195	131	jt_eaton
196
197	135	jt_eaton
198			`fs-lint`
199
200
201			`../verilog/common/jtag_tap_tb`
202			`verilogSourcemodule`
203
204	131	jt_eaton
205
206	135	jt_eaton
207
208
209
210
211
212
213
214
215
216
217
218