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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
mult
ord_r4
 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      mult_ord_r4
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 
 
 
 
 
 

 
        
 
                        
                                verilog
                                verilog
                                cde_mult_ord_r4
                                
                                        
                                                WIDTH
                                                16
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
       
 
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 

WIDTH16

 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 

 
   
      fs-common
 
 
      
        ../verilog/top.ord_r4
        verilogSourcefragment
      
 
  
 
   
      fs-sim
 
      
        ../verilog/common/mult_ord_r4
        verilogSourcemodule
      
 
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/mult_ord_r4
        verilogSourcemodule
      
 
      
        ../verilog/ord_r4.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`mult`
15			`ord_r4`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21	135	jt_eaton
22			`gen_verilog`
23			`104.0`
24			`none`
25			`:common:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`mult_ord_r4`
31
32
33
34	131	jt_eaton
35
36
37
38	135	jt_eaton
39			`gen_verilogLib_sim`
40			`105.0`
41			`none`
42			`:Simulation:`
43			`tools/verilog/gen_verilogLib`
44
45
46			`dest_dir`
47			`../views`
48
49
50			`view`
51			`sim`
52
53
54
55	131	jt_eaton
56
57	135	jt_eaton
58			`gen_verilogLib_syn`
59			`105.0`
60			`none`
61			`:Synthesis:`
62			`tools/verilog/gen_verilogLib`
63
64
65			`dest_dir`
66			`../views`
67
68
69			`view`
70			`syn`
71
72
73
74	131	jt_eaton
75
76
77	135	jt_eaton
78	131	jt_eaton
79
80
81
82
83
84
85
86	135	jt_eaton
87	131	jt_eaton
88	135	jt_eaton
89	131	jt_eaton
90	135	jt_eaton
91			`verilog`
92			`verilog`
93			`cde_mult_ord_r4`
94
95
96			`WIDTH`
97			`16`
98
99
100
101			`fs-sim`
102
103
104
105	131	jt_eaton
106
107
108	135	jt_eaton
109
110	131	jt_eaton
111
112
113	135	jt_eaton
114			`rtl`
115			`verilog:Kactus2:`
116			`verilog`
117
118	131	jt_eaton
119
120	135	jt_eaton
121
122			`common:common:`
123
124			`Verilog`
125
126
127			`fs-common`
128
129
130	131	jt_eaton
131
132	135	jt_eaton
133			`sim:Simulation:`
134
135			`Verilog`
136
137
138			`fs-sim`
139
140
141	131	jt_eaton
142
143
144	135	jt_eaton
145			`syn:Synthesis:`
146
147			`Verilog`
148
149
150			`fs-syn`
151
152
153	131	jt_eaton
154
155	135	jt_eaton
156			`doc`
157
158
159			`ipxact:library="Testbench"`
160			`ipxact:name="toolflow"`
161			`ipxact:version="documentation"/>`
162
163			`:Documentation:`
164			`Verilog`
165
166	131	jt_eaton
167
168
169
170
171	135	jt_eaton
172	131	jt_eaton
173
174	135	jt_eaton
175			`WIDTH16`
176
177	131	jt_eaton
178
179
180
181
182	135	jt_eaton
183	131	jt_eaton
184	135	jt_eaton	`clk`
185			`wire`
186			`in`
187
188	131	jt_eaton
189	135	jt_eaton	`reset`
190			`wire`
191			`in`
192
193	131	jt_eaton
194
195
196
197
198
199	135	jt_eaton	`a_in`
200			`wire`
201			`in`
202			`WIDTH-10`
203
204	131	jt_eaton
205
206	135	jt_eaton	`b_in`
207			`wire`
208			`in`
209			`WIDTH-10`
210
211	131	jt_eaton
212
213	135	jt_eaton	`alu_op_mul`
214			`wire`
215			`in`
216
217	131	jt_eaton
218
219	135	jt_eaton	`ex_freeze`
220			`wire`
221			`in`
222
223	131	jt_eaton
224
225
226
227	135	jt_eaton	`mul_prod_r`
228			`reg`
229			`out`
230			`2*WIDTH-10`
231
232	131	jt_eaton
233
234	135	jt_eaton	`mul_stall`
235			`wire`
236			`out`
237
238	131	jt_eaton
239
240
241
242	135	jt_eaton
243	131	jt_eaton
244	135	jt_eaton
245	131	jt_eaton
246
247
248
249	135	jt_eaton
250	131	jt_eaton
251	135	jt_eaton
252			`fs-common`
253	131	jt_eaton
254
255	135	jt_eaton
256			`../verilog/top.ord_r4`
257			`verilogSourcefragment`
258
259	131	jt_eaton
260	135	jt_eaton
261	131	jt_eaton
262	135	jt_eaton
263			`fs-sim`
264	131	jt_eaton
265	135	jt_eaton
266			`../verilog/common/mult_ord_r4`
267			`verilogSourcemodule`
268
269	131	jt_eaton
270
271	135	jt_eaton
272			`../verilog/ord_r4.v`
273			`verilogSourcemodule`
274
275	131	jt_eaton
276
277	135	jt_eaton
278
279			`dest_dir../views/sim/`
280			`verilogSourcelibraryDir`
281
282	131	jt_eaton
283	135	jt_eaton
284	131	jt_eaton
285
286	135	jt_eaton
287			`fs-syn`
288	131	jt_eaton
289	135	jt_eaton
290			`../verilog/common/mult_ord_r4`
291			`verilogSourcemodule`
292
293	131	jt_eaton
294	135	jt_eaton
295			`../verilog/ord_r4.v`
296			`verilogSourcemodule`
297
298	131	jt_eaton
299
300	135	jt_eaton
301			`dest_dir../views/syn/`
302			`verilogSourcelibraryDir`
303
304	131	jt_eaton
305
306
307	135	jt_eaton
308	131	jt_eaton
309
310
311	135	jt_eaton
312	131	jt_eaton
313	135	jt_eaton	`fs-lint`
314
315			`dest_dir../views/syn/`
316			`verilogSourcelibraryDir`
317
318	131	jt_eaton
319	135	jt_eaton
320
321
322
323
324
325
326
327
328
329
330
331
332