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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_adhoc.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
pad
in_adhoc
 
 
 
 

 
 
 
 
 pad
  
 
  
      
  
          
            
        pad_in
        pad_in        
            
          
        
      
  
 
 
 
 
 
 

 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_in_adhoc
    
  

 
 
 
 

 
 
 

 
 
 
 
                
                        
                                verilog
                                verilog
                                cde_pad_in_adhoc
                                
                                        
                                                WIDTH
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
  
 
                
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 

WIDTH1

 
 
 

 
 
pad_in
wire
in
WIDTH-10

 
 
 
adhoc_pad_in
wire
out
WIDTH-10

 
 
 
 
 
 
 
 
 
 

 

 
 
 
 
 

 
 
 
 
      fs-common
 
      
        
        ../verilog/pad_in_dig
        verilogSourcefragment
      
 
   
 
 
 
   
      fs-sim
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_in_adhoc
        verilogSourcemodule
      
 
 
 
       
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_in_adhoc
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_adhoc.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`in_adhoc`
16
17
18
19
20
21
22
23
24
25			`pad`
26
27
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31
32
33			`pad_in`
34			`pad_in`
35
36
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47
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49
50
51
52
53
54
55			`gen_verilog`
56			`104.0`
57			`none`
58			`:common:`
59			`tools/verilog/gen_verilog`
60
61
62			`destination`
63			`pad_in_adhoc`
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82			`verilog`
83			`verilog`
84			`cde_pad_in_adhoc`
85
86
87			`WIDTH`
88			`1`
89
90
91
92			`fs-sim`
93
94
95
96
97
98
99
100
101
102
103			`rtl`
104			`verilog:Kactus2:`
105			`verilog`
106
107
108
109			`verilog`
110
111
112			`ipxact:library="Testbench"`
113			`ipxact:name="toolflow"`
114			`ipxact:version="verilog"/>`
115
116
117
118
119
120
121			`common:common:`
122			`Verilog`
123
124
125			`fs-common`
126
127
128
129
130
131			`sim:Simulation:`
132			`Verilog`
133
134
135			`fs-sim`
136
137
138
139
140			`syn:Synthesis:`
141			`Verilog`
142
143
144			`fs-syn`
145
146
147
148
149			`doc`
150
151
152			`ipxact:library="Testbench"`
153			`ipxact:name="toolflow"`
154			`ipxact:version="documentation"/>`
155
156			`:Documentation:`
157			`Verilog`
158
159
160
161
162
163
164			`WIDTH1`
165
166
167
168
169
170
171
172			`pad_in`
173			`wire`
174			`in`
175			`WIDTH-10`
176
177
178
179
180			`adhoc_pad_in`
181			`wire`
182			`out`
183			`WIDTH-10`
184
185
186
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188
189
190
191
192
193
194
195
196
197
198
199
200
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207
208			`fs-common`
209
210
211
212			`../verilog/pad_in_dig`
213			`verilogSourcefragment`
214
215
216
217
218
219
220
221			`fs-sim`
222
223
224
225
226			`../verilog/copyright`
227			`verilogSourceinclude`
228
229
230
231
232
233			`../verilog/common/pad_in_adhoc`
234			`verilogSourcemodule`
235
236
237
238
239
240			`dest_dir`
241			`../views/sim/`
242			`verilogSourcelibraryDir`
243
244
245
246
247
248
249			`fs-syn`
250
251
252
253
254			`../verilog/copyright`
255			`verilogSourceinclude`
256
257
258
259
260
261			`../verilog/common/pad_in_adhoc`
262			`verilogSourcemodule`
263
264
265
266
267			`dest_dir`
268			`../views/syn/`
269			`verilogSourcelibraryDir`
270
271
272
273
274
275
276
277
278
279
280			`fs-lint`
281
282			`dest_dir`
283			`../views/syn/`
284			`verilogSourcelibraryDir`
285
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