URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reg/] [rtl/] [xml/] [cde_reg_def.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
reg
def
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      reg_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      reg_def
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 
 
 
 
 
 
 

 
   
      fs-sim
 
       
        ../verilog/logic
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/reg_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
       
        ../verilog/logic
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/reg_def
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
            
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
D
wire
in

 
clk
wire
in

 
 
 
 
 
Q
reg
out

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 

 
 

 

 geda-project.org
 symbols
 gates
 def
 reg
 0
 300

 
 
 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 700
 clk
0

 
 
 
 
 

refdes
U?
1200
2200
5
10
1
1
2

 

module_name
cde_reg_def
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
reg
0
-400
0
10
0
0
0

 
 
 

version
def
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_reg_def
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 1700
 D
 1

 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1300
 1700
 Q
 1

 
 

 
 
 

vector
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 1700
 D
 1

 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1300
 1700
 Q
 1

 
 

 
 
 
 
 
 

 
 


 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reg/] [rtl/] [xml/] [cde_reg_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`reg`
15			`def`
16
17
18
19
20
21
22			`gen_verilog_sim`
23			`104.0`
24			`none`
25			`:Simulation:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`reg_def`
31
32
33
34
35
36
37			`gen_verilog_syn`
38			`104.0`
39			`none`
40			`:Synthesis:`
41			`tools/verilog/gen_verilog`
42
43
44			`destination`
45			`reg_def`
46
47
48
49
50
51
52
53
54			`gen_verilogLib_sim`
55			`105.0`
56			`none`
57			`:Simulation:`
58			`tools/verilog/gen_verilogLib`
59
60
61			`dest_dir`
62			`../views`
63
64
65			`view`
66			`sim`
67
68
69
70
71
72
73
74			`gen_verilogLib_syn`
75			`105.0`
76			`none`
77			`:Synthesis:`
78			`tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`syn`
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106			`fs-sim`
107
108
109			`../verilog/logic`
110			`verilogSourcefragment`
111
112
113
114
115			`../verilog/copyright`
116			`verilogSourceinclude`
117
118
119
120
121			`../verilog/sim/reg_def`
122			`verilogSourcemodule`
123
124
125
126
127
128			`dest_dir`
129			`../views/sim/`
130			`verilogSourcelibraryDir`
131
132
133
134
135
136
137			`fs-syn`
138
139
140
141			`../verilog/logic`
142			`verilogSourcefragment`
143
144
145
146
147			`../verilog/copyright`
148			`verilogSourceinclude`
149
150
151
152
153			`../verilog/sim/reg_def`
154			`verilogSourcemodule`
155
156
157
158
159
160
161			`dest_dir`
162			`../views/syn/`
163			`verilogSourcelibraryDir`
164
165
166
167
168
169
170
171
172
173			`fs-lint`
174
175			`dest_dir`
176			`../views/syn/`
177			`verilogSourcelibraryDir`
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199			`sim:Simulation:`
200			`Verilog`
201
202
203			`fs-sim`
204
205
206
207
208			`syn:Synthesis:`
209			`Verilog`
210
211
212			`fs-syn`
213
214
215
216
217
218			`doc`
219
220
221			`ipxact:library="Testbench"`
222			`ipxact:name="toolflow"`
223			`ipxact:version="documentation"/>`
224
225			`:Documentation:`
226			`Verilog`
227
228
229
230
231
232
233
234
235
236
237
238
239			`D`
240			`wire`
241			`in`
242
243
244			`clk`
245			`wire`
246			`in`
247
248
249
250
251
252
253			`Q`
254			`reg`
255			`out`
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280			`geda-project.org`
281			`symbols`
282			`gates`
283			`def`
284			`reg`
285			`0`
286			`300`
287
288
289
290
291
292
293
294
295
296			`geda-project.org`
297			`symbols`
298			`pins`
299			`def`
300			`in_wire`
301			`0`
302			`700`
303			`clk`
304			`0`
305
306
307
308
309
310
311
312			`refdes`
313			`U?`
314			`1200`
315			`2200`
316			`5`
317			`10`
318			`1`
319			`1`
320			`2`
321
322
323
324			`module_name`
325			`cde_reg_def`
326			`400`
327			`0`
328			`5`
329			`10`
330			`0`
331			`1`
332			`2`
333
334
335
336			`vendor`
337			`opencores.org`
338			`0`
339			`-200`
340			`0`
341			`10`
342			`0`
343			`0`
344			`0`
345
346
347
348			`library`
349			`cde`
350			`0`
351			`-300`
352			`0`
353			`10`
354			`0`
355			`0`
356			`0`
357
358
359
360
361			`component`
362			`reg`
363			`0`
364			`-400`
365			`0`
366			`10`
367			`0`
368			`0`
369			`0`
370
371
372
373
374
375			`version`
376			`def`
377			`0`
378			`-500`
379			`0`
380			`10`
381			`0`
382			`0`
383			`0`
384
385
386
387
388
389
390
391
392
393
394
395
396			`cde_reg_def`
397
398
399
400
401			`geda-project.org`
402			`symbols`
403			`pins`
404			`def`
405			`in_wire`
406			`0`
407			`1700`
408			`D`
409			`1`
410
411
412
413			`geda-project.org`
414			`symbols`
415			`pins`
416			`def`
417			`out_wire`
418			`1300`
419			`1700`
420			`Q`
421			`1`
422
423
424
425
426
427
428
429
430			`vector`
431
432
433
434
435			`geda-project.org`
436			`symbols`
437			`pins`
438			`def`
439			`in_bus`
440			`0`
441			`1700`
442			`D`
443			`1`
444
445
446
447			`geda-project.org`
448			`symbols`
449			`pins`
450			`def`
451			`out_bus`
452			`1300`
453			`1700`
454			`Q`
455			`1`
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477