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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
reset
def
 
 
 

 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 

 
 
 
 
 
 

 
                
 
 
 
                
                Hierarchical
                
                
 
 
                        
                                verilog
                                verilog
                                cde_reset_def
                                
                                        
                                                WIDTH
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
 
                
 
 
 
 
 
       
 
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
              
              Hierarchical
 
            Hierarchical
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

WIDTH1
DEPTH1

 

 
clk
wire
in

 
async_reset_n
wire
in

 
atg_asyncdisable
wire
in

 
sync_reset
wire
in
WIDTH-10

 
 
reset_n_out
wire
out
WIDTH-10

 
 
 
reset_out
wire
out
WIDTH-10

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [reset/] [rtl/] [xml/] [cde_reset_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`reset`
15			`def`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24
25
26	135	jt_eaton
27	131	jt_eaton
28
29
30	135	jt_eaton
31	131	jt_eaton
32	135	jt_eaton
33			`fs-sim`
34	131	jt_eaton
35
36	135	jt_eaton
37			`dest_dir`
38			`../verilog/`
39			`verilogSourcelibraryDir`
40
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44
45	135	jt_eaton
46			`fs-syn`
47	131	jt_eaton
48	135	jt_eaton
49			`dest_dir`
50			`../verilog/`
51			`verilogSourcelibraryDir`
52
53	131	jt_eaton
54
55
56	135	jt_eaton
57	131	jt_eaton
58
59	135	jt_eaton
60	131	jt_eaton
61	135	jt_eaton	`fs-lint`
62
63			`dest_dir`
64			`../verilog/`
65			`verilogSourcelibraryDir`
66
67	131	jt_eaton
68	135	jt_eaton
69	131	jt_eaton
70
71
72	135	jt_eaton
73	131	jt_eaton
74
75
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78
79	135	jt_eaton
80	131	jt_eaton
81	135	jt_eaton
82	131	jt_eaton
83
84
85	135	jt_eaton
86			`Hierarchical`
87
88
89	131	jt_eaton
90	135	jt_eaton
91
92			`verilog`
93			`verilog`
94			`cde_reset_def`
95
96
97			`WIDTH`
98			`1`
99
100
101
102			`fs-sim`
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117			`rtl`
118			`verilog:Kactus2:`
119			`verilog`
120
121
122
123
124			`Hierarchical`
125
126			`Hierarchical`
127
128
129
130
131			`sim:Simulation:`
132			`Verilog`
133
134
135			`fs-sim`
136
137
138
139
140			`syn:Synthesis:`
141			`Verilog`
142
143
144			`fs-syn`
145
146
147
148	131	jt_eaton
149
150	135	jt_eaton
151			`doc`
152
153
154			`ipxact:library="Testbench"`
155			`ipxact:name="toolflow"`
156			`ipxact:version="documentation"/>`
157
158			`:Documentation:`
159			`Verilog`
160
161	131	jt_eaton
162
163	135	jt_eaton
164	131	jt_eaton
165
166
167	135	jt_eaton
168			`WIDTH1`
169			`DEPTH1`
170
171	131	jt_eaton
172	135	jt_eaton
173	131	jt_eaton
174	135	jt_eaton	`clk`
175			`wire`
176			`in`
177
178	131	jt_eaton
179	135	jt_eaton	`async_reset_n`
180			`wire`
181			`in`
182
183	131	jt_eaton
184	135	jt_eaton	`atg_asyncdisable`
185			`wire`
186			`in`
187
188	131	jt_eaton
189	135	jt_eaton	`sync_reset`
190			`wire`
191			`in`
192			`WIDTH-10`
193
194	131	jt_eaton
195
196	135	jt_eaton	`reset_n_out`
197			`wire`
198			`out`
199			`WIDTH-10`
200
201	131	jt_eaton
202
203
204	135	jt_eaton	`reset_out`
205			`wire`
206			`out`
207			`WIDTH-10`
208
209	131	jt_eaton
210
211
212
213
214	135	jt_eaton
215	131	jt_eaton
216	135	jt_eaton
217	131	jt_eaton
218
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226	135	jt_eaton