OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [doc/] [sch/] [cde_serial_rcvr.sch] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton
v 20100214 1
2
C 1500 300 1 0 0 in_port.sym
3
{
4
T 1500 300 5 10 1 1 0 6 1 1
5
refdes=ser_in
6
}
7
C 1500 700 1 0 0 in_port.sym
8
{
9
T 1500 700 5 10 1 1 0 6 1 1
10
refdes=reset
11
}
12
C 1500 1100 1 0 0 in_port.sym
13
{
14
T 1500 1100 5 10 1 1 0 6 1 1
15
refdes=parity_type
16
}
17
C 1500 1500 1 0 0 in_port.sym
18
{
19
T 1500 1500 5 10 1 1 0 6 1 1
20
refdes=parity_force
21
}
22
C 1500 1900 1 0 0 in_port.sym
23
{
24
T 1500 1900 5 10 1 1 0 6 1 1
25
refdes=parity_enable
26
}
27
C 1500 2300 1 0 0 in_port.sym
28
{
29
T 1500 2300 5 10 1 1 0 6 1 1
30
refdes=edge_enable
31
}
32
C 1500 2700 1 0 0 in_port.sym
33
{
34
T 1500 2700 5 10 1 1 0 6 1 1
35
refdes=clk
36
}
37
C 5100 300  1 0  0 out_port_vector.sym
38
{
39
T 6100 300 5  10 1 1 0 0 1 1
40
refdes=shift_buffer[WIDTH-1:0]
41
}
42
C 5100 700  1 0 0 out_port.sym
43
{
44
T 6100 700 5  10 1 1 0 0 1 1
45
refdes=stop_cnt
46
}
47
C 5100 1100  1 0 0 out_port.sym
48
{
49
T 6100 1100 5  10 1 1 0 0 1 1
50
refdes=parity_samp
51
}
52
C 5100 1500  1 0 0 out_port.sym
53
{
54
T 6100 1500 5  10 1 1 0 0 1 1
55
refdes=parity_calc
56
}
57
C 5100 1900  1 0 0 out_port.sym
58
{
59
T 6100 1900 5  10 1 1 0 0 1 1
60
refdes=last_cnt
61
}
62
C 5100 2300  1 0 0 out_port.sym
63
{
64
T 6100 2300 5  10 1 1 0 0 1 1
65
refdes=frame_err
66
}
67
C 5100 2700  1 0 0 out_port.sym
68
{
69
T 6100 2700 5  10 1 1 0 0 1 1
70
refdes=break_detect
71
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.