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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
sram
dp
 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      sram_dp
    
  

 

 
 
 
 
 
 
 

 
                
                        
                                verilog
                                verilog
                                cde_sram_dp
                                
                                        
                                                ADDR
                                                8
                                        
                                        
                                                WIDTH
                                                8
                                        
                                        
                                                WORDS
                                                256
                                        
                                        
                                                WRITETHRU
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
       
 
                        
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
             
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
                     
                            fs-syn
                     
              
 
              
              lint:*Lint:*
              Verilog
                     
                            fs-lint
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 

 
clk

wire
in

 
cs

wire
in

 
wr

wire
in

 
rd

wire
in

 
 
waddr

wire
in
ADDR-10

 
raddr

wire
in
ADDR-10

 
 
wdata

wire
in
WIDTH-10

 
rdata

reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 

 
  
      fs-common
 
      
        
        ../verilog/sram_dp
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
   
      fs-sim
 
 
 
    
        
        ../verilog/common/sram_dp
        verilogSourcemodule
      
 
 
       
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
    
        
        ../verilog/common/sram_dp
        verilogSourcemodule
      
 
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
   
      fs-lint
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
   
 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`sram`
15			`dp`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21	135	jt_eaton
22			`gen_verilog`
23			`104.0`
24			`none`
25			`:common:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`sram_dp`
31
32
33
34	131	jt_eaton
35	135	jt_eaton
36	131	jt_eaton
37
38
39	134	jt_eaton
40
41
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton
46
47			`verilog`
48			`verilog`
49			`cde_sram_dp`
50
51
52			`ADDR`
53			`8`
54
55
56			`WIDTH`
57			`8`
58
59
60			`WORDS`
61			`256`
62
63
64			`WRITETHRU`
65			`1`
66
67
68
69			`fs-sim`
70
71
72
73	131	jt_eaton
74	134	jt_eaton
75	135	jt_eaton
76
77	134	jt_eaton
78	135	jt_eaton
79			`rtl`
80			`verilog:Kactus2:`
81			`verilog`
82
83	134	jt_eaton
84	135	jt_eaton
85			`verilog`
86
87
88			`ipxact:library="Testbench"`
89			`ipxact:name="toolflow"`
90			`ipxact:version="verilog"/>`
91
92
93	131	jt_eaton
94	135	jt_eaton
95			`common:common:`
96			`Verilog`
97
98
99			`fs-common`
100
101
102	131	jt_eaton
103
104	135	jt_eaton
105			`sim:Simulation:`
106			`Verilog`
107
108			`fs-sim`
109
110
111	131	jt_eaton
112	135	jt_eaton
113			`syn:Synthesis:`
114			`Verilog`
115
116			`fs-syn`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`lint:Lint:`
122			`Verilog`
123
124			`fs-lint`
125
126
127	131	jt_eaton
128	135	jt_eaton
129
130			`doc`
131
132
133			`ipxact:library="Testbench"`
134			`ipxact:name="toolflow"`
135			`ipxact:version="documentation"/>`
136
137			`:Documentation:`
138			`Verilog`
139
140
141
142	131	jt_eaton
143
144
145
146	135	jt_eaton
147	131	jt_eaton
148
149
150
151	135	jt_eaton
152	131	jt_eaton
153	135	jt_eaton	`clk`
154
155			`wire`
156			`in`
157
158	131	jt_eaton
159	135	jt_eaton	`cs`
160
161			`wire`
162			`in`
163
164	131	jt_eaton
165	135	jt_eaton	`wr`
166
167			`wire`
168			`in`
169
170	131	jt_eaton
171	135	jt_eaton	`rd`
172
173			`wire`
174			`in`
175
176	131	jt_eaton
177
178	135	jt_eaton	`waddr`
179
180			`wire`
181			`in`
182			`ADDR-10`
183
184	131	jt_eaton
185	135	jt_eaton	`raddr`
186
187			`wire`
188			`in`
189			`ADDR-10`
190
191	131	jt_eaton
192
193	135	jt_eaton	`wdata`
194
195			`wire`
196			`in`
197			`WIDTH-10`
198
199	131	jt_eaton
200	135	jt_eaton	`rdata`
201
202			`reg`
203			`out`
204			`WIDTH-10`
205
206	131	jt_eaton
207
208
209	135	jt_eaton
210	131	jt_eaton
211	135	jt_eaton
212	131	jt_eaton
213
214
215
216
217
218	135	jt_eaton
219	131	jt_eaton
220	135	jt_eaton
221			`fs-common`
222	131	jt_eaton
223	135	jt_eaton
224
225			`../verilog/sram_dp`
226			`verilogSourcefragment`
227
228	131	jt_eaton
229
230	135	jt_eaton
231
232			`../verilog/copyright`
233			`verilogSourceinclude`
234
235	131	jt_eaton
236
237
238	135	jt_eaton
239	131	jt_eaton
240
241	135	jt_eaton
242			`fs-sim`
243	131	jt_eaton
244
245	134	jt_eaton
246	135	jt_eaton
247
248			`../verilog/common/sram_dp`
249			`verilogSourcemodule`
250
251	134	jt_eaton
252
253	135	jt_eaton
254			`dest_dir../views/sim/`
255			`verilogSourcelibraryDir`
256
257	131	jt_eaton
258
259
260	135	jt_eaton
261	131	jt_eaton
262
263	135	jt_eaton
264			`fs-syn`
265	131	jt_eaton
266
267	135	jt_eaton
268
269			`../verilog/common/sram_dp`
270			`verilogSourcemodule`
271
272	131	jt_eaton
273
274
275	135	jt_eaton
276			`dest_dir../views/syn/`
277			`verilogSourcelibraryDir`
278
279	131	jt_eaton
280
281	135	jt_eaton
282	131	jt_eaton
283
284
285	135	jt_eaton
286			`fs-lint`
287	131	jt_eaton
288	135	jt_eaton
289			`dest_dir../views/syn/`
290			`verilogSourcelibraryDir`
291
292	131	jt_eaton
293	135	jt_eaton
294	131	jt_eaton
295	135	jt_eaton
296	131	jt_eaton
297
298
299
300
301
302
303
304
305	135	jt_eaton