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Soft AVR Core + Interfaces
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==========================
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Introduction
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------------
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This package is a full-stack implementation of the AVR 2-stage pipeline,
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featuring synthesis for AVR2 (classic core), AVR2.5 (classic plus), AVR3
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(with extended program memory), AVR4 (enhanced core) and AVR5 (enhanced core
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with extended program memory). Interrupts are supported with customized number
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of IRQ vector width.
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The project comes with some example peripherals, such as UART, SPI, a
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basic timer, output port and SysTick timer.
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Synthetized and tested using various tools, including free & open source
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packages:
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 - iCE40HX8K-BG121 and iCE40HX8K-CT256 (on ICE40HX8K-B-EVN and custom
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design boards): Project IceStorm: yosys-0.9, nextpnr-ice40 and icestorm
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utilities;
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 - iCE40HX8K-BG121 and iCE40HX8K-CT256 (on ICE40HX8K-B-EVN and custom
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design boards): Lattice iCEcube2; and
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 - XA7A100T-1CSG324 (on a Digilent Nexys A7 board): Xilinx Vivado 2019.1.
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Software run by the core can seamlessly be built with the AVR-GCC
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toolchain. This bundle includes utilities aiding the conversion from ELF
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output to BRAM initializations (designed for iCE40 EBRs) or generic
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synchronous ROM interface to set up the initial program memory. A
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configurable startup code (crt0.s) is included in the package with
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options to be matched to the synthetized core architecture.
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Availability
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------------
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This package is available from https://szofi.net/pub/verilog/softavrcore/.
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Select the softavrcore-latest.tar.gz file for the latest version. Comments
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are welcomed! Contact: Andras Pal .
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Getting started
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---------------
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 - On a Linux system, install the following toolchains and utilities:
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        * gcc-avr
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        * avr-libc
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        * binutils-avr
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        * icestorm
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        * yosys
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        * nextpnr-ice40
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   then enter `make` in the main directory. This will compile the example
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   C code (found in ./build) and then run the synthesis and place-and-route
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   targeted for the ICE40HX8K-B-EVN board. This step is automatically following
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   by the generation of the FPGA configuration bitstream for iCE40HX8K-CT256
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   in the file top.bin.
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 - On another operating systems for non-Lattice FPGA targets:
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        * use the corresponding AVR port to compile the source and create
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          the main.bin file. A working bash/awk is needed to automatically
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          create the *.v files containing the flash interface for this
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          virtual MCU. These are available on MacOS by default. On Windows, you
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          may need to install additional components (e.g. Cygwin).
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        * Collect the source *.v files, including the core (avr_core.v),
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          peripherals (avr_io_*.v), flash interface (main.v), data memory
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          (ram.v) and the top module (top.v) into a single directory _if_ your
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          operating system does not support symlinks.
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        * Import the top.v to your synthesis toolchain (icecube2, vivado, ...).
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          You can use the shipped *.pcf files for Lattice tools (such as
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          icecube2) without any further modifications. For Xilinx, you may
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          use the file top-digilent_nexys_a7-cx7a100t.xdc as a starting point,
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          or use it without any modifications for the Digilent Nexys A7 board.
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By default the example code (./build/main.c) sends the following series of
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messages via the built-in secondary UART interface of the ICE40HX8K-B-EVN
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board at 115200 baud:
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        [x] 0 => 0
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        [x] 1 => 1
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        [x] 2 => 4
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        [x] 3 => 9
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        [x] 4 => 16
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        [x] 5 => 25
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        [x] 6 => 36
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        ...
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Here the cadence is one message per minute. The cores and the C code expect
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a 12MHz clock input for baud rate configuration and during the computation
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of the timer delay.
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You may change the contents of the main() function to switch to another
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examples. Note also that the example is fitted for 1024 words of program code
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(i.e. 2048 bytes of program flash memory). Change top.v and ./build/Makefile
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accordingly for larger (or smaller) program memory configurations.
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Known issues
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------------
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 - LD/ST operations work only on data memory interface, not on the I/O
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port and the register file. GCC is not known to generate such code unless
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register mappings are explicitly indexed with the X, Y or Z pointer registers.
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Since registers are not available directly for C code and I/O ports are
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defined to be constants for all of the relevant peripherals, it is not
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expected at all and access to those areas are seamlessly translated by GCC to
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the faster MOV, IN and OUT instructions instead of LD/ST.
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 - SPM instruction is not supported, however, equivalent
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self-programming interfaces can be synthetized by custom peripherals.
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 - Watchdog is not supported, however, equivalent functionality can be
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synthetized by custom peripherals.
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 - Automatic interrupt acknowledgement is not supported at the moment.
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 - Fuse bits and in-system programming are not supported. These are, in
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practice, nearly meaningless on such an FPGA-based CPU/MCU implementation.
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 - This soft AVR CPU is cycle compatible with the exception of the store
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operations (LD, LDS, LDD, PUSH). These store operations runs faster by 1 cycle
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compared to the AVR hardware. Use a preceeding or following NOP to be
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cycle compatible with off-the-shelf AVR hardware.
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Coming soon
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-----------
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 - I2C peripheral
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 - CAN bus interface
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 - An implementation of the AVR architecture using a 4-stage pipeline
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 - FreeRTOS port
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 - some more detaild documentation
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