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[/] [softavrcore/] [trunk/] [peripherals/] [avr_io_uart.v] - Blame information for rev 2

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1 2 apal
/*****************************************************************************/
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/* avr_io_uart.v                                                             */
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/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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/* (c) 2019-2020; Andras Pal <apal@szofi.net>                                */
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/*****************************************************************************/
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module uart_tx (input clk, input [7:0] prescaler, input [7:0] tx_in, input strobe, output reg txd, output busy, output prefetch);
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parameter TX_STATE_IDLE = 0;
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parameter TX_STATE_TRANSMIT = 1;
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reg state = TX_STATE_IDLE;
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//reg txd = 1;
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reg [7:0] count = 0;
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reg [7:0] scaler_counter = 0;
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reg [7:0] dataout = 0;
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parameter count_step = 2;
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assign busy = state;
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wire scaler_limit = (scaler_counter==0);
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wire bit_limit = (count[3:0] == 4'b0000);
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wire last_bit = (count[7:4]==4'd10);
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assign prefetch = ( state==TX_STATE_TRANSMIT ) & scaler_limit & bit_limit & last_bit;
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always @(posedge clk) begin
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        if ( state==TX_STATE_IDLE && strobe ) begin
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                state <= TX_STATE_TRANSMIT;
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                txd <= 0;
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                count <= count_step;
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                dataout <= tx_in;
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                scaler_counter <= prescaler;
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        end else if ( state==TX_STATE_TRANSMIT && scaler_limit ) begin
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                if ( bit_limit ) begin
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                        if ( last_bit ) begin
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                                if ( strobe ) begin
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                                        txd <= 0;
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                                        count <= count_step;
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                                        dataout <= tx_in;
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                                end else begin
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                                        txd <= 1;
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                                        state <= TX_STATE_IDLE;
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                                end
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                        end else begin
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                                txd <= dataout[0];
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                                dataout <= { 1'b1, dataout[7:1] };
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                                count <= count + count_step;
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                        end
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                end else begin
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                        count <= count + count_step;
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                end
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                scaler_counter <= prescaler;
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        end else if ( state==TX_STATE_TRANSMIT ) begin
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                scaler_counter <= scaler_counter - 1;
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        end
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end
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endmodule
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/*****************************************************************************/
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module uart_rx (input clk, input [7:0] prescaler, input rxd, input reset, output [7:0] rx_out, output reg avail);
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parameter STATE_IDLE = 0;
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parameter STATE_STARTBIT = 2;
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parameter STATE_RECEIVE = 3;
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reg [1:0] state = STATE_IDLE;
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reg [7:0] count = 0;
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reg [7:0] scaler_counter = 0;
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reg [7:0] datain = 0;
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//reg avail = 0;
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parameter count_step = 2;
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wire rx_sub_bit = ( state==STATE_RECEIVE && scaler_counter==0 );
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wire rx_bit = (rx_sub_bit && count[3:0] == 4'b0000);
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wire rx_completed = (rx_bit && count[7:4]==4'd9 );
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assign rx_out = datain;
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always @(posedge clk) begin
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        if ( state==STATE_IDLE && rxd==0 ) begin
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                state <= STATE_STARTBIT;
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                count <= count_step;
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                scaler_counter <= prescaler;
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        end else if ( state==STATE_STARTBIT && scaler_counter==0 ) begin
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                if ( count[3:0] == 4'b1000 ) begin
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                        state <= STATE_RECEIVE;
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                        count <= count_step;
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                end else begin
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                        count <= count + count_step;
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                end
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                scaler_counter <= prescaler;
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        end else if ( state==STATE_RECEIVE && scaler_counter==0 ) begin
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                if ( count[3:0] == 4'b0000 ) begin
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                        if ( count[7:4]==4'd9 ) begin
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                                state <= STATE_IDLE;
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                        end else begin
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                                datain <= { rxd, datain[7:1] };
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                                count <= count + count_step;
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                        end
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                end else begin
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                        count <= count + count_step;
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                end
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                scaler_counter <= prescaler;
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        end else if ( state[1] ) begin
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                scaler_counter <= scaler_counter - 1;
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        end
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        avail <= rx_completed | (avail & ~reset);
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end
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endmodule
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/*****************************************************************************/
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module avr_io_uart
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 (      input clk,
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        input rst,
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        input io_re,
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        input io_we,
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        input [1:0] io_a,
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        output [7:0] io_do,
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        input [7:0] io_di,
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        output txd,
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        input rxd,
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        output  [2:0] irq
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 );
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reg [7:0] UDR_TX = 0;
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reg [7:0] UDR_RX  = 0;
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reg [7:0] UCSRB  = 0;
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reg [7:0] UBRR  = 0;
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parameter UCSRA_RXB8    = 3'd0;
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parameter UCSRA_x1      = 3'd1;
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parameter UCSRA_PE      = 3'd2;
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parameter UCSRA_DOR     = 3'd3;
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parameter UCSRA_FE      = 3'd4;
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parameter UCSRA_UDRE    = 3'd5;
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parameter UCSRA_TXC     = 3'd6;
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parameter UCSRA_RXC     = 3'd7;
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wire    RXCIE, TXCIE, UDRIE, USBS, UPM1, UPM0, UCSZ, TXB8;
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assign  { RXCIE, TXCIE, UDRIE, USBS, UPM1, UPM0, UCSZ, TXB8 } = UCSRB;
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reg     rx0_non_empty = 0, rx0_overrun = 0, rx0_reset = 0;
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wire    tx0_txd,tx0_busy,tx0_prefetch;
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reg     tx0_non_empty = 0;
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wire [7:0] UCSRA = { rx0_non_empty, ~tx0_busy, ~tx0_non_empty, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
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assign  irq = UCSRB[7:5] & UCSRA[7:5];
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/* I/O read: */
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reg [7:0] io_do_data;
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always @(*) begin
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        casex (io_a)
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                2'b00: io_do_data = UDR_RX[7:0];
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                2'b01: io_do_data = UCSRA;
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                2'b10: io_do_data = UCSRB;
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                2'b11: io_do_data = UBRR;
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        endcase
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end
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assign io_do = io_re ? io_do_data : 8'b00000000;
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/* I/O write: configuration: */
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always @(posedge clk) begin
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        if ( io_we ) begin
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                casex (io_a)
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                        2'b10: UCSRB <= io_di;
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                        2'b11: UBRR <= io_di;
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                endcase
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        end
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end
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/* TX */
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uart_tx tx0 (clk, UBRR, UDR_TX, tx0_non_empty, tx0_txd, tx0_busy, tx0_prefetch);
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/* transmitter state changes: */
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always @(posedge clk) begin
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        if ( io_we && io_a == 2'b00 && ~tx0_non_empty ) begin
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                tx0_non_empty <= 1;
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                UDR_TX <= io_di;
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        end else if ( (tx0_non_empty & ~tx0_busy) | tx0_prefetch )
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                tx0_non_empty <= 0;
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end
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assign  txd = tx0_txd | (~tx0_busy);
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/* RX */
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wire [7:0] rx0_data;
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wire    rx0_avail;
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uart_rx rx0 (clk, UBRR, rxd, rx0_reset, rx0_data, rx0_avail);
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/* receiver state changes: */
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always @(posedge clk) begin
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        if ( io_re && io_a == 2'b00 ) begin
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                rx0_non_empty <= 0;
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                rx0_overrun   <= 0;
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        end else if ( rx0_avail && ~rx0_reset ) begin
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                UDR_RX <= rx0_data;
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                rx0_non_empty <= 1;
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                rx0_overrun   <= rx0_non_empty;
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                rx0_reset <= 1;
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        end else begin
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                rx0_reset <= 0;
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        end
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end
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/*****************************************************************************/
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/* Debug section starts here */
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`ifdef SIMULATOR
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initial begin
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        $dumpvars(1,UDR_TX,UDR_RX,UCSRB,UBRR,tx0_non_empty,tx0_busy,tx0_prefetch);
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        $dumpvars(1,rxd,rx0_non_empty,rx0_avail,rx0_data,rx0_reset,rx0_overrun);
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end
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`endif
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/* end of debug section */
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/*****************************************************************************/
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endmodule
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/*****************************************************************************/

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