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[/] [spacewire_light/] [trunk/] [bench/] [vhdl/] [streamtest_tb.vhd] - Blame information for rev 2

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1 2 jorisvr
--
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-- Test bench for spwstream.
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--
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-- Tests:
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--  * one spwstream instance with SpaceWire signals looped back to itself
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--  * sending of bytes, packets and time codes through the SpaceWire link
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--  * handling of link disabling and link disconnection
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--
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-- This test bench is intended to test the buffering logic in spwstream.
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-- It does not thoroughly verify behaviour of the receiver, transmitter,
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-- signal patterns etc. Please use spwlink_tb.vhd to test those aspects.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use work.spwpkg.all;
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entity streamtest_tb is
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end entity;
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architecture tb_arch of streamtest_tb is
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    -- Parameters.
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    constant sys_clock_freq: real   := 20.0e6;
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    component streamtest is
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        generic (
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            sysfreq:    real;
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            tickdiv:    integer range 12 to 24 := 20;
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            rximpl:     spw_implementation_type := impl_generic;
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            rxchunk:    integer range 1 to 4 := 1;
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            tximpl:     spw_implementation_type := impl_generic;
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            rxfifosize_bits: integer range 6 to 14 := 11;
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            txfifosize_bits: integer range 2 to 14 := 11 );
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        port (
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            clk:        in  std_logic;
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            rxclk:      in  std_logic;
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            txclk:      in  std_logic;
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            rst:        in  std_logic;
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            linkstart:  in  std_logic;
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            autostart:  in  std_logic;
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            linkdisable: in std_logic;
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            senddata:   in  std_logic;
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            sendtick:   in  std_logic;
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            txdivcnt:   in  std_logic_vector(7 downto 0);
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            linkstarted: out std_logic;
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            linkconnecting: out std_logic;
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            linkrun:    out std_logic;
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            linkerror:  out std_logic;
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            gotdata:    out std_logic;
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            dataerror:  out std_logic;
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            tickerror:  out std_logic;
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            spw_di:     in  std_logic;
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            spw_si:     in  std_logic;
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            spw_do:     out std_logic;
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            spw_so:     out std_logic );
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    end component;
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    signal sys_clock_enable: std_logic := '0';
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    signal sysclk:      std_logic := '0';
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    signal s_loopback:  std_logic := '0';
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    signal s_nreceived: integer := 0;
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    signal s_rst:       std_logic := '1';
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    signal s_linkstart: std_logic;
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    signal s_autostart: std_logic;
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    signal s_linkdisable: std_logic;
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    signal s_divcnt:    std_logic_vector(7 downto 0);
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    signal s_linkrun:   std_logic;
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    signal s_linkerror: std_logic;
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    signal s_gotdata:   std_logic;
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    signal s_dataerror: std_logic;
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    signal s_tickerror: std_logic;
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    signal s_spwdi:     std_logic;
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    signal s_spwsi:     std_logic;
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    signal s_spwdo:     std_logic;
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    signal s_spwso:     std_logic;
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begin
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    -- streamtest instance
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    streamtest_inst: streamtest
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        generic map (
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            sysfreq     => sys_clock_freq,
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            tickdiv     => 16,
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            rximpl      => impl_generic,
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            rxchunk     => 1,
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            tximpl      => impl_generic,
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            rxfifosize_bits => 9,
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            txfifosize_bits => 8 )
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        port map (
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            clk         => sysclk,
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            rxclk       => sysclk,
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            txclk       => sysclk,
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            rst         => s_rst,
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            linkstart   => s_linkstart,
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            autostart   => s_autostart,
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            linkdisable => s_linkdisable,
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            senddata    => '1',
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            sendtick    => '1',
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            txdivcnt    => s_divcnt,
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            linkstarted => open,
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            linkconnecting => open,
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            linkrun     => s_linkrun,
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            linkerror   => s_linkerror,
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            gotdata     => s_gotdata,
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            dataerror   => s_dataerror,
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            tickerror   => s_tickerror,
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            spw_di      => s_spwdi,
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            spw_si      => s_spwsi,
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            spw_do      => s_spwdo,
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            spw_so      => s_spwso );
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    -- Conditional loopback of SpaceWire signals.
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    s_spwdi <= s_spwdo when (s_loopback = '1') else '0';
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    s_spwsi <= s_spwso when (s_loopback = '1') else '0';
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    -- Generate system clock.
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    process is
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    begin
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        if sys_clock_enable /= '1' then
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            wait until sys_clock_enable = '1';
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        end if;
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        sysclk  <= '1';
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        wait for (0.5 sec) / sys_clock_freq;
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        sysclk  <= '0';
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        wait for (0.5 sec) / sys_clock_freq;
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    end process;
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    -- Verify that error indications remain off.
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    process is
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    begin
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        wait on s_linkerror, s_dataerror, s_tickerror;
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        assert s_dataerror = '0' report "Detected data error";
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        assert s_tickerror = '0' report "Detected time code error";
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        if s_loopback = '1' then
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            assert s_linkerror /= '1' report "Unexpected link error";
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        end if;
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    end process;
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    -- Verify that data is received regularly when the link is up.
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    process is
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    begin
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        if s_linkrun = '0' or s_gotdata = '1' then
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            wait until s_linkrun = '1' and s_gotdata = '0';
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        end if;
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        wait until s_gotdata = '1' or s_linkrun = '0' for 3 ms;
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        if s_linkrun = '1' then
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            assert s_gotdata = '1' report "Link running but no data received";
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        end if;
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    end process;
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    -- Count number of received characters.
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    process is
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    begin
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        wait until rising_edge(sysclk);
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        if s_gotdata = '1' then
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            s_nreceived <= s_nreceived + 1;
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        end if;
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    end process;
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    -- Main process.
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    process is
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        variable vline: LINE;
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    begin
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        report "Starting streamtest test bench";
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        -- Initialize.
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        s_loopback  <= '1';
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        s_rst       <= '1';
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        s_linkstart <= '0';
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        s_autostart <= '0';
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        s_linkdisable <= '0';
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        s_divcnt    <= "00000001";
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        sys_clock_enable <= '1';
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        wait for 1 us;
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        -- Test link and data transmission.
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        report "Testing txdivcnt = 1";
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        s_rst       <= '0';
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        s_linkstart <= '1';
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        wait for 100 us;
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        assert s_linkrun = '1' report "Link failed to start";
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        wait for 50 ms;
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        -- Check number of received characters.
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        write(vline, string'("Received "));
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        write(vline, s_nreceived);
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        write(vline, string'(" characters in 50 ms."));
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        writeline(output, vline);
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        assert s_nreceived > 24000 report "Too few characters received";
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        -- Test switching to different transmission rate.
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        report "Testing txdivcnt = 2";
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        s_divcnt    <= "00000010";
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        wait for 10 ms;
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        report "Testing txdivcnt = 3";
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        s_divcnt    <= "00000011";
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        wait for 10 ms;
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        -- Disable and re-enable link.
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        report "Testing link disable/re-enable";
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        s_linkdisable <= '1';
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        s_divcnt    <= "00000001";
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        wait for 2 ms;
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        s_linkdisable <= '0';
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        wait for 100 us;
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        assert s_linkrun = '1' report "Link failed to start after re-enable";
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        wait for 10 ms;
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        -- Cut and reconnect loopback wiring.
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        report "Testing physical disconnect/reconnect";
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        s_loopback  <= '0';
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        wait for 2 ms;
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        s_loopback  <= '1';
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        wait for 100 us;
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        assert s_linkrun = '1' report "Link failed to start after reconnect";
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        wait for 10 ms;
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        s_loopback  <= '0';
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        wait for 2 ms;
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        s_loopback  <= '1';
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        wait for 100 us;
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        assert s_linkrun = '1' report "Link failed to start after reconnect (2)";
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        wait for 10 ms;
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        -- Shut down.
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        s_rst   <= '1';
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        wait for 1 us;
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        sys_clock_enable <= '0';
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        write(vline, string'("Received "));
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        write(vline, s_nreceived);
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        write(vline, string'(" characters."));
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        writeline(output, vline);
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        report "Done";
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        wait;
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    end process;
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end architecture tb_arch;

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