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[/] [spacewire_light/] [trunk/] [rtl/] [vhdl/] [spwpkg.vhd] - Blame information for rev 10

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Line No. Rev Author Line
1 2 jorisvr
--
2
--  SpaceWire VHDL package
3
--
4
 
5
library ieee;
6
use ieee.std_logic_1164.all;
7
 
8
package spwpkg is
9
 
10
 
11
    -- Indicates a platform-specific implementation.
12
    type spw_implementation_type is ( impl_generic, impl_fast );
13
 
14
 
15
    -- Input signals to spwlink.
16
    type spw_link_in_type is record
17
 
18
        -- Enables automatic link start on receipt of a NULL character.
19
        autostart:  std_logic;
20
 
21
        -- Enables link start once the Ready state is reached.
22
        -- Without either "autostart" or "linkstart", the link remains in
23
        -- state Ready.
24
        linkstart:  std_logic;
25
 
26
        -- Do not start link (overrides "linkstart" and "autostart") and/or
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        -- disconnect the currently running link.
28
        linkdis:    std_logic;
29
 
30
        -- Number of bytes available in the receive buffer. Used to for
31
        -- flow-control operation. At least 8 bytes must be available
32
        -- initially, otherwise the link can not start. Values larger than 63
33
        -- are irrelevant and may be presented as 63. The available room may
34
        -- decrease by one byte due to the reception of an N-Char; in that case
35
        -- the "rxroom" signal must be updated on the clock following the clock
36
        -- on which "rxchar" is high. Under no other circumstances may "rxroom"
37
        -- be decreased.
38
        rxroom:     std_logic_vector(5 downto 0);
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40
        -- High for one clock cycle to request transmission of a TimeCode.
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        -- The request is registered inside spwxmit until it can be processed.
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        tick_in:    std_logic;
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44
        -- Control bits of the TimeCode to be sent.
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        -- Must be valid while tick_in is high.
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        ctrl_in:    std_logic_vector(1 downto 0);
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48
        -- Counter value of the TimeCode to be sent.
49
        -- Must be valid while tick_in is high.
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        time_in:    std_logic_vector(5 downto 0);
51
 
52
        -- Requests transmission of an N-Char.
53
        -- Keep this signal high until confirmed by "txack".
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        txwrite:    std_logic;
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56
        -- Control flag to be sent with the next N-Char.
57
        -- Must be valid while "txwrite" is high.
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        txflag:     std_logic;
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        -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
61
        -- Must be valid while "txwrite" is high.
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        txdata:     std_logic_vector(7 downto 0);
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    end record;
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65
 
66
    -- Output signals from spwlink.
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    type spw_link_out_type is record
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        -- High if the link state machine is currently in state Started.
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        started:    std_logic;
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        -- High if the link state machine is currently in state Connecting.
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        connecting: std_logic;
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75
        -- High if the link state machine is currently in state Run.
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        running:    std_logic;
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78
        -- Disconnect detected in state Run. Triggers a reset and reconnect.
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        -- This indication is auto-clearing.
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        errdisc:    std_logic;
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82
        -- Parity error detected in state Run. Triggers a reset and reconnect.
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        -- This indication is auto-clearing.
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        errpar:     std_logic;
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86
        -- Invalid escape sequence detected in state Run.
87
        -- Triggers a reset and reconnect; auto-clearing.
88
        erresc:     std_logic;
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90
        -- Credit error detected. Triggers a reset and reconnect.
91
        -- This indication is auto-clearing.
92
        errcred:    std_logic;
93
 
94
        -- High to confirm the transmission of an N-Char.
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        -- This is a Wishbone-style handshake signal. It has a combinatorial
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        -- dependency on "txwrite".
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        txack:      std_logic;
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99
        -- High for one clock cycle if a TimeCode was just received.
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        -- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50
101
        -- is not implemented; all received timecodes are reported.
102
        tick_out:   std_logic;
103
 
104
        -- Control bits of last received TimeCode.
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        ctrl_out:   std_logic_vector(1 downto 0);
106
 
107
        -- Counter value of last received TimeCode.
108
        time_out:   std_logic_vector(5 downto 0);
109
 
110
        -- High for one clock cycle if an N-Char (data byte or EOP or EEP) was
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        -- just received. The data bits must be accepted immediately from
112
        -- "rxflag" and "rxdata".
113
        rxchar:     std_logic;
114
 
115
        -- High if the received character is EOP or EEP, low if it is a data
116
        -- byte. Valid when "rxchar" is high.
117
        rxflag:     std_logic;
118
 
119
        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
120
        -- Valid when "rxchar" is high.
121
        rxdata:     std_logic_vector(7 downto 0);
122
    end record;
123
 
124
 
125
    -- Output signals from spwrecv to spwlink.
126
    type spw_recv_out_type is record
127
 
128
        -- High if at least one signal change was seen since enable.
129
        -- Resets to low when rxen is low.
130
        gotbit:     std_logic;
131
 
132
        -- High if at least one valid NULL pattern was detected since enable.
133
        -- Resets to low when rxen is low.
134
        gotnull:    std_logic;
135
 
136
        -- High for one clock cycle if an FCT token was just received.
137
        gotfct:     std_logic;
138
 
139
        -- High for one clock cycle if a TimeCode was just received.
140
        tick_out:   std_logic;
141
 
142
        -- Control bits of last received TimeCode.
143
        ctrl_out:   std_logic_vector(1 downto 0);
144
 
145
        -- Counter value of last received TimeCode.
146
        time_out:   std_logic_vector(5 downto 0);
147
 
148
        -- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received.
149
        rxchar:     std_logic;
150
 
151
        -- High if rxchar is high and the received character is EOP or EEP.
152
        -- Low if rxchar is high and the received character is a data byte.
153
        rxflag:     std_logic;
154
 
155
        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
156
        -- Valid when "rxchar" is high.
157
        rxdata:     std_logic_vector(7 downto 0);
158
 
159
        -- Disconnect detected (after a signal change was seen).
160
        -- Resets to low when rxen is low or when a signal change is seen.
161
        errdisc:    std_logic;
162
 
163
        -- Parity error detected (after a valid NULL pattern was seen).
164
        -- Sticky; resets to low when rxen is low.
165
        errpar:     std_logic;
166
 
167
        -- Escape sequence error detected (after a valid NULL pattern was seen).
168
        -- Sticky; resets to low when rxen is low.
169
        erresc:     std_logic;
170
    end record;
171
 
172
 
173
    -- Input signals to spwxmit from spwlink.
174
    type spw_xmit_in_type is record
175
 
176
        -- High to enable transmitter; low to disable and reset transmitter.
177
        txen:       std_logic;
178
 
179
        -- Indicates that only NULL characters may be transmitted.
180
        stnull:     std_logic;
181
 
182
        -- Indicates that only NULL and/or FCT characters may be transmitted.
183
        stfct:      std_logic;
184
 
185
        -- Requests transmission of an FCT character.
186
        -- Keep this signal high until confirmed by "fctack".
187
        fct_in:     std_logic;
188
 
189
        -- High for one clock cycle to request transmission of a TimeCode.
190
        -- The request is registered inside spwxmit until it can be processed.
191
        tick_in:    std_logic;
192
 
193
        -- Control bits of the TimeCode to be sent.
194
        -- Must be valid while "tick_in" is high.
195
        ctrl_in:    std_logic_vector(1 downto 0);
196
 
197
        -- Counter value of the TimeCode to be sent.
198
        -- Must be valid while "tick_in" is high.
199
        time_in:    std_logic_vector(5 downto 0);
200
 
201
        -- Request transmission of an N-Char.
202
        -- Keep this signal high until confirmed by "txack".
203
        txwrite:    std_logic;
204
 
205
        -- Control flag to be sent with the next N-Char.
206
        -- Must be valid while "txwrite" is high.
207
        txflag:     std_logic;
208
 
209
        -- Byte to send, or "00000000" for EOP or "00000001" for EEP.
210
        -- Must be valid while "txwrite" is high.
211
        txdata:     std_logic_vector(7 downto 0);
212
    end record;
213
 
214
 
215
    -- Output signals from spwxmit to spwlink.
216
    type spw_xmit_out_type is record
217
 
218
        -- High to confirm transmission on an FCT character.
219
        -- This is a Wishbone-style handshaking signal; it is combinatorially
220
        -- dependent on "fct_in".
221
        fctack:     std_logic;
222
 
223
        -- High to confirm transmission of an N-Char.
224
        -- This is a Wishbone-style handshaking signal; it is combinatorially
225
        -- dependent on both "fct_in" and "txwrite".
226
        txack:      std_logic;
227
    end record;
228
 
229
 
230
    -- Character-stream interface
231
    component spwstream is
232
        generic (
233
            sysfreq:        real;                           -- clk freq in Hz
234 3 jorisvr
            txclkfreq:      real := 0.0;                    -- txclk freq in Hz
235 2 jorisvr
            rximpl:         spw_implementation_type := impl_generic;
236
            rxchunk:        integer range 1 to 4 := 1;      -- max bits per clk
237
            tximpl:         spw_implementation_type := impl_generic;
238
            rxfifosize_bits: integer range 6 to 14 := 11;   -- rx fifo size
239
            txfifosize_bits: integer range 2 to 14 := 11    -- tx fifo size
240
        );
241
        port (
242
            clk:        in  std_logic;          -- system clock
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            rxclk:      in  std_logic;          -- receiver sample clock
244
            txclk:      in  std_logic;          -- transmit clock
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            rst:        in  std_logic;          -- synchronous reset
246
            autostart:  in  std_logic;          -- automatic link start
247
            linkstart:  in  std_logic;          -- forced link start
248
            linkdis:    in  std_logic;          -- stop link
249
            txdivcnt:   in  std_logic_vector(7 downto 0);   -- tx scale factor
250
            tick_in:    in  std_logic;          -- request timecode xmit
251
            ctrl_in:    in  std_logic_vector(1 downto 0);
252
            time_in:    in  std_logic_vector(5 downto 0);
253
            txwrite:    in  std_logic;          -- request character xmit
254
            txflag:     in  std_logic;          -- control flag of tx char
255
            txdata:     in  std_logic_vector(7 downto 0);
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            txrdy:      out std_logic;          -- room in tx fifo
257
            txhalff:    out std_logic;          -- tx fifo half full
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            tick_out:   out std_logic;          -- timecode received
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            ctrl_out:   out std_logic_vector(1 downto 0);
260
            time_out:   out std_logic_vector(5 downto 0);
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            rxvalid:    out std_logic;          -- rx fifo not empty
262
            rxhalff:    out std_logic;          -- rx fifo half full
263
            rxflag:     out std_logic;          -- control flag of rx char
264
            rxdata:     out std_logic_vector(7 downto 0);
265
            rxread:     in  std_logic;          -- accept rx character
266
            started:    out std_logic;          -- link in Started state
267
            connecting: out std_logic;          -- link in Connecting state
268
            running:    out std_logic;          -- link in Run state
269
            errdisc:    out std_logic;          -- disconnect error
270
            errpar:     out std_logic;          -- parity error
271
            erresc:     out std_logic;          -- escape error
272
            errcred:    out std_logic;          -- credit error
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            spw_di:     in  std_logic;
274
            spw_si:     in  std_logic;
275
            spw_do:     out std_logic;
276
            spw_so:     out std_logic
277
        );
278
    end component spwstream;
279
 
280
 
281
    -- Link Level Interface
282
    component spwlink is
283
        generic (
284
            reset_time:      integer        -- reset time in clocks (6.4 us)
285
        );
286
        port (
287
            clk:        in  std_logic;      -- system clock
288
            rst:        in  std_logic;      -- synchronous reset (active-high)
289
            linki:      in  spw_link_in_type;
290
            linko:      out spw_link_out_type;
291
            rxen:       out std_logic;
292
            recvo:      in  spw_recv_out_type;
293
            xmiti:      out spw_xmit_in_type;
294
            xmito:      in  spw_xmit_out_type
295
        );
296
    end component spwlink;
297
 
298
 
299
    -- Receiver
300
    component spwrecv is
301
        generic (
302
            disconnect_time: integer range 1 to 255;    -- disconnect period in system clock cycles
303
            rxchunk:        integer range 1 to 4        -- nr of bits per system clock
304
        );
305
        port (
306
            clk:        in  std_logic;      -- system clock
307
            rxen:       in  std_logic;      -- receiver enabled
308
            recvo:      out spw_recv_out_type;
309
            inact:      in  std_logic;
310
            inbvalid:   in  std_logic;
311
            inbits:     in  std_logic_vector(rxchunk-1 downto 0)
312
        );
313
    end component spwrecv;
314
 
315
 
316
    -- Transmitter (generic implementation)
317
    component spwxmit is
318
        port (
319
            clk:        in  std_logic;      -- system clock
320
            rst:        in  std_logic;      -- synchronous reset (active-high)
321
            divcnt:     in  std_logic_vector(7 downto 0);
322
            xmiti:      in  spw_xmit_in_type;
323
            xmito:      out spw_xmit_out_type;
324
            spw_do:     out std_logic;      -- tx data to SPW bus
325
            spw_so:     out std_logic       -- tx strobe to SPW bus
326
        );
327
    end component spwxmit;
328
 
329
 
330
    -- Transmitter (separate tx clock domain)
331
    component spwxmit_fast is
332
        port (
333
            clk:        in  std_logic;      -- system clock
334
            txclk:      in  std_logic;      -- transmit clock
335
            rst:        in  std_logic;      -- synchronous reset (active-high)
336
            divcnt:     in  std_logic_vector(7 downto 0);
337
            xmiti:      in  spw_xmit_in_type;
338
            xmito:      out spw_xmit_out_type;
339
            spw_do:     out std_logic;      -- tx data to SPW bus
340
            spw_so:     out std_logic       -- tx strobe to SPW bus
341
        );
342
    end component spwxmit_fast;
343
 
344
 
345
    -- Front-end for SpaceWire Receiver (generic implementation)
346
    component spwrecvfront_generic is
347
        port (
348
            clk:        in  std_logic;      -- system clock
349
            rxen:       in  std_logic;      -- high to enable receiver
350
            inact:      out std_logic;      -- high if activity on input
351
            inbvalid:   out std_logic;      -- high if inbits contains a valid received bit
352
            inbits:     out std_logic_vector(0 downto 0);   -- received bit
353
            spw_di:     in  std_logic;      -- Data In signal from SpaceWire bus
354
            spw_si:     in  std_logic       -- Strobe In signal from SpaceWire bus
355
        );
356
    end component spwrecvfront_generic;
357
 
358
 
359
    -- Front-end for SpaceWire Receiver (separate rx clock domain)
360
    component spwrecvfront_fast is
361
        generic (
362
            rxchunk:        integer range 1 to 4    -- max number of bits per system clock
363
        );
364
        port (
365
            clk:        in  std_logic;      -- system clock
366
            rxclk:      in  std_logic;      -- sample clock (DDR)
367
            rxen:       in  std_logic;      -- high to enable receiver
368
            inact:      out std_logic;      -- high if activity on input
369
            inbvalid:   out std_logic;      -- high if inbits contains a valid group of received bits
370
            inbits:     out std_logic_vector(rxchunk-1 downto 0);    -- received bits
371
            spw_di:     in  std_logic;      -- Data In signal from SpaceWire bus
372
            spw_si:     in  std_logic       -- Strobe In signal from SpaceWire bus
373
        );
374
    end component spwrecvfront_fast;
375
 
376
 
377 7 jorisvr
    -- Synchronous two-port memory.
378 2 jorisvr
    component spwram is
379
        generic (
380
            abits:      integer;
381
            dbits:      integer );
382
        port (
383
            rclk:       in  std_logic;
384
            wclk:       in  std_logic;
385
            ren:        in  std_logic;
386
            raddr:      in  std_logic_vector(abits-1 downto 0);
387
            rdata:      out std_logic_vector(dbits-1 downto 0);
388
            wen:        in  std_logic;
389
            waddr:      in  std_logic_vector(abits-1 downto 0);
390
            wdata:      in  std_logic_vector(dbits-1 downto 0) );
391
    end component spwram;
392
 
393 7 jorisvr
 
394
    --  Double flip-flop synchronizer.
395
    component syncdff is
396
        port (
397
            clk:        in  std_logic;          -- clock (destination domain)
398
            rst:        in  std_logic;          -- asynchronous reset, active-high
399
            di:         in  std_logic;          -- input data
400
            do:         out std_logic );        -- output data
401
    end component syncdff;
402
 
403 2 jorisvr
end package;

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