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[/] [spacewire_light/] [trunk/] [sim/] [spwamba_leon3/] [spwamba_tb.vhd] - Blame information for rev 5

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1 5 jorisvr
--
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-- Test Bench for SpaceWire AMBA interface.
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--
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-- Instantiate a minimal LEON3 system with SPWAMBA core.
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-- At the start of the simulation, a software image is loaded into memory
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-- from an external file spwamba_test.srec.
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--
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library ieee;
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use ieee.std_logic_1164.all, ieee.numeric_std.all;
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use std.textio.all;
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library techmap;
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use techmap.gencomp.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use work.spwpkg.all;
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use work.spwambapkg.all;
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entity spwamba_tb is
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end spwamba_tb;
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architecture tb_arch of spwamba_tb is
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    -- 40 MHz system clock
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    constant sys_clock_freq: real := 40.0e6;
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    signal clkm:    std_ulogic := '0';
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    signal rstn:    std_ulogic := '0';
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    signal apbi:    apb_slv_in_type;
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    signal apbo:    apb_slv_out_vector := (others => apb_none);
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    signal ahbsi:   ahb_slv_in_type;
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    signal ahbso:   ahb_slv_out_vector := (others => ahbs_none);
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    signal ahbmi:   ahb_mst_in_type;
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    signal ahbmo:   ahb_mst_out_vector := (others => ahbm_none);
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    signal irqi:    irq_in_vector(0 to 0);
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    signal irqo:    irq_out_vector(0 to 0);
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    signal dbgi:    l3_debug_in_type;
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    signal dbgo:    l3_debug_out_type;
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    signal uarti:   uart_in_type;
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    signal uarto:   uart_out_type;
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    signal gpti:    gptimer_in_type;
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    signal gpto:    gptimer_out_type;
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    signal spw_tick_in: std_logic;
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    signal spw_di:      std_logic;
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    signal spw_si:      std_logic;
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    signal spw_do:      std_logic;
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    signal spw_so:      std_logic;
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    component ahbram_loadfile is
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        generic (
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            hindex: integer;
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            haddr:  integer;
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            hmask:  integer := 16#fff#;
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            abits:  integer range 10 to 24;
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            fname:  string );
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        port (
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            rstn:   in  std_logic;
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            clk:    in  std_logic;
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            ahbi:   in  ahb_slv_in_type;
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            ahbo:   out ahb_slv_out_type );
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    end component;
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begin
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    --
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    -- Reset and clock generation.
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    --
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    process is
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    begin
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        -- Reset (APBUART needs 2 reset cycles)
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        rstn    <= '0';
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        for i in 0 to 1 loop
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            wait for (0.5 sec) / sys_clock_freq;
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            clkm    <= '1';
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            wait for (0.5 sec) / sys_clock_freq;
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            clkm    <= '0';
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        end loop;
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        rstn    <= '1';
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        report "Start simulation";
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        -- Main loop
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        loop
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            wait for (0.5 sec) / sys_clock_freq;
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            clkm    <= '1';
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            wait for (0.5 sec) / sys_clock_freq;
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            clkm    <= '0';
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            -- Check LEON3 error signal.
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            assert dbgo.error = '1' report "LEON3 in error mode";
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            exit when dbgo.error = '0';
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            -- End simulation when LEON3 is in power down mode.
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            exit when dbgo.pwd = '1';
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        end loop;
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        -- End simulation.
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        report "End of simulation";
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        wait;
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    end process;
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    --
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    -- AHB controller.
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    --
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    ahb0: ahbctrl
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        generic map (defmast => 0, split => 0, rrobin => 1,
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                     ioaddr => 16#fff#, ioen => 0, nahbm => 2, nahbs => 4)
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        port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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    --
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    -- LEON3 processor.
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    --
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    cpu: leon3s
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        generic map (hindex => 0, fabtech => inferred, memtech => inferred,
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                     nwindows => 8, dsu => 0, fpu => 0, v8 => 0, cp => 0, mac => 0,
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                     pclow => 2, notag => 0, nwp => 4,
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                     icen => 1, irepl => 0, isets => 1, ilinesize => 8, isetsize => 4, isetlock => 0,
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                     dcen => 0, drepl => 0, dsets => 1, dlinesize => 4, dsetsize => 4, dsetlock => 0, dsnoop => 1,
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                     ilram => 0, ilramsize => 1, ilramstart => 16#8E#,
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                     dlram => 0, dlramsize => 1, dlramstart => 16#8F#,
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                     mmuen => 0, itlbnum => 8, dtlbnum => 8, tlb_type => 2, tlb_rep => 0,
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                     lddel => 1, disas => 0, tbuf => 2, pwd => 2, svt => 1,
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                     rstaddr => 16#40000#, smp => 0, cached => 0, scantest => 0, mmupgsz => 4, bp => 1)
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        port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi, dbgo);
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    dbgi <= (dsuen => '0', denable => '0', dbreak => '0', step => '0', halt => '0', reset => '0', dwrite => '0', daddr => (others => '0'), ddata => (others => '0'), btrapa => '0', btrape => '0', berror => '0',bwatch => '0', bsoft => '0', tenable => '0', timer => (others => '0'));
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    --
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    -- APB bridge.
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    --
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    apb0: apbctrl
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        generic map (hindex => 1, haddr => 16#800#, nslaves => 8)
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        port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
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    --
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    -- Console UART.
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    --
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    uart1: apbuart
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        generic map (pindex => 1, paddr => 1, pirq => 2, console => 1, fifosize => 1)
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        port map (rstn, clkm, apbi, apbo(1), uarti, uarto);
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    uarti.rxd       <= '0';
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    uarti.ctsn      <= '0';
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    uarti.extclk    <= '0';
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    --
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    -- Interrupt controller.
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    --
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    irqctrl0 : irqmp
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        generic map (pindex => 2, paddr => 2, ncpu => 1)
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        port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
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    --
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    -- Timer.
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    --
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    timer0: gptimer
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        generic map (pindex => 3, paddr => 3, pirq => 8, sepirq => 0,
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                     sbits => 8, ntimers => 2, nbits => 32, wdog => 0)
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        port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
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    gpti.dhalt  <= '0';
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    gpti.extclk <= '0';
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    --
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    -- AHB RAM (128 kByte)
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    --
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    ahbram0: ahbram_loadfile
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        generic map (hindex => 3, haddr => 16#400#, abits => 17, fname => "spwamba_test.srec")
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        port map (rstn, clkm, ahbsi, ahbso(3));
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    --
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    -- SpaceWire Light
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    --
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    spw0: spwamba
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        generic map (
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            tech        => inferred,
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            hindex      => 1,
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            pindex      => 4,
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            paddr       => 4,
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            pirq        => 4,
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            sysfreq     => sys_clock_freq,
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            txclkfreq   => sys_clock_freq,
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            rximpl      => impl_generic,
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            rxchunk     => 1,
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            tximpl      => impl_generic,
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            timecodegen => true,
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            rxfifosize  => 7,
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            txfifosize  => 6,
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            desctablesize => 5,
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            maxburst    => 3 )
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        port map (
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            clk     => clkm,
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            rxclk   => clkm,
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            txclk   => clkm,
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            rstn    => rstn,
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            apbi    => apbi,
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            apbo    => apbo(4),
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            ahbi    => ahbmi,
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            ahbo    => ahbmo(1),
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            tick_in => spw_tick_in,
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            spw_di  => spw_di,
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            spw_si  => spw_si,
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            spw_do  => spw_do,
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            spw_so  => spw_so );
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    -- Loopback SpaceWire signals.
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    -- Loopback can be controlled from software through the RXEN bit of
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    -- the APBUART control register.
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    spw_di  <= spw_do when (uarto.rxen = '1') else '0';
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    spw_si  <= spw_so when (uarto.rxen = '1') else '0';
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    -- Take external timecode tick from second GPTIMER.
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    spw_tick_in <= gpto.tick(2);
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end tb_arch;

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