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1 5 jorisvr
-----------------------------------------------------------------------------
2
--  LEON3 Demonstration design
3
--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4
--
5
--  Modified by Joris van Rantwijk for use with SpaceWire Light.
6
------------------------------------------------------------------------------
7
--  This program is free software; you can redistribute it and/or modify
8
--  it under the terms of the GNU General Public License as published by
9
--  the Free Software Foundation; either version 2 of the License, or
10
--  (at your option) any later version.
11
--
12
--  This program is distributed in the hope that it will be useful,
13
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
14
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
--  GNU General Public License for more details.
16
--
17
--  You should have received a copy of the GNU General Public License
18
--  along with this program; if not, write to the Free Software
19
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
20
------------------------------------------------------------------------------
21
 
22
 
23
library ieee;
24
use ieee.std_logic_1164.all;
25
library grlib, techmap;
26
use grlib.amba.all;
27
use grlib.stdlib.all;
28
use techmap.gencomp.all;
29
library gaisler;
30
use gaisler.memctrl.all;
31
use gaisler.leon3.all;
32
use gaisler.uart.all;
33
use gaisler.misc.all;
34
use gaisler.can.all;
35
use gaisler.net.all;
36
use gaisler.jtag.all;
37
use gaisler.spacewire.all;
38
use gaisler.grusb.all;
39
use gaisler.ata.all;
40
 
41
library esa;
42
use esa.memoryctrl.all;
43
 
44
library unisim;
45
use unisim.vcomponents.DCM;
46
 
47
use work.config.all;
48
use work.spwpkg.all;
49
use work.spwambapkg.all;
50
 
51
entity leon3mp is
52
  generic (
53
    fabtech       : integer := CFG_FABTECH;
54
    memtech       : integer := CFG_MEMTECH;
55
    padtech       : integer := CFG_PADTECH;
56
    clktech       : integer := CFG_CLKTECH;
57
    disas         : integer := CFG_DISAS;       -- Enable disassembly to console
58
    dbguart       : integer := CFG_DUART;       -- Print UART on console
59
    pclow         : integer := CFG_PCLOW
60
  );
61
  port (
62
    resetn        : in  std_ulogic;
63
    clk           : in  std_ulogic;     -- 50 MHz main clock
64
    clk3          : in  std_ulogic;     -- 25 MHz ethernet clock
65
    pllref        : in  std_ulogic;
66
    errorn        : out std_ulogic;
67
    wdogn         : out std_ulogic;
68
    address       : out std_logic_vector(27 downto 0);
69
    data          : inout std_logic_vector(31 downto 0);
70
    ramsn         : out std_logic_vector (4 downto 0);
71
    ramoen        : out std_logic_vector (4 downto 0);
72
    rwen          : out std_logic_vector (3 downto 0);
73
    oen           : out std_ulogic;
74
    writen        : out std_ulogic;
75
    read          : out std_ulogic;
76
    iosn          : out std_ulogic;
77
    bexcn         : in  std_ulogic;                     -- DSU rx data
78
    brdyn         : in  std_ulogic;                     -- DSU rx data
79
    romsn         : out std_logic_vector (1 downto 0);
80
    sdclk         : out std_ulogic;
81
    sdcsn         : out std_logic_vector (1 downto 0);    -- sdram chip select
82
    sdwen         : out std_ulogic;                       -- sdram write enable
83
    sdrasn        : out std_ulogic;                       -- sdram ras
84
    sdcasn        : out std_ulogic;                       -- sdram cas
85
    sddqm         : out std_logic_vector (3 downto 0);    -- sdram dqm
86
 
87
    dsuen         : in std_ulogic;
88
    dsubre        : in std_ulogic;
89
    dsuact        : out std_ulogic;
90
 
91
    txd1          : out std_ulogic;                     -- UART1 tx data
92
    rxd1          : in  std_ulogic;                     -- UART1 rx data
93
    ctsn1         : in  std_ulogic;                     -- UART1 rx data
94
    rtsn1         : out std_ulogic;                     -- UART1 rx data
95
    txd2          : out std_ulogic;                     -- UART2 tx data
96
    rxd2          : in  std_ulogic;                     -- UART2 rx data
97
    ctsn2         : in  std_ulogic;                     -- UART1 rx data
98
    rtsn2         : out std_ulogic;                     -- UART1 rx data
99
 
100
    pio           : inout std_logic_vector(17 downto 0);         -- I/O port
101
 
102
    emdio         : inout std_logic;            -- ethernet PHY interface
103
    etx_clk       : in std_ulogic;
104
    erx_clk       : in std_ulogic;
105
    erxd          : in std_logic_vector(3 downto 0);
106
    erx_dv        : in std_ulogic;
107
    erx_er        : in std_ulogic;
108
    erx_col       : in std_ulogic;
109
    erx_crs       : in std_ulogic;
110
    emdint        : in std_ulogic;
111
    etxd          : out std_logic_vector(3 downto 0);
112
    etx_en        : out std_ulogic;
113
    etx_er        : out std_ulogic;
114
    emdc          : out std_ulogic;
115
 
116
    ps2clk        : inout std_logic_vector(1 downto 0);
117
    ps2data       : inout std_logic_vector(1 downto 0);
118
 
119
    vid_clock     : out std_ulogic;
120
    vid_blankn    : out std_ulogic;
121
    vid_syncn     : out std_ulogic;
122
    vid_hsync     : out std_ulogic;
123
    vid_vsync     : out std_ulogic;
124
    vid_r         : out std_logic_vector(7 downto 0);
125
    vid_g         : out std_logic_vector(7 downto 0);
126
    vid_b         : out std_logic_vector(7 downto 0);
127
 
128
    spw_clk       : in  std_ulogic;
129
    spw_rxdp      : in  std_logic_vector(0 to 2);
130
    spw_rxdn      : in  std_logic_vector(0 to 2);
131
    spw_rxsp      : in  std_logic_vector(0 to 2);
132
    spw_rxsn      : in  std_logic_vector(0 to 2);
133
    spw_txdp      : out std_logic_vector(0 to 2);
134
    spw_txdn      : out std_logic_vector(0 to 2);
135
    spw_txsp      : out std_logic_vector(0 to 2);
136
    spw_txsn      : out std_logic_vector(0 to 2);
137
 
138
    usb_clkout    : in std_ulogic;
139
    usb_d         : inout std_logic_vector(15 downto 0);
140
    usb_linestate : in std_logic_vector(1 downto 0);
141
    usb_opmode    : out std_logic_vector(1 downto 0);
142
    usb_reset     : out std_ulogic;
143
    usb_rxactive  : in std_ulogic;
144
    usb_rxerror   : in std_ulogic;
145
    usb_rxvalid   : in std_ulogic;
146
    usb_suspend   : out std_ulogic;
147
    usb_termsel   : out std_ulogic;
148
    usb_txready   : in std_ulogic;
149
    usb_txvalid   : out std_ulogic;
150
    usb_validh    : inout std_ulogic;
151
    usb_xcvrsel   : out std_ulogic;
152
    usb_vbus      : in std_ulogic;
153
 
154
    ata_rstn  : out std_logic;
155
    ata_data  : inout std_logic_vector(15 downto 0);
156
    ata_da    : out std_logic_vector(2 downto 0);
157
    ata_cs0   : out std_logic;
158
    ata_cs1   : out std_logic;
159
    ata_dior  : out std_logic;
160
    ata_diow  : out std_logic;
161
    ata_iordy : in std_logic;
162
    ata_intrq : in std_logic;
163
    ata_dmarq : in std_logic;
164
    ata_dmack : out std_logic;
165
    --ata_dasp  : in std_logic
166
    ata_csel  : out std_logic
167
 
168
        );
169
end;
170
 
171
architecture rtl of leon3mp is
172
 
173
attribute syn_netlist_hierarchy : boolean;
174
attribute syn_netlist_hierarchy of rtl : architecture is false;
175
 
176
constant blength : integer := 12;
177
constant fifodepth : integer := 8;
178
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
179
        CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
180
        CFG_ATA+CFG_GRUSBDC;
181
 
182
signal vcc, gnd   : std_logic_vector(4 downto 0);
183
signal memi  : memory_in_type;
184
signal memo  : memory_out_type;
185
signal wpo   : wprot_out_type;
186
signal sdi   : sdctrl_in_type;
187
signal sdo   : sdram_out_type;
188
signal sdo2, sdo3 : sdctrl_out_type;
189
 
190
signal apbi  : apb_slv_in_type;
191
signal apbo  : apb_slv_out_vector := (others => apb_none);
192
signal ahbsi : ahb_slv_in_type;
193
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
194
signal ahbmi : ahb_mst_in_type;
195
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
196
 
197
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
198
signal cgi, cgi2   : clkgen_in_type;
199
signal cgo, cgo2   : clkgen_out_type;
200
signal u1i, u2i, dui : uart_in_type;
201
signal u1o, u2o, duo : uart_out_type;
202
 
203
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
204
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
205
 
206
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
207
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
208
 
209
signal dsui : dsu_in_type;
210
signal dsuo : dsu_out_type;
211
 
212
signal ethi, ethi1, ethi2 : eth_in_type;
213
signal etho, etho1, etho2 : eth_out_type;
214
 
215
signal gpti : gptimer_in_type;
216
signal gpto : gptimer_out_type;
217
 
218
signal gpioi : gpio_in_type;
219
signal gpioo : gpio_out_type;
220
 
221
signal can_lrx, can_ltx   : std_logic_vector(0 to 7);
222
 
223
signal lclk, rst, ndsuact, wdogl : std_ulogic;
224
signal tck, tckn, tms, tdi, tdo : std_ulogic;
225
 
226
signal ethclk : std_ulogic;
227
 
228
signal kbdi  : ps2_in_type;
229
signal kbdo  : ps2_out_type;
230
signal moui  : ps2_in_type;
231
signal mouo  : ps2_out_type;
232
signal vgao  : apbvga_out_type;
233
 
234
constant BOARD_FREQ : integer := 50000;   -- input frequency in KHz
235
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;  -- cpu frequency in KHz
236
constant IOAEN : integer := CFG_CAN + CFG_ATA + CFG_GRUSBDC;
237
 
238
signal stati : ahbstat_in_type;
239
 
240
signal spw_clkl   : std_ulogic;
241
signal spw_tick_in: std_logic;
242
signal spw_di: std_logic;
243
signal spw_si: std_logic;
244
signal spw_do: std_logic;
245
signal spw_so: std_logic;
246
 
247
signal uclk : std_ulogic;
248
signal usbi : grusb_in_type;
249
signal usbo : grusb_out_type;
250
 
251
signal idei : ata_in_type;
252
signal ideo : ata_out_type;
253
 
254
constant SPW_LOOP_BACK : integer := 0;
255
 
256
signal dac_clk, video_clk, clk50 : std_logic;  -- signals to vga_clkgen.
257
signal clk_sel : std_logic_vector(1 downto 0);
258
 
259
attribute keep : boolean;
260
attribute syn_keep : boolean;
261
attribute syn_preserve : boolean;
262
attribute syn_keep of clk50 : signal is true;
263
attribute syn_preserve of clk50 : signal is true;
264
attribute keep of clk50 : signal is true;
265
attribute syn_keep of video_clk : signal is true;
266
attribute syn_preserve of video_clk : signal is true;
267
attribute keep of video_clk : signal is true;
268
attribute keep of spw_clkl : signal is true;
269
 
270
begin
271
 
272
----------------------------------------------------------------------
273
---  Reset and Clock generation  -------------------------------------
274
----------------------------------------------------------------------
275
 
276
  vcc <= (others => '1'); gnd <= (others => '0');
277
  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
278
 
279
  pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
280
  ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
281
  clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
282
  clkgen0 : clkgen              -- clock generator
283
    generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
284
        CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
285
    port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
286
 
287
  sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
288
        port map (sdclk, sdclkl);
289
 
290
  resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
291
  rst0 : rstgen                 -- reset generator
292
  port map (rst, clkm, cgo.clklock, rstn, rstraw);
293
 
294
----------------------------------------------------------------------
295
---  AHB CONTROLLER --------------------------------------------------
296
----------------------------------------------------------------------
297
 
298
  ahb0 : ahbctrl                -- AHB arbiter/multiplexer
299
  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
300
        rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
301
        ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
302
  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
303
 
304
----------------------------------------------------------------------
305
---  LEON3 processor and DSU -----------------------------------------
306
----------------------------------------------------------------------
307
 
308
  l3 : if CFG_LEON3 = 1 generate
309
    cpu : for i in 0 to CFG_NCPU-1 generate
310
      u0 : leon3s                       -- LEON3 processor      
311
      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
312
        0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
313
        CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
314
        CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
315
        CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
316
        CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
317
        CFG_MMU_PAGE, CFG_BP)
318
      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
319
                irqi(i), irqo(i), dbgi(i), dbgo(i));
320
    end generate;
321
    errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
322
 
323
    dsugen : if CFG_DSU = 1 generate
324
      dsu0 : dsu3                       -- LEON3 Debug Support Unit
325
      generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
326
         ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
327
      port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
328
      dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
329
      dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
330
      dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
331
      ndsuact <= not dsuo.active;
332
    end generate;
333
  end generate;
334
  nodsu : if CFG_DSU = 0 generate
335
    dsuo.tstop <= '0'; dsuo.active <= '0';
336
  end generate;
337
 
338
  dcomgen : if CFG_AHB_UART = 1 generate
339
    dcom0: ahbuart              -- Debug UART
340
    generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
341
    port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
342
    dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
343
    dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
344
  end generate;
345
  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
346
 
347
  ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
348
    ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
349
      port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
350
               open, open, open, open, open, open, open, gnd(0));
351
  end generate;
352
 
353
----------------------------------------------------------------------
354
---  Memory controllers ----------------------------------------------
355
----------------------------------------------------------------------
356
 
357
  memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
358
  brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
359
  bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
360
 
361
  mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
362
        paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
363
        ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
364
        invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
365
        pageburst => CFG_MCTRL_PAGE)
366
  port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
367
  sdpads : if CFG_MCTRL_SDEN = 1 generate               -- SDRAM controller
368
      sdwen_pad : outpad generic map (tech => padtech)
369
           port map (sdwen, sdo.sdwen);
370
      sdras_pad : outpad generic map (tech => padtech)
371
           port map (sdrasn, sdo.rasn);
372
      sdcas_pad : outpad generic map (tech => padtech)
373
           port map (sdcasn, sdo.casn);
374
      sddqm_pad : outpadv generic map (width =>4, tech => padtech)
375
           port map (sddqm, sdo.dqm(3 downto 0));
376
  end generate;
377
  sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
378
           port map (sdcsn, sdo.sdcsn);
379
 
380
  addr_pad : outpadv generic map (width => 28, tech => padtech)
381
        port map (address, memo.address(27 downto 0));
382
  rams_pad : outpadv generic map (width => 5, tech => padtech)
383
        port map (ramsn, memo.ramsn(4 downto 0));
384
  roms_pad : outpadv generic map (width => 2, tech => padtech)
385
        port map (romsn, memo.romsn(1 downto 0));
386
  oen_pad  : outpad generic map (tech => padtech)
387
        port map (oen, memo.oen);
388
  rwen_pad : outpadv generic map (width => 4, tech => padtech)
389
        port map (rwen, memo.wrn);
390
  roen_pad : outpadv generic map (width => 5, tech => padtech)
391
        port map (ramoen, memo.ramoen(4 downto 0));
392
  wri_pad  : outpad generic map (tech => padtech)
393
        port map (writen, memo.writen);
394
  read_pad : outpad generic map (tech => padtech)
395
        port map (read, memo.read);
396
  iosn_pad : outpad generic map (tech => padtech)
397
        port map (iosn, memo.iosn);
398
  bdr : for i in 0 to 3 generate
399
      data_pad : iopadv generic map (tech => padtech, width => 8)
400
      port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
401
        memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
402
  end generate;
403
 
404
----------------------------------------------------------------------
405
---  APB Bridge and various periherals -------------------------------
406
----------------------------------------------------------------------
407
 
408
  apb0 : apbctrl                                -- AHB/APB bridge
409
  generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
410
  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
411
 
412
  ua1 : if CFG_UART1_ENABLE /= 0 generate
413
    uart1 : apbuart                     -- UART 1
414
    generic map (pindex => 1, paddr => 1,  pirq => 2, console => dbguart,
415
        fifosize => CFG_UART1_FIFO)
416
    port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
417
    u1i.extclk <= '0';
418
    rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
419
    txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
420
    cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
421
    rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
422
  end generate;
423
  noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
424
 
425
  ua2 : if CFG_UART2_ENABLE /= 0 generate
426
    uart2 : apbuart                     -- UART 2
427
    generic map (pindex => 9, paddr => 9,  pirq => 3, fifosize => CFG_UART2_FIFO)
428
    port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
429
    u2i.extclk <= '0';
430
    rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
431
    txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
432
    cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
433
    rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
434
  end generate;
435
  noua1 : if CFG_UART2_ENABLE = 0 generate
436
    apbo(9) <= apb_none;  rtsn2 <= '0';
437
  end generate;
438
 
439
  irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
440
    irqctrl0 : irqmp                    -- interrupt controller
441
    generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
442
    port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
443
  end generate;
444
  irq3 : if CFG_IRQ3_ENABLE = 0 generate
445
    x : for i in 0 to CFG_NCPU-1 generate
446
      irqi(i).irl <= "0000";
447
    end generate;
448
    apbo(2) <= apb_none;
449
  end generate;
450
 
451
  gpt : if CFG_GPT_ENABLE /= 0 generate
452
    timer0 : gptimer                    -- timer unit
453
    generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
454
        sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
455
        nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
456
    port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
457
    gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
458
  end generate;
459
  wden : if CFG_GPT_WDOGEN /= 0 generate
460
    wdogl <= gpto.wdogn or not rstn;
461
    wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
462
  end generate;
463
  wddis : if CFG_GPT_WDOGEN = 0 generate
464
    wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
465
  end generate;
466
 
467
  nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
468
 
469
  kbd : if CFG_KBD_ENABLE /= 0 generate
470
    ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
471
      port map(rstn, clkm, apbi, apbo(4), moui, mouo);
472
    ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
473
      port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
474
  end generate;
475
  nokbd : if CFG_KBD_ENABLE = 0 generate
476
        apbo(4) <= apb_none; mouo <= ps2o_none;
477
        apbo(5) <= apb_none; kbdo <= ps2o_none;
478
  end generate;
479
  kbdclk_pad : iopad generic map (tech => padtech)
480
      port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
481
  kbdata_pad : iopad generic map (tech => padtech)
482
        port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
483
  mouclk_pad : iopad generic map (tech => padtech)
484
      port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
485
  mouata_pad : iopad generic map (tech => padtech)
486
        port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
487
 
488
  vga : if CFG_VGA_ENABLE /= 0 generate
489
    vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
490
       port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
491
    video_clock_pad : outpad generic map ( tech => padtech)
492
        port map (vid_clock, video_clk);
493
    video_clk <= not ethclk;
494
   end generate;
495
 
496
  -- Note: SVGA graphics support removed to make room for SpaceWire Light
497
  assert CFG_SVGA_ENABLE = 0 report "SVGA graphics not supported";
498
  svga : if CFG_SVGA_ENABLE /= 0 generate
499
    ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) <= ahbm_none;
500
    apbo(6) <= apb_none;
501
    vgao <= vgao_none;
502
    video_clk <= not clkm;
503
    video_clock_pad : outpad generic map ( tech => padtech)
504
        port map (vid_clock, video_clk);
505
  end generate;
506
 
507
  novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
508
    apbo(6) <= apb_none; vgao <= vgao_none;
509
    video_clk <= not clkm;
510
    video_clock_pad : outpad generic map ( tech => padtech)
511
        port map (vid_clock, video_clk);
512
  end generate;
513
 
514
  blank_pad : outpad generic map (tech => padtech)
515
        port map (vid_blankn, vgao.blank);
516
  comp_sync_pad : outpad generic map (tech => padtech)
517
        port map (vid_syncn, vgao.comp_sync);
518
  vert_sync_pad : outpad generic map (tech => padtech)
519
        port map (vid_vsync, vgao.vsync);
520
  horiz_sync_pad : outpad generic map (tech => padtech)
521
        port map (vid_hsync, vgao.hsync);
522
  video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
523
        port map (vid_r, vgao.video_out_r);
524
  video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
525
        port map (vid_g, vgao.video_out_g);
526
  video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
527
        port map (vid_b, vgao.video_out_b);
528
 
529
  gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GPIO unit
530
    grgpio0: grgpio
531
    generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
532
    port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
533
    gpioi => gpioi, gpioo => gpioo);
534
    p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
535
      pio_pads : for i in 1 to 2 generate
536
        pio_pad : iopad generic map (tech => padtech)
537
            port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
538
      end generate;
539
    end generate;
540
    p1 : if (CFG_CAN = 0) generate
541
      pio_pads : for i in 4 to 5 generate
542
        pio_pad : iopad generic map (tech => padtech)
543
            port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
544
      end generate;
545
    end generate;
546
    pio_pad0 : iopad generic map (tech => padtech)
547
            port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
548
    pio_pad1 : iopad generic map (tech => padtech)
549
            port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
550
    pio_pads : for i in 6 to 17 generate
551
        pio_pad : iopad generic map (tech => padtech)
552
            port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
553
    end generate;
554
 
555
  end generate;
556
 
557
  ahbs : if CFG_AHBSTAT = 1 generate    -- AHB status register
558
    ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
559
        nftslv => CFG_AHBSTATN)
560
      port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
561
  end generate;
562
 
563
-----------------------------------------------------------------------
564
---  ETHERNET ---------------------------------------------------------
565
-----------------------------------------------------------------------
566
 
567
    eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
568
      e1 : grethm generic map(
569
        hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
570
        pindex => 13, paddr => 13, pirq => 13, memtech => memtech,
571
        mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
572
        nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
573
        macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
574
        ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
575
      port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
576
        ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
577
        apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
578
    end generate;
579
 
580
    ethpads : if (CFG_GRETH = 1) generate -- eth pads
581
      emdio_pad : iopad generic map (tech => padtech)
582
      port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
583
      etxc_pad : clkpad generic map (tech => padtech, arch => 2)
584
        port map (etx_clk, ethi.tx_clk);
585
      erxc_pad : clkpad generic map (tech => padtech, arch => 2)
586
        port map (erx_clk, ethi.rx_clk);
587
      erxd_pad : inpadv generic map (tech => padtech, width => 4)
588
        port map (erxd, ethi.rxd(3 downto 0));
589
      erxdv_pad : inpad generic map (tech => padtech)
590
        port map (erx_dv, ethi.rx_dv);
591
      erxer_pad : inpad generic map (tech => padtech)
592
        port map (erx_er, ethi.rx_er);
593
      erxco_pad : inpad generic map (tech => padtech)
594
        port map (erx_col, ethi.rx_col);
595
      erxcr_pad : inpad generic map (tech => padtech)
596
        port map (erx_crs, ethi.rx_crs);
597
      emdint_pad : inpad generic map (tech => padtech)
598
        port map (emdint, ethi.mdint);
599
 
600
      etxd_pad : outpadv generic map (tech => padtech, width => 4)
601
        port map (etxd, etho.txd(3 downto 0));
602
      etxen_pad : outpad generic map (tech => padtech)
603
        port map ( etx_en, etho.tx_en);
604
      etxer_pad : outpad generic map (tech => padtech)
605
        port map (etx_er, etho.tx_er);
606
      emdc_pad : outpad generic map (tech => padtech)
607
        port map (emdc, etho.mdc);
608
    end generate;
609
 
610
-----------------------------------------------------------------------
611
---  AHB RAM ----------------------------------------------------------
612
-----------------------------------------------------------------------
613
 
614
  ocram : if CFG_AHBRAMEN = 1 generate
615
    ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
616
        tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
617
    port map ( rstn, clkm, ahbsi, ahbso(7));
618
  end generate;
619
 
620
-----------------------------------------------------------------------
621
---  Multi-core CAN ---------------------------------------------------
622
-----------------------------------------------------------------------
623
 
624
   can0 : if CFG_CAN = 1 generate
625
     can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
626
        iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
627
        ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
628
      port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
629
      can_tx_pad1 : iopad generic map (tech => padtech)
630
            port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
631
      can_rx_pad1 : iopad generic map (tech => padtech)
632
            port map (pio(4), gnd(0), vcc(0), can_lrx(0));
633
      canpas : if CFG_CAN_NUM = 2 generate
634
        can_tx_pad2 : iopad generic map (tech => padtech)
635
            port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
636
        can_rx_pad2 : iopad generic map (tech => padtech)
637
            port map (pio(1), gnd(0), vcc(0), can_lrx(1));
638
      end generate;
639
   end generate;
640
 
641
   -- standby controlled by pio(3) and pio(0)
642
 
643
-----------------------------------------------------------------------
644
---  SpaceWire Light --------------------------------------------------
645
-----------------------------------------------------------------------
646
 
647
   spw0: spwamba
648
      generic map (
649
         tech        => memtech,
650
         hindex      => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
651
         pindex      => 10,
652
         paddr       => 10,
653
         pirq        => 10,
654
         sysfreq     => real(CPU_FREQ) * 1000.0,
655
         txclkfreq   => 200.0e6,
656
         rximpl      => impl_fast,
657
         rxchunk     => 4,
658
         tximpl      => impl_fast,
659
         timecodegen => true,
660
         rxfifosize  => 8,
661
         txfifosize  => 8,
662
         desctablesize => 10,
663
         maxburst    => 3 )
664
      port map (
665
         clk     => clkm,
666
         rxclk   => spw_clkl,
667
         txclk   => spw_clkl,
668
         rstn    => rstn,
669
         apbi    => apbi,
670
         apbo    => apbo(10),
671
         ahbi    => ahbmi,
672
         ahbo    => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
673
         tick_in => spw_tick_in,
674
         spw_di  => spw_di,
675
         spw_si  => spw_si,
676
         spw_do  => spw_do,
677
         spw_so  => spw_so );
678
 
679
   spw_rxd_pad: inpad_ds
680
      generic map (padtech, lvds, x25v)
681
      port map (spw_rxdp(0), spw_rxdn(0), spw_di);
682
   spw_rxs_pad: inpad_ds
683
      generic map (padtech, lvds, x25v)
684
      port map (spw_rxsp(0), spw_rxsn(0), spw_si);
685
   spw_txd_pad: outpad_ds
686
      generic map (padtech, lvds, x25v)
687
      port map (spw_txdp(0), spw_txdn(0), spw_do, '0');
688
   spw_txs_pad: outpad_ds
689
      generic map (padtech, lvds, x25v)
690
      port map (spw_txsp(0), spw_txsn(0), spw_so, '0');
691
 
692
   -- Use 2nd GPTIMER unit to generate external tick_in signal.
693
   spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';
694
 
695
   -- Generate 200 MHz clock for fast receiver/transmitter.
696
   spwclk0: DCM
697
      generic map (
698
         CLKFX_DIVIDE       => 1,
699
         CLKFX_MULTIPLY     => 4,
700
         CLK_FEEDBACK       => "NONE",
701
         CLKIN_DIVIDE_BY_2  => false,
702
         CLKIN_PERIOD       => 20.0,
703
         CLKOUT_PHASE_SHIFT => "NONE",
704
         DESKEW_ADJUST      => "SYSTEM_SYNCHRONOUS",
705
         DFS_FREQUENCY_MODE => "LOW",
706
         DUTY_CYCLE_CORRECTION => true,
707
         STARTUP_WAIT       => false )
708
      port map (
709
         CLKIN      => lclk,
710
         RST        => not rstraw,
711
         CLKFX      => spw_clkl );
712
 
713
-------------------------------------------------------------------------------
714
--- USB -----------------------------------------------------------------------
715
-------------------------------------------------------------------------------
716
  -- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
717
  -- time (board has only one USB transceiver), therefore they share AHB
718
  -- master/slave indexes
719
  -----------------------------------------------------------------------------
720
  -- Shared pads
721
  -----------------------------------------------------------------------------
722
  usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
723
    usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
724
      port map (usb_clkout, uclk);
725
 
726
    usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
727
      port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
728
 
729
    usb_txready_pad : inpad generic map (tech => padtech)
730
      port map (usb_txready,usbi.txready);
731
    usb_rxvalid_pad : inpad generic map (tech => padtech)
732
      port map (usb_rxvalid,usbi.rxvalid);
733
    usb_rxerror_pad : inpad generic map (tech => padtech)
734
      port map (usb_rxerror,usbi.rxerror);
735
    usb_rxactive_pad : inpad generic map (tech => padtech)
736
      port map (usb_rxactive,usbi.rxactive);
737
    usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
738
      port map (usb_linestate,usbi.linestate);
739
    usb_vbus_pad : inpad generic map (tech => padtech)
740
      port map (usb_vbus, usbi.vbusvalid);
741
 
742
    usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
743
      port map (usb_reset,usbo.reset);
744
    usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
745
      port map (usb_suspend,usbo.suspendm);
746
    usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
747
      port map (usb_termsel,usbo.termselect);
748
    usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
749
      port map (usb_xcvrsel,usbo.xcvrselect(0));
750
    usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
751
      port map (usb_txvalid,usbo.txvalid);
752
    usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
753
      port map (usb_opmode,usbo.opmode);
754
 
755
    usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
756
      port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
757
 
758
  end generate;
759
 
760
  -----------------------------------------------------------------------------
761
  -- USB 2.0 Device Controller
762
  -----------------------------------------------------------------------------
763
  usbdc0: if CFG_GRUSBDC = 1 generate
764
    usbdc0: grusbdc
765
      generic map(
766
        hsindex => 5, hirq => 9, haddr => 16#004#, hmask => 16#FFC#,
767
        hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
768
        CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
769
        aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
770
        nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
771
        i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
772
        i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
773
        i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
774
        i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
775
        i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
776
        i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
777
        i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
778
        i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
779
        o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
780
        o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
781
        o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
782
        o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
783
        o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
784
        o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
785
        o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
786
        o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
787
        memtech => memtech)
788
      port map(
789
        uclk  => uclk,
790
        usbi  => usbi,
791
        usbo  => usbo,
792
        hclk  => clkm,
793
        hrst  => rstn,
794
        ahbmi => ahbmi,
795
        ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
796
                       CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
797
        ahbsi => ahbsi,
798
        ahbso => ahbso(5)
799
        );
800
  end generate usbdc0;
801
 
802
  -----------------------------------------------------------------------------
803
  -- USB DCL
804
  -----------------------------------------------------------------------------
805
  usb_dcl0: if CFG_GRUSB_DCL = 1 generate
806
    usb_dcl0: grusb_dcl
807
      generic map (
808
        hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
809
        CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
810
        memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
811
      port map (
812
        uclk, usbi, usbo, clkm, rstn, ahbmi,
813
        ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
814
              CFG_SPW_NUM*CFG_SPW_EN));
815
  end generate usb_dcl0;
816
 
817
-----------------------------------------------------------------------
818
---  AHB ATA ----------------------------------------------------------
819
-----------------------------------------------------------------------
820
 
821
  ata0 : if CFG_ATA = 1 generate
822
    atac0 : atactrl
823
      generic map(
824
        tech => 0, fdepth => CFG_ATAFIFO,
825
        mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
826
        CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
827
        CFG_GRUSBDC,
828
        shindex => 3, haddr => 16#A00#, hmask => 16#fff#, pirq  => CFG_ATAIRQ,
829
        mwdma => CFG_ATADMA, TWIDTH   => 8,
830
        -- PIO mode 0 settings (@100MHz clock)
831
        PIO_mode0_T1   => 6,   -- 70ns
832
        PIO_mode0_T2   => 28,  -- 290ns
833
        PIO_mode0_T4   => 2,   -- 30ns
834
        PIO_mode0_Teoc => 23   -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
835
        )
836
      port map(
837
        rst => rstn, arst => vcc(0), clk => clkm, ahbmi => ahbmi,
838
        ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
839
                       CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+
840
                       CFG_GRUSB_DCL+CFG_GRUSBDC),
841
        ahbsi => ahbsi, ahbso => ahbso(3), atai => idei, atao => ideo);
842
 
843
    ata_rstn_pad : outpad generic map (tech => padtech)
844
      port map (ata_rstn, ideo.rstn);
845
    ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
846
      port map (ata_data, ideo.ddo, ideo.oen, idei.ddi);
847
    ata_da_pad : outpadv generic map (tech => padtech, width => 3)
848
      port map (ata_da, ideo.da);
849
    ata_cs0_pad : outpad generic map (tech => padtech)
850
      port map (ata_cs0, ideo.cs0);
851
    ata_cs1_pad : outpad generic map (tech => padtech)
852
      port map (ata_cs1, ideo.cs1);
853
    ata_dior_pad : outpad generic map (tech => padtech)
854
      port map (ata_dior, ideo.dior);
855
    ata_diow_pad : outpad generic map (tech => padtech)
856
      port map (ata_diow, ideo.diow);
857
    iordy_pad : inpad generic map (tech => padtech)
858
      port map (ata_iordy, idei.iordy);
859
    intrq_pad : inpad generic map (tech => padtech)
860
      port map (ata_intrq, idei.intrq);
861
    dmarq_pad : inpad generic map (tech => padtech)
862
      port map (ata_dmarq, idei.dmarq);
863
    dmack_pad : outpad generic map (tech => padtech)
864
      port map (ata_dmack, ideo.dmack);
865
    ata_csel <= '0';
866
  end generate;
867
 
868
-----------------------------------------------------------------------
869
---  Drive unused bus elements  ---------------------------------------
870
-----------------------------------------------------------------------
871
 
872
--  nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
873
--    ahbmo(i) <= ahbm_none;
874
--  end generate;
875
--  nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
876
--  nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
877
 
878
-----------------------------------------------------------------------
879
---  Boot message  ----------------------------------------------------
880
-----------------------------------------------------------------------
881
 
882
-- pragma translate_off
883
  x : report_version
884
  generic map (
885
   msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
886
      msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
887
        & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
888
   msg3 => "Target technology: " & tech_table(fabtech) & ",  memory library: " & tech_table(memtech),
889
   mdel => 1
890
  );
891
-- pragma translate_on
892
end;

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