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[/] [spacewire_light/] [trunk/] [syn/] [streamtest_digilent-xc3s200/] [Makefile] - Blame information for rev 2

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1 2 jorisvr
 
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###############################################################################
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##                                                                           ##
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##                        project-dependent variables                        ##
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##                                                                           ##
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###############################################################################
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# The project name. The bit-file that is generated in the end will be named
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# "$(PROJ).bit"
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PROJ = streamtest
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# The top-level entity to be instantiated
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TOPLEVEL = streamtest_top
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# The VHDL sources that need to be compiled during synthesis
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RTLDIR = ../../rtl/vhdl
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VHDL_SOURCES = streamtest_top.vhd \
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               $(RTLDIR)/streamtest.vhd \
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               $(RTLDIR)/spwpkg.vhd \
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               $(RTLDIR)/spwstream.vhd \
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               $(RTLDIR)/spwlink.vhd \
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               $(RTLDIR)/spwram.vhd \
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               $(RTLDIR)/spwrecv.vhd \
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               $(RTLDIR)/spwxmit.vhd \
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               $(RTLDIR)/spwxmit_fast.vhd \
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               $(RTLDIR)/spwrecvfront_generic.vhd \
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               $(RTLDIR)/spwrecvfront_fast.vhd
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# Device type: Spartan-3 200 on Digilent board
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FPGA_TYPE       = xc3s200-ft256-4
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# The default target; recommended targets: "bitfile" or "upload"
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default : bitfile
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UCFFILE = streamtest.ucf
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###############################################################################
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##                                                                           ##
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##            miscellaneous project-independent variables & rules            ##
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##                                                                           ##
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###############################################################################
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# use this to make most tools quieter
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OPT_INTSTYLE = -intstyle ise
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# Phony (non file creating) targets
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.PHONY : default clean bitfile
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clean :
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        $(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb
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        $(RM) $(PROJ).xst-script
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        $(RM) $(PROJ).lso $(PROJ).prj
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        $(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
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        $(RM) $(PROJ).ngd $(PROJ).bld
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        $(RM) $(PROJ).twx $(PROJ).twr
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        $(RM) $(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm
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        $(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
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        $(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
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        $(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
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bitfile : $(PROJ).bit
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###############################################################################
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#                                                                             #
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#                    STAGE 1: "xst" (Xilinx Synthesis Tool)                   #
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#  needs:                                                                     #
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#                                                                             #
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#    $(PROJ).vhdl                                                             #
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#    $(PROJ).prj - Project file (created below)                               #
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#    $(PROJ).lso - Library Search Order file (created below)                  #
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#                                                                             #
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#  created files:                                                             #
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#                                                                             #
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#    $(PROJ).ngc     - netlist                                                #
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#    $(PROJ).ngr     - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e       #
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#                      (optional, depending on the '-rtlview' option)         #
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#    $(PROJ).xst.log - human-readable synthesis report                        #
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#                      (AKA .syr, .srp)                                       #
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#                                                                             #
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#  created directories:                                                       #
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#                                                                             #
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#    work                                                                     #
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#    dump.xst                                                                 #
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#                                                                             #
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###############################################################################
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# Generate a "Library Search Order" file, containing just "work" for now.
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$(PROJ).lso :
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        @echo "work" > $@
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# Generate a "Project" file, consisting of lines containing each of the
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# VHDL_SOURCES, preceded by "vhdl work".
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$(PROJ).prj :
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        $(shell echo -n $(VHDL_SOURCES) | \
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        sed 's/\([^ ]\+\) */vhdl work \1\n/g' > $@)
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$(PROJ).xst-script :
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        @echo "set -tmpdir /tmp"                                        > $@
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        @echo "set -xsthdpdir ."                                       >> $@
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        @echo "run"                                                    >> $@
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        @echo "-ifn                                  $(PROJ).prj"      >> $@
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        @echo "-ifmt                                 mixed"            >> $@
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        @echo "-ofn                                  $(PROJ)"          >> $@
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        @echo "-ofmt                                 ngc"              >> $@
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        @echo "-p                                    $(FPGA_TYPE)"     >> $@
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        @echo "-top                                  $(TOPLEVEL)"      >> $@
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        @echo "-opt_mode                             speed"            >> $@
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        @echo "-opt_level                            1"                >> $@
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        @echo "-iuc                                  no"               >> $@
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        @echo "-lso                                  $(PROJ).lso"      >> $@
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        @echo "-keep_hierarchy                       no"               >> $@
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        @echo "-glob_opt                             AllClockNets"     >> $@
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        @echo "-rtlview                              no"               >> $@
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        @echo "-read_cores                           yes"              >> $@
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# Note: write_timing_constraints is non-standard
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        @echo "-write_timing_constraints             yes"              >> $@
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        @echo "-cross_clock_analysis                 no"               >> $@
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#       @echo "-hierarchy_separator                  _"                >> $@
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        @echo "-bus_delimiter                        <>"               >> $@
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        @echo "-case                                 maintain"         >> $@
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        @echo "-slice_utilization_ratio              100"              >> $@
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#       @echo "-verilog2001                          yes"              >> $@
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#       @echo "-vlgincdir"                                             >> $@
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        @echo "-fsm_extract                          yes"              >> $@
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        @echo "-fsm_encoding                         auto"             >> $@
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        @echo "-fsm_style                            lut"              >> $@
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# Note: safe_implementation is non-standard
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        @echo "-safe_implementation                  yes"              >> $@
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        @echo "-ram_extract                          yes"              >> $@
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        @echo "-ram_style                            auto"             >> $@
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        @echo "-rom_extract                          yes"              >> $@
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        @echo "-rom_style                            auto"             >> $@
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        @echo "-mux_extract                          yes"              >> $@
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        @echo "-mux_style                            auto"             >> $@
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        @echo "-decoder_extract                      yes"              >> $@
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        @echo "-priority_extract                     yes"              >> $@
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        @echo "-shreg_extract                        yes"              >> $@
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        @echo "-shift_extract                        yes"              >> $@
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        @echo "-xor_collapse                         yes"              >> $@
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        @echo "-resource_sharing                     yes"              >> $@
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        @echo "-mult_style                           auto"             >> $@
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        @echo "-iobuf                                yes"              >> $@
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        @echo "-max_fanout                           500"              >> $@
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        @echo "-bufg                                 8"                >> $@
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        @echo "-register_duplication                 yes"              >> $@
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        @echo "-equivalent_register_removal          yes"              >> $@
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        @echo "-register_balancing                   no"               >> $@
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        @echo "-slice_packing                        yes"              >> $@
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        @echo "-optimize_primitives                  no"               >> $@
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        @echo "-iob                                  auto"             >> $@
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$(PROJ).ngc $(PROJ).xst.log : $(VHDL_SOURCES) $(PROJ).prj $(PROJ).lso $(PROJ).xst-script
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        rm -rf work dump.xst
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        xst $(OPT_INTSTYLE) -ifn $(PROJ).xst-script -ofn $(PROJ).xst.log
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        rm -rf work dump.xst
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###############################################################################
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#                                                                             #
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#                               STAGE 2: ngdbuild                             #
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#  needs:                                                                     #
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#                                                                             #
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#    $(PROJ).ngc                                                              #
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#                                                                             #
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#  created files:                                                             #
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#                                                                             #
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#    $(PROJ).bld - human-readable build log                                   #
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#    $(PROJ).ngd - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e           #
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#                                                                             #
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#  created dir:                                                               #
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#    _ngo                                                                     #
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#                                                                             #
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###############################################################################
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$(PROJ).ngd $(PROJ).bld: $(PROJ).ngc $(UCFFILE)
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        rm -rf _ngo
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        ngdbuild $(OPT_INTSTYLE) -dd _ngo -aul -p $(FPGA_TYPE) $(if $(UCFFILE),-uc $(UCFFILE)) $(PROJ).ngc $(PROJ).ngd
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        rm -rf _ngo
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###############################################################################
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#                                                                             #
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#                                STAGE 3: Mapper                              #
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#  needs:                                                                     #
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#                                                                             #
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#    $(PROJ).ngd                                                              #
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#                                                                             #
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#  created files:                                                             #
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#                                                                             #
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#    $(PROJ).pcf     - ASCII file                                             #
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#    $(PROJ)_map.mrp - human-readable mapping report                          #
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#    $(PROJ)_map.ncd - binary format                                          #
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#    $(PROJ)_map.ngm - XILINX-XDB 0.1 STUB 0.1 ASCII / XILINX-XDM V1.2e       #
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#                                                                             #
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#  NOTE:                                                                      #
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#                                                                             #
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#    In order to prevent the make process from terminating on these spurious  #
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#    problems, we precede the "map" invocation with a hyphen, instructing     #
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#    make to ignore the return code from "map".                               #
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#                                                                             #
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###############################################################################
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$(PROJ).pcf $(PROJ)_map.mrp $(PROJ)_map.ncd $(PROJ)_map.ngm: $(PROJ).ngd
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        map $(OPT_INTSTYLE) -p $(FPGA_TYPE) -cm area -pr b -c 100 -o $(PROJ)_map.ncd $(PROJ).ngd $(PROJ).pcf
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###############################################################################
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#                                                                             #
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#                          STAGE 4: Place-and-Route                           #
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#  needs:                                                                     #
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#                                                                             #
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#    $(PROJ).pcf                                                              #
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#    $(PROJ)_map.ncd                                                          #
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#                                                                             #
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#  created files:                                                             #
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#                                                                             #
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#    $(PROJ).ncd     - binary file                                            #
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#    $(PROJ).pad     - ASCII file for import in spreadsheet                   #
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#    $(PROJ).par     - human-readable place-and-route report                  #
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#    $(PROJ).xpi     - ASCII file                                             #
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#    $(PROJ)_pad.csv - human-readable CVS file                                #
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#    $(PROJ)_pad.txt - human-readable file                                    #
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#                                                                             #
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###############################################################################
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$(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt: $(PROJ).pcf $(PROJ)_map.ncd
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        par -w $(OPT_INTSTYLE) -t 1 $(PROJ)_map.ncd $(PROJ).ncd $(PROJ).pcf
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###############################################################################
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#                                                                             #
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#                         STAGE 4.5 (optional): trace                         #
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#  needs:                                                                     #
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#                                                                             #
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#  created files:                                                             #
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#                                                                             #
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###############################################################################
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$(PROJ).twr $(PROJ).twx : $(PROJ).ncd $(PROJ).pcf
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        trce $(OPT_INTSTYLE) -e 5 -l 5 -u 5 -xml $(PROJ) $(PROJ).ncd -o $(PROJ).twr $(PROJ).pcf
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###############################################################################
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#                                                                             #
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#                          STAGE 5: Generate BIT-file                         #
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#  needs:                                                                     #
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#                                                                             #
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#    $(PROJ).ncd                                                              #
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#                                                                             #
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#  created files: $(PROJ).bgn $(PROJ).bit $(PROJ).drc                         #
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#                                                                             #
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#    $(PROJ).bgn - human-readable BitGen report                               #
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#    $(PROJ).drc - human readable DRC report                                  #
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#    $(PROJ).bit - binary image file                                          #
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#                                                                             #
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###############################################################################
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# We omit "-g StartUpClk:JtagClk" ; this doesn't work if the image is loaded
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# from a PROM.
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# Note: LCK_cycle:3 is non-standard
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OPT_BITGEN = -w                     \
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             -g DebugBitstream:No   \
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             -g Binary:no           \
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             -g CRC:Enable          \
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             -g ConfigRate:6        \
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             -g CclkPin:PullUp      \
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             -g M0Pin:PullUp        \
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             -g M1Pin:PullUp        \
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             -g M2Pin:PullUp        \
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             -g ProgPin:PullUp      \
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             -g DonePin:PullUp      \
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             -g TckPin:PullUp       \
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             -g TdiPin:PullUp       \
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             -g TdoPin:PullUp       \
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             -g TmsPin:PullUp       \
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             -g UnusedPin:PullDown  \
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             -g UserID:0xFFFFFFFF   \
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             -g DCMShutDown:Disable \
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             -g DONE_cycle:4        \
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             -g GTS_cycle:5         \
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             -g GWE_cycle:6         \
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             -g LCK_cycle:3         \
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             -g Match_cycle:Auto    \
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             -g Security:None       \
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             -g DonePipe:No         \
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             -g DriveDone:No
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$(PROJ).bit $(PROJ).bgn $(PROJ).drc: $(PROJ).ncd
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        bitgen $(OPT_INTSTYLE) $(OPT_BITGEN) $(PROJ).ncd
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###############################################################################
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