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redbear |
--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=64 NUMWORDS_B=64 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=9 WIDTH_B=9 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_A="NONE" address_a address_b addressstall_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:06:01:09:22:16:SJ cbx_altsyncram 2017:06:01:09:22:16:SJ cbx_cycloneii 2017:06:01:09:22:16:SJ cbx_lpm_add_sub 2017:06:01:09:22:16:SJ cbx_lpm_compare 2017:06:01:09:22:16:SJ cbx_lpm_decode 2017:06:01:09:22:16:SJ cbx_lpm_mux 2017:06:01:09:22:16:SJ cbx_mgl 2017:06:01:10:52:00:SJ cbx_nadder 2017:06:01:09:22:16:SJ cbx_stratix 2017:06:01:09:22:16:SJ cbx_stratixii 2017:06:01:09:22:16:SJ cbx_stratixiii 2017:06:01:09:22:16:SJ cbx_stratixv 2017:06:01:09:22:16:SJ cbx_util_mgl 2017:06:01:09:22:16:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Intel and sold by Intel or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
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WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
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RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = M10K 1
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_pfo1
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(
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address_a[5..0] : input;
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address_b[5..0] : input;
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addressstall_b : input;
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clock0 : input;
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data_a[8..0] : input;
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q_b[8..0] : output;
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wren_a : input;
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)
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VARIABLE
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ram_block1a0 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 6,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 63,
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PORT_A_LOGICAL_RAM_DEPTH = 64,
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PORT_A_LOGICAL_RAM_WIDTH = 9,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 6,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 63,
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PORT_B_LOGICAL_RAM_DEPTH = 64,
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PORT_B_LOGICAL_RAM_WIDTH = 9,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 6,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 63,
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PORT_A_LOGICAL_RAM_DEPTH = 64,
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PORT_A_LOGICAL_RAM_WIDTH = 9,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 6,
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PORT_B_DATA_OUT_CLEAR = "none",
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| 86 |
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 1,
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PORT_B_LAST_ADDRESS = 63,
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PORT_B_LOGICAL_RAM_DEPTH = 64,
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PORT_B_LOGICAL_RAM_WIDTH = 9,
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| 92 |
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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| 93 |
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RAM_BLOCK_TYPE = "AUTO"
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| 94 |
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);
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| 95 |
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ram_block1a2 : cyclonev_ram_block
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| 96 |
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WITH (
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| 97 |
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CLK0_CORE_CLOCK_ENABLE = "none",
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| 98 |
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CLK0_INPUT_CLOCK_ENABLE = "none",
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| 99 |
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 6,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 2,
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PORT_A_LAST_ADDRESS = 63,
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PORT_A_LOGICAL_RAM_DEPTH = 64,
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PORT_A_LOGICAL_RAM_WIDTH = 9,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 6,
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PORT_B_DATA_OUT_CLEAR = "none",
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| 114 |
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PORT_B_DATA_WIDTH = 1,
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| 115 |
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 2,
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PORT_B_LAST_ADDRESS = 63,
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PORT_B_LOGICAL_RAM_DEPTH = 64,
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PORT_B_LOGICAL_RAM_WIDTH = 9,
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| 120 |
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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| 121 |
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RAM_BLOCK_TYPE = "AUTO"
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| 122 |
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);
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| 123 |
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ram_block1a3 : cyclonev_ram_block
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| 124 |
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WITH (
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| 125 |
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CLK0_CORE_CLOCK_ENABLE = "none",
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| 126 |
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CLK0_INPUT_CLOCK_ENABLE = "none",
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| 127 |
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CONNECTIVITY_CHECKING = "OFF",
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| 128 |
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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| 129 |
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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| 130 |
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OPERATION_MODE = "dual_port",
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| 131 |
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PORT_A_ADDRESS_WIDTH = 6,
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| 132 |
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PORT_A_DATA_WIDTH = 1,
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| 133 |
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PORT_A_FIRST_ADDRESS = 0,
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| 134 |
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PORT_A_FIRST_BIT_NUMBER = 3,
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| 135 |
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PORT_A_LAST_ADDRESS = 63,
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| 136 |
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PORT_A_LOGICAL_RAM_DEPTH = 64,
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| 137 |
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PORT_A_LOGICAL_RAM_WIDTH = 9,
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| 138 |
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PORT_B_ADDRESS_CLEAR = "none",
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| 139 |
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PORT_B_ADDRESS_CLOCK = "clock0",
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| 140 |
|
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PORT_B_ADDRESS_WIDTH = 6,
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| 141 |
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PORT_B_DATA_OUT_CLEAR = "none",
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| 142 |
|
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PORT_B_DATA_WIDTH = 1,
|
| 143 |
|
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PORT_B_FIRST_ADDRESS = 0,
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| 144 |
|
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PORT_B_FIRST_BIT_NUMBER = 3,
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| 145 |
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PORT_B_LAST_ADDRESS = 63,
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| 146 |
|
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PORT_B_LOGICAL_RAM_DEPTH = 64,
|
| 147 |
|
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PORT_B_LOGICAL_RAM_WIDTH = 9,
|
| 148 |
|
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PORT_B_READ_ENABLE_CLOCK = "clock0",
|
| 149 |
|
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RAM_BLOCK_TYPE = "AUTO"
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| 150 |
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);
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| 151 |
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ram_block1a4 : cyclonev_ram_block
|
| 152 |
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WITH (
|
| 153 |
|
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CLK0_CORE_CLOCK_ENABLE = "none",
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| 154 |
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CLK0_INPUT_CLOCK_ENABLE = "none",
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| 155 |
|
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CONNECTIVITY_CHECKING = "OFF",
|
| 156 |
|
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 157 |
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 158 |
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OPERATION_MODE = "dual_port",
|
| 159 |
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PORT_A_ADDRESS_WIDTH = 6,
|
| 160 |
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PORT_A_DATA_WIDTH = 1,
|
| 161 |
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PORT_A_FIRST_ADDRESS = 0,
|
| 162 |
|
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PORT_A_FIRST_BIT_NUMBER = 4,
|
| 163 |
|
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PORT_A_LAST_ADDRESS = 63,
|
| 164 |
|
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PORT_A_LOGICAL_RAM_DEPTH = 64,
|
| 165 |
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PORT_A_LOGICAL_RAM_WIDTH = 9,
|
| 166 |
|
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PORT_B_ADDRESS_CLEAR = "none",
|
| 167 |
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PORT_B_ADDRESS_CLOCK = "clock0",
|
| 168 |
|
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PORT_B_ADDRESS_WIDTH = 6,
|
| 169 |
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
| 170 |
|
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PORT_B_DATA_WIDTH = 1,
|
| 171 |
|
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PORT_B_FIRST_ADDRESS = 0,
|
| 172 |
|
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PORT_B_FIRST_BIT_NUMBER = 4,
|
| 173 |
|
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PORT_B_LAST_ADDRESS = 63,
|
| 174 |
|
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PORT_B_LOGICAL_RAM_DEPTH = 64,
|
| 175 |
|
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PORT_B_LOGICAL_RAM_WIDTH = 9,
|
| 176 |
|
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PORT_B_READ_ENABLE_CLOCK = "clock0",
|
| 177 |
|
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RAM_BLOCK_TYPE = "AUTO"
|
| 178 |
|
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);
|
| 179 |
|
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ram_block1a5 : cyclonev_ram_block
|
| 180 |
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WITH (
|
| 181 |
|
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CLK0_CORE_CLOCK_ENABLE = "none",
|
| 182 |
|
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CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 183 |
|
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CONNECTIVITY_CHECKING = "OFF",
|
| 184 |
|
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 185 |
|
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 186 |
|
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OPERATION_MODE = "dual_port",
|
| 187 |
|
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PORT_A_ADDRESS_WIDTH = 6,
|
| 188 |
|
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PORT_A_DATA_WIDTH = 1,
|
| 189 |
|
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PORT_A_FIRST_ADDRESS = 0,
|
| 190 |
|
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PORT_A_FIRST_BIT_NUMBER = 5,
|
| 191 |
|
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PORT_A_LAST_ADDRESS = 63,
|
| 192 |
|
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PORT_A_LOGICAL_RAM_DEPTH = 64,
|
| 193 |
|
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PORT_A_LOGICAL_RAM_WIDTH = 9,
|
| 194 |
|
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PORT_B_ADDRESS_CLEAR = "none",
|
| 195 |
|
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PORT_B_ADDRESS_CLOCK = "clock0",
|
| 196 |
|
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PORT_B_ADDRESS_WIDTH = 6,
|
| 197 |
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
| 198 |
|
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PORT_B_DATA_WIDTH = 1,
|
| 199 |
|
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PORT_B_FIRST_ADDRESS = 0,
|
| 200 |
|
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PORT_B_FIRST_BIT_NUMBER = 5,
|
| 201 |
|
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PORT_B_LAST_ADDRESS = 63,
|
| 202 |
|
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PORT_B_LOGICAL_RAM_DEPTH = 64,
|
| 203 |
|
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PORT_B_LOGICAL_RAM_WIDTH = 9,
|
| 204 |
|
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PORT_B_READ_ENABLE_CLOCK = "clock0",
|
| 205 |
|
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RAM_BLOCK_TYPE = "AUTO"
|
| 206 |
|
|
);
|
| 207 |
|
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ram_block1a6 : cyclonev_ram_block
|
| 208 |
|
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WITH (
|
| 209 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 210 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 211 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 212 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 213 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 214 |
|
|
OPERATION_MODE = "dual_port",
|
| 215 |
|
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PORT_A_ADDRESS_WIDTH = 6,
|
| 216 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 217 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 218 |
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
| 219 |
|
|
PORT_A_LAST_ADDRESS = 63,
|
| 220 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 64,
|
| 221 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 9,
|
| 222 |
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
| 223 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 224 |
|
|
PORT_B_ADDRESS_WIDTH = 6,
|
| 225 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 226 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 227 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 228 |
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
| 229 |
|
|
PORT_B_LAST_ADDRESS = 63,
|
| 230 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 64,
|
| 231 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 9,
|
| 232 |
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
| 233 |
|
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RAM_BLOCK_TYPE = "AUTO"
|
| 234 |
|
|
);
|
| 235 |
|
|
ram_block1a7 : cyclonev_ram_block
|
| 236 |
|
|
WITH (
|
| 237 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 238 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 239 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 240 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 241 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 242 |
|
|
OPERATION_MODE = "dual_port",
|
| 243 |
|
|
PORT_A_ADDRESS_WIDTH = 6,
|
| 244 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 245 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 246 |
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
| 247 |
|
|
PORT_A_LAST_ADDRESS = 63,
|
| 248 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 64,
|
| 249 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 9,
|
| 250 |
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
| 251 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 252 |
|
|
PORT_B_ADDRESS_WIDTH = 6,
|
| 253 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 254 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 255 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 256 |
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
| 257 |
|
|
PORT_B_LAST_ADDRESS = 63,
|
| 258 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 64,
|
| 259 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 9,
|
| 260 |
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
| 261 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 262 |
|
|
);
|
| 263 |
|
|
ram_block1a8 : cyclonev_ram_block
|
| 264 |
|
|
WITH (
|
| 265 |
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
| 266 |
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
| 267 |
|
|
CONNECTIVITY_CHECKING = "OFF",
|
| 268 |
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
| 269 |
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
| 270 |
|
|
OPERATION_MODE = "dual_port",
|
| 271 |
|
|
PORT_A_ADDRESS_WIDTH = 6,
|
| 272 |
|
|
PORT_A_DATA_WIDTH = 1,
|
| 273 |
|
|
PORT_A_FIRST_ADDRESS = 0,
|
| 274 |
|
|
PORT_A_FIRST_BIT_NUMBER = 8,
|
| 275 |
|
|
PORT_A_LAST_ADDRESS = 63,
|
| 276 |
|
|
PORT_A_LOGICAL_RAM_DEPTH = 64,
|
| 277 |
|
|
PORT_A_LOGICAL_RAM_WIDTH = 9,
|
| 278 |
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
| 279 |
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
| 280 |
|
|
PORT_B_ADDRESS_WIDTH = 6,
|
| 281 |
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
| 282 |
|
|
PORT_B_DATA_WIDTH = 1,
|
| 283 |
|
|
PORT_B_FIRST_ADDRESS = 0,
|
| 284 |
|
|
PORT_B_FIRST_BIT_NUMBER = 8,
|
| 285 |
|
|
PORT_B_LAST_ADDRESS = 63,
|
| 286 |
|
|
PORT_B_LOGICAL_RAM_DEPTH = 64,
|
| 287 |
|
|
PORT_B_LOGICAL_RAM_WIDTH = 9,
|
| 288 |
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
| 289 |
|
|
RAM_BLOCK_TYPE = "AUTO"
|
| 290 |
|
|
);
|
| 291 |
|
|
address_a_wire[5..0] : WIRE;
|
| 292 |
|
|
address_b_wire[5..0] : WIRE;
|
| 293 |
|
|
|
| 294 |
|
|
BEGIN
|
| 295 |
|
|
ram_block1a[8..0].clk0 = clock0;
|
| 296 |
|
|
ram_block1a[8..0].portaaddr[] = ( address_a_wire[5..0]);
|
| 297 |
|
|
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
| 298 |
|
|
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
| 299 |
|
|
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
| 300 |
|
|
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
| 301 |
|
|
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
| 302 |
|
|
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
| 303 |
|
|
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
| 304 |
|
|
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
| 305 |
|
|
ram_block1a[8].portadatain[] = ( data_a[8..8]);
|
| 306 |
|
|
ram_block1a[8..0].portawe = wren_a;
|
| 307 |
|
|
ram_block1a[8..0].portbaddr[] = ( address_b_wire[5..0]);
|
| 308 |
|
|
ram_block1a[8..0].portbaddrstall = addressstall_b;
|
| 309 |
|
|
ram_block1a[8..0].portbre = B"111111111";
|
| 310 |
|
|
address_a_wire[] = address_a[];
|
| 311 |
|
|
address_b_wire[] = address_b[];
|
| 312 |
|
|
q_b[] = ( ram_block1a[8..0].portbdataout[0..0]);
|
| 313 |
|
|
END;
|
| 314 |
|
|
--VALID FILE
|
