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URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [db/] [prev_cmp_spw_fifo_ulight.qmsg] - Blame information for rev 40

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Line No. Rev Author Line
1 40 redbear 
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1516735621447 ""}
2 
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Shell Quartus Prime " "Running Quartus Prime Shell" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 23 17:27:00 2018 " "Processing started: Tue Jan 23 17:27:00 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}
3 
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight " "Command: quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight" {  } {  } 0 0 "Command: %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}
4 
{ "Info" "IQEXE_START_BANNER_TCL_ARGS" "-variation_files ulight_fifo.qsys spw_fifo_ulight " "Quartus(args): -variation_files ulight_fifo.qsys spw_fifo_ulight" {  } {  } 0 0 "Quartus(args): %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""}
5 
{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo.qsys ulight_fifo.BAK.qsys " "Backing up file \"ulight_fifo.qsys\" to \"ulight_fifo.BAK.qsys\"" {  } {  } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653410 ""}
6 
{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo/synthesis/ulight_fifo.v ulight_fifo.BAK.v " "Backing up file \"ulight_fifo/synthesis/ulight_fifo.v\" to \"ulight_fifo.BAK.v\"" {  } {  } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653455 ""}
7 
{ "Info" "IIPMAN_IPRGEN_START" "Qsys ulight_fifo.qsys " "Started upgrading IP component Qsys with file \"ulight_fifo.qsys\"" {  } {  } 0 11837 "Started upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653457 ""}
8 
{ "Info" "" "" "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" {  } {  } 0 0 "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" 0 0 "Shell" 0 -1 1516735704060 ""}
9 
{ "Info" "" "" "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" {  } {  } 0 0 "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" 0 0 "Shell" 0 -1 1516735704118 ""}
10 
{ "Info" "ulight_fifo_generation.rpt" "" "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" 0 0 "Shell" 0 -1 1516735739162 ""}
11 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Starting: Create simulation model" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Starting: Create simulation model" 0 0 "Shell" 0 -1 1516735739163 ""}
12 
{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735739395 ""}
13 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Reading input file" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Reading input file" 0 0 "Shell" 0 -1 1516735739472 ""}
14 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739501 ""}
15 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module auto_start" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735739502 ""}
16 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735739503 ""}
17 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clk_0" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735739503 ""}
18 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739504 ""}
19 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735739505 ""}
20 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739506 ""}
21 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735739510 ""}
22 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739513 ""}
23 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735739515 ""}
24 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739516 ""}
25 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735739520 ""}
26 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739522 ""}
27 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_info" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735739523 ""}
28 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739525 ""}
29 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735739527 ""}
30 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739528 ""}
31 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735739543 ""}
32 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739544 ""}
33 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735739544 ""}
34 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739546 ""}
35 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735739546 ""}
36 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739547 ""}
37 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735739548 ""}
38 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739548 ""}
39 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735739549 ""}
40 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735739550 ""}
41 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module hps_0" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735739564 ""}
42 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739586 ""}
43 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735739586 ""}
44 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739588 ""}
45 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_disable" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735739589 ""}
46 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739590 ""}
47 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_start" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735739598 ""}
48 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735739599 ""}
49 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module pll_0" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735739600 ""}
50 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739604 ""}
51 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735739605 ""}
52 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739606 ""}
53 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735739612 ""}
54 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739614 ""}
55 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735739615 ""}
56 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739616 ""}
57 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" 0 0 "Shell" 0 -1 1516735739625 ""}
58 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739627 ""}
59 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735739627 ""}
60 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739628 ""}
61 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735739629 ""}
62 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739630 ""}
63 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735739631 ""}
64 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Building connections" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Building connections" 0 0 "Shell" 0 -1 1516735739632 ""}
65 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing connections" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735739642 ""}
66 
{ "Info" "" "" "2018.01.23.17:28:59 Info: Validating" {  } {  } 0 0 "2018.01.23.17:28:59 Info: Validating" 0 0 "Shell" 0 -1 1516735739645 ""}
67 
{ "Info" "" "" "2018.01.23.17:29:08 Info: Done reading input file" {  } {  } 0 0 "2018.01.23.17:29:08 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735748747 ""}
68 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""}
69 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""}
70 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36" {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36" 0 0 "Shell" 0 -1 1516735752190 ""}
71 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" 0 0 "Shell" 0 -1 1516735752190 ""}
72 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735752196 ""}
73 
{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" {  } {  } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735752197 ""}
74 
{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" {  } {  } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735752198 ""}
75 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735752198 ""}
76 
{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" {  } {  } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735752198 ""}
77 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""}
78 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""}
79 
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752200 ""}
80 
{ "Info" "" "" "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" {  } {  } 0 0 "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" 0 0 "Shell" 0 -1 1516735756855 ""}
81 
{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" {  } {  } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735775279 ""}
82 
{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" {  } {  } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735775279 ""}
83 
{ "Info" "" "" "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" {  } {  } 0 0 "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735779023 ""}
84 
{ "Info" "  ]" "" "2018.01.23.17:29:39 Info: auto_start:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" {  } {  } 0 0 "2018.01.23.17:29:39 Info: auto_start:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" 0 0 "Shell" 0 -1 1516735779023 ""}
85 
{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" {  } {  } 0 0 "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735780647 ""}
86 
{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" {  } {  } 0 0 "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735780650 ""}
87 
{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" {  } {  } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780733 ""}
88 
{ "Info" "  ]" "" "2018.01.23.17:29:40 Info: clock_sel:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" {  } {  } 0 0 "2018.01.23.17:29:40 Info: clock_sel:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" 0 0 "Shell" 0 -1 1516735780733 ""}
89 
{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" {  } {  } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780886 ""}
90 
{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" {  } {  } 0 0 "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735780888 ""}
91 
{ "Info" "" "" "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" {  } {  } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735780972 ""}
92 
{ "Info" "  ]" "" "2018.01.23.17:29:40 Info: counter_rx_fifo:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" {  } {  } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" 0 0 "Shell" 0 -1 1516735780972 ""}
93 
{ "Info" "" "" "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" {  } {  } 0 0 "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735781099 ""}
94 
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" {  } {  } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735781242 ""}
95 
{ "Info" "  ]" "" "2018.01.23.17:29:41 Info: data_flag_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" {  } {  } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" 0 0 "Shell" 0 -1 1516735781242 ""}
96 
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" {  } {  } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735781379 ""}
97 
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" {  } {  } 0 0 "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781502 ""}
98 
{ "Info" "  ]" "" "2018.01.23.17:29:41 Info: data_info:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" {  } {  } 0 0 "2018.01.23.17:29:41 Info: data_info:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" 0 0 "Shell" 0 -1 1516735781502 ""}
99 
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" {  } {  } 0 0 "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781634 ""}
100 
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" {  } {  } 0 0 "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735781635 ""}
101 
{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" {  } {  } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781751 ""}
102 
{ "Info" "  ]" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" {  } {  } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" 0 0 "Shell" 0 -1 1516735781752 ""}
103 
{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" {  } {  } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781904 ""}
104 
{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" {  } {  } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735781906 ""}
105 
{ "Info" "" "" "2018.01.23.17:29:41 Info: hps_0: \"Running  for module: hps_0\"" {  } {  } 0 0 "2018.01.23.17:29:41 Info: hps_0: \"Running  for module: hps_0\"" 0 0 "Shell" 0 -1 1516735781908 ""}
106 
{ "Info" "" "" "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0  m = 36" {  } {  } 0 0 "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0  m = 36" 0 0 "Shell" 0 -1 1516735782735 ""}
107 
{ "Info" "" "" "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" {  } {  } 0 0 "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" 0 0 "Shell" 0 -1 1516735783333 ""}
108 
{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." {  } {  } 0 0 "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735783343 ""}
109 
{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" {  } {  } 0 0 "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735783636 ""}
110 
{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" {  } {  } 0 0 "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735783757 ""}
111 
{ "Info" "" "" "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" {  } {  } 0 0 "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735784424 ""}
112 
{ "Info" "  ]" "" "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" {  } {  } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" 0 0 "Shell" 0 -1 1516735784521 ""}
113 
{ "Info" "" "" "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" {  } {  } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735784720 ""}
114 
{ "Info" "" "" "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" {  } {  } 0 0 "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" 0 0 "Shell" 0 -1 1516735784779 ""}
115 
{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" {  } {  } 0 0 "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" 0 0 "Shell" 0 -1 1516735812813 ""}
116 
{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" {  } {  } 0 0 "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735812815 ""}
117 
{ "Info" "" "" "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" {  } {  } 0 0 "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735812969 ""}
118 
{ "Info" "  ]" "" "2018.01.23.17:30:12 Info: timecode_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" {  } {  } 0 0 "2018.01.23.17:30:12 Info: timecode_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" 0 0 "Shell" 0 -1 1516735812970 ""}
119 
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" {  } {  } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735813142 ""}
120 
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" {  } {  } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735813144 ""}
121 
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" {  } {  } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813212 ""}
122 
{ "Info" "  ]" "" "2018.01.23.17:30:13 Info: timecode_tx_data:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" {  } {  } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" 0 0 "Shell" 0 -1 1516735813212 ""}
123 
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" {  } {  } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813329 ""}
124 
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" {  } {  } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735813330 ""}
125 
{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" {  } {  } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813400 ""}
126 
{ "Info" "  ]" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" {  } {  } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl  --do_build_sim=1    --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" 0 0 "Shell" 0 -1 1516735813401 ""}
127 
{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" {  } {  } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813531 ""}
128 
{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" {  } {  } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735813533 ""}
129 
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815764 ""}
130 
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815843 ""}
131 
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815918 ""}
132 
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815973 ""}
133 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816040 ""}
134 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816108 ""}
135 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816205 ""}
136 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816278 ""}
137 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816352 ""}
138 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816421 ""}
139 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816501 ""}
140 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816574 ""}
141 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816654 ""}
142 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816731 ""}
143 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816801 ""}
144 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816868 ""}
145 
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816942 ""}
146 
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817025 ""}
147 
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817110 ""}
148 
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817182 ""}
149 
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817249 ""}
150 
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817317 ""}
151 
{ "Info" "" "" "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" {  } {  } 0 0 "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735820323 ""}
152 
{ "Info" "" "" "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" {  } {  } 0 0 "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735820407 ""}
153 
{ "Info" "" "" "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" {  } {  } 0 0 "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735820733 ""}
154 
{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" {  } {  } 0 0 "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735820852 ""}
155 
{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" {  } {  } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735820878 ""}
156 
{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" {  } {  } 0 0 "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735820907 ""}
157 
{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" {  } {  } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735820943 ""}
158 
{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735821010 ""}
159 
{ "Info" "" "" "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735821047 ""}
160 
{ "Info" "" "" "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735821058 ""}
161 
{ "Info" "" "" "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735821132 ""}
162 
{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821135 ""}
163 
{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735821258 ""}
164 
{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821262 ""}
165 
{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821263 ""}
166 
{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735821319 ""}
167 
{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735821334 ""}
168 
{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735821340 ""}
169 
{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735821360 ""}
170 
{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821362 ""}
171 
{ "Info" "" "" "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735821401 ""}
172 
{ "Info" "" "" "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735821470 ""}
173 
{ "Info" "verbosity_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""}
174 
{ "Info" "avalon_utilities_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""}
175 
{ "Info" "avalon_mm_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821472 ""}
176 
{ "Info" "altera_avalon_mm_slave_bfm.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821474 ""}
177 
{ "Info" "altera_avalon_interrupt_sink.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""}
178 
{ "Info" "altera_avalon_clock_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""}
179 
{ "Info" "altera_avalon_reset_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821476 ""}
180 
{ "Info" "" "" "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" {  } {  } 0 0 "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735821510 ""}
181 
{ "Info" "" "" "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" {  } {  } 0 0 "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" 0 0 "Shell" 0 -1 1516735821511 ""}
182 
{ "Info" "" "" "2018.01.23.17:30:21 Info: qsys-generate succeeded." {  } {  } 0 0 "2018.01.23.17:30:21 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735821581 ""}
183 
{ "Info" "" "" "2018.01.23.17:30:21 Info: Finished: Create simulation model" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Finished: Create simulation model" 0 0 "Shell" 0 -1 1516735821581 ""}
184 
{ "Info" "" "" "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." {  } {  } 0 0 "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735821582 ""}
185 
{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821583 ""}
186 
{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821590 ""}
187 
{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822982 ""}
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{ "Info" "msim_setup.tcl" "" "2018.01.23.17:30:22 Info:     mentor" {  } {  } 0 0 "2018.01.23.17:30:22 Info:     mentor" 0 0 "Shell" 0 -1 1516735822983 ""}
189 
{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822995 ""}
190 
{ "Info" "vcs_setup.sh" "" "2018.01.23.17:30:22 Info:     synopsys/vcs" {  } {  } 0 0 "2018.01.23.17:30:22 Info:     synopsys/vcs" 0 0 "Shell" 0 -1 1516735822996 ""}
191 
{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823007 ""}
192 
{ "Info" "synopsys_sim.setup" "" "2018.01.23.17:30:23 Info:     synopsys/vcsmx" {  } {  } 0 0 "2018.01.23.17:30:23 Info:     synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823054 ""}
193 
{ "Info" "vcsmx_setup.sh" "" "2018.01.23.17:30:23 Info:     synopsys/vcsmx" {  } {  } 0 0 "2018.01.23.17:30:23 Info:     synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823361 ""}
194 
{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823387 ""}
195 
{ "Info" "cds.lib" "" "2018.01.23.17:30:23 Info:     cadence" {  } {  } 0 0 "2018.01.23.17:30:23 Info:     cadence" 0 0 "Shell" 0 -1 1516735823388 ""}
196 
{ "Info" "hdl.var" "" "2018.01.23.17:30:23 Info:     cadence" {  } {  } 0 0 "2018.01.23.17:30:23 Info:     cadence" 0 0 "Shell" 0 -1 1516735823404 ""}
197 
{ "Info" "ncsim_setup.sh" "" "2018.01.23.17:30:23 Info:     cadence" {  } {  } 0 0 "2018.01.23.17:30:23 Info:     cadence" 0 0 "Shell" 0 -1 1516735823411 ""}
198 
{ "Info" " directory" "" "2018.01.23.17:30:23 Info:     32 .cds.lib files in cadence/cds_libs" {  } {  } 0 0 "2018.01.23.17:30:23 Info:     32 .cds.lib files in cadence/cds_libs" 0 0 "Shell" 0 -1 1516735823411 ""}
199 
{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823422 ""}
200 
{ "Info" "rivierapro_setup.tcl" "" "2018.01.23.17:30:23 Info:     aldec" {  } {  } 0 0 "2018.01.23.17:30:23 Info:     aldec" 0 0 "Shell" 0 -1 1516735823423 ""}
201 
{ "Info" "." "" "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" {  } {  } 0 0 "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823423 ""}
202 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." {  } {  } 0 0 "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." 0 0 "Shell" 0 -1 1516735823424 ""}
203 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." {  } {  } 0 0 "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735823424 ""}
204 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735823425 ""}
205 
{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735823430 ""}
206 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Reading input file" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Reading input file" 0 0 "Shell" 0 -1 1516735823456 ""}
207 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823461 ""}
208 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module auto_start" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735823461 ""}
209 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735823462 ""}
210 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clk_0" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735823463 ""}
211 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823464 ""}
212 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735823464 ""}
213 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823465 ""}
214 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735823466 ""}
215 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823466 ""}
216 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735823467 ""}
217 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823468 ""}
218 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735823472 ""}
219 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823473 ""}
220 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_info" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735823474 ""}
221 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823475 ""}
222 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735823475 ""}
223 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823476 ""}
224 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735823477 ""}
225 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823484 ""}
226 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735823484 ""}
227 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823486 ""}
228 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735823487 ""}
229 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823488 ""}
230 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735823488 ""}
231 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823489 ""}
232 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735823490 ""}
233 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735823491 ""}
234 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module hps_0" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735823496 ""}
235 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823514 ""}
236 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735823515 ""}
237 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823516 ""}
238 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_disable" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735823517 ""}
239 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823518 ""}
240 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_start" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735823518 ""}
241 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735823519 ""}
242 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module pll_0" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735823521 ""}
243 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823524 ""}
244 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735823524 ""}
245 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823531 ""}
246 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735823531 ""}
247 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823532 ""}
248 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735823533 ""}
249 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823539 ""}
250 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735823542 ""}
251 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823543 ""}
252 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735823543 ""}
253 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823544 ""}
254 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735823546 ""}
255 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Building connections" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Building connections" 0 0 "Shell" 0 -1 1516735823547 ""}
256 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing connections" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735823550 ""}
257 
{ "Info" "" "" "2018.01.23.17:30:23 Info: Validating" {  } {  } 0 0 "2018.01.23.17:30:23 Info: Validating" 0 0 "Shell" 0 -1 1516735823560 ""}
258 
{ "Info" "" "" "2018.01.23.17:30:31 Info: Done reading input file" {  } {  } 0 0 "2018.01.23.17:30:31 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735831710 ""}
259 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833912 ""}
260 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
261 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
262 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
263 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
264 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
265 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
266 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""}
267 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833914 ""}
268 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36" {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36" 0 0 "Shell" 0 -1 1516735833914 ""}
269 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" 0 0 "Shell" 0 -1 1516735833914 ""}
270 
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." {  } {  } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735833914 ""}
271 
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" {  } {  } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735833914 ""}
272 
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" {  } {  } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735833915 ""}
273 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735833918 ""}
274 
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" {  } {  } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735833918 ""}
275 
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" {  } {  } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735833918 ""}
276 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735833918 ""}
277 
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" {  } {  } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735833918 ""}
278 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}
279 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}
280 
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""}
281 
{ "Info" "" "" "2018.01.23.17:30:34 Info: qsys-generate succeeded." {  } {  } 0 0 "2018.01.23.17:30:34 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735834875 ""}
282 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735834876 ""}
283 
{ "Info" "" "" "2018.01.23.17:30:34 Info:" {  } {  } 0 0 "2018.01.23.17:30:34 Info:" 0 0 "Shell" 0 -1 1516735834876 ""}
284 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735834876 ""}
285 
{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735834883 ""}
286 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Reading input file" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Reading input file" 0 0 "Shell" 0 -1 1516735834905 ""}
287 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834909 ""}
288 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module auto_start" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735834909 ""}
289 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735834912 ""}
290 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clk_0" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735834913 ""}
291 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834913 ""}
292 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735834914 ""}
293 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834915 ""}
294 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735834915 ""}
295 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834916 ""}
296 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735834917 ""}
297 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834918 ""}
298 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735834918 ""}
299 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834919 ""}
300 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_info" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735834919 ""}
301 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834920 ""}
302 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735834921 ""}
303 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834921 ""}
304 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735834922 ""}
305 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834923 ""}
306 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735834925 ""}
307 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834926 ""}
308 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735834926 ""}
309 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834927 ""}
310 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735834929 ""}
311 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module hps_0" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735834934 ""}
312 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834943 ""}
313 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735834944 ""}
314 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834946 ""}
315 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_disable" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735834946 ""}
316 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834948 ""}
317 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_start" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735834948 ""}
318 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735834949 ""}
319 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module pll_0" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735834950 ""}
320 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""}
321 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735834953 ""}
322 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""}
323 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735834953 ""}
324 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834954 ""}
325 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735834955 ""}
326 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735834958 ""}
327 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834959 ""}
328 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735834959 ""}
329 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Building connections" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Building connections" 0 0 "Shell" 0 -1 1516735834960 ""}
330 
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" {  } {  } 0 0 "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" 0 0 "Shell" 0 -1 1516735834965 ""}
331 
{ "Info" "" "" "2018.01.23.17:30:41 Info: Done reading input file" {  } {  } 0 0 "2018.01.23.17:30:41 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735841270 ""}
332 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843344 ""}
333 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
334 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
335 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
336 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
337 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
338 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
339 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
340 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""}
341 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36" {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0  m = 36" 0 0 "Shell" 0 -1 1516735843346 ""}
342 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" 0 0 "Shell" 0 -1 1516735843346 ""}
343 
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." {  } {  } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735843346 ""}
344 
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" {  } {  } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735843346 ""}
345 
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" {  } {  } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735843346 ""}
346 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735843348 ""}
347 
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" {  } {  } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735843349 ""}
348 
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" {  } {  } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735843349 ""}
349 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735843349 ""}
350 
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" {  } {  } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735843349 ""}
351 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}
352 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}
353 
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." {  } {  } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""}
354 
{ "Info" "" "" "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" {  } {  } 0 0 "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" 0 0 "Shell" 0 -1 1516735846790 ""}
355 
{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" {  } {  } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735856250 ""}
356 
{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" {  } {  } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735856250 ""}
357 
{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" {  } {  } 0 0 "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858344 ""}
358 
{ "Info" "ulight_fifo_auto_start_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:30:58 Info: auto_start:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" {  } {  } 0 0 "2018.01.23.17:30:58 Info: auto_start:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" 0 0 "Shell" 0 -1 1516735858345 ""}
359 
{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" {  } {  } 0 0 "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858460 ""}
360 
{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" {  } {  } 0 0 "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735858461 ""}
361 
{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" {  } {  } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858554 ""}
362 
{ "Info" "ulight_fifo_clock_sel_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:30:58 Info: clock_sel:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" {  } {  } 0 0 "2018.01.23.17:30:58 Info: clock_sel:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" 0 0 "Shell" 0 -1 1516735858555 ""}
363 
{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" {  } {  } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858668 ""}
364 
{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" {  } {  } 0 0 "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735858670 ""}
365 
{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" {  } {  } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858778 ""}
366 
{ "Info" "ulight_fifo_counter_rx_fifo_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:30:58 Info: counter_rx_fifo:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" {  } {  } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" 0 0 "Shell" 0 -1 1516735858778 ""}
367 
{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" {  } {  } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858895 ""}
368 
{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" {  } {  } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735858898 ""}
369 
{ "Info" "" "" "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" {  } {  } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735858988 ""}
370 
{ "Info" "ulight_fifo_data_flag_rx_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:30:58 Info: data_flag_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" {  } {  } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" 0 0 "Shell" 0 -1 1516735858988 ""}
371 
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" {  } {  } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735859104 ""}
372 
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" {  } {  } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735859105 ""}
373 
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" {  } {  } 0 0 "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859198 ""}
374 
{ "Info" "ulight_fifo_data_info_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:30:59 Info: data_info:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" {  } {  } 0 0 "2018.01.23.17:30:59 Info: data_info:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" 0 0 "Shell" 0 -1 1516735859199 ""}
375 
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" {  } {  } 0 0 "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859311 ""}
376 
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" {  } {  } 0 0 "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735859312 ""}
377 
{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" {  } {  } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859420 ""}
378 
{ "Info" "ulight_fifo_fifo_empty_rx_status_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" {  } {  } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" 0 0 "Shell" 0 -1 1516735859420 ""}
379 
{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" {  } {  } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859548 ""}
380 
{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" {  } {  } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735859548 ""}
381 
{ "Info" "" "" "2018.01.23.17:30:59 Info: hps_0: \"Running  for module: hps_0\"" {  } {  } 0 0 "2018.01.23.17:30:59 Info: hps_0: \"Running  for module: hps_0\"" 0 0 "Shell" 0 -1 1516735859549 ""}
382 
{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0  m = 36" {  } {  } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0  m = 36" 0 0 "Shell" 0 -1 1516735860279 ""}
383 
{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" {  } {  } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 19" 0 0 "Shell" 0 -1 1516735860805 ""}
384 
{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." {  } {  } 0 0 "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735860809 ""}
385 
{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" {  } {  } 0 0 "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735860825 ""}
386 
{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" {  } {  } 0 0 "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735860912 ""}
387 
{ "Info" "" "" "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" {  } {  } 0 0 "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735861270 ""}
388 
{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" {  } {  } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861415 ""}
389 
{ "Info" "ulight_fifo_led_pio_test_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:31:01 Info: led_pio_test:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" {  } {  } 0 0 "2018.01.23.17:31:01 Info: led_pio_test:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" 0 0 "Shell" 0 -1 1516735861415 ""}
390 
{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" {  } {  } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861536 ""}
391 
{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" {  } {  } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735861537 ""}
392 
{ "Info" "" "" "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" {  } {  } 0 0 "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735861569 ""}
393 
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861676 ""}
394 
{ "Info" "ulight_fifo_timecode_rx_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:31:01 Info: timecode_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_rx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" 0 0 "Shell" 0 -1 1516735861676 ""}
395 
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861788 ""}
396 
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735861789 ""}
397 
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861875 ""}
398 
{ "Info" "ulight_fifo_timecode_tx_data_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:31:01 Info: timecode_tx_data:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" 0 0 "Shell" 0 -1 1516735861876 ""}
399 
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861988 ""}
400 
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" {  } {  } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735861989 ""}
401 
{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" {  } {  } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862097 ""}
402 
{ "Info" "ulight_fifo_write_data_fifo_tx_component_configuration.pl  --do_build_sim=0  ]" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/" {  } {  } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx:   Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/" 0 0 "Shell" 0 -1 1516735862097 ""}
403 
{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" {  } {  } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862210 ""}
404 
{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" {  } {  } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735862211 ""}
405 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863534 ""}
406 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863572 ""}
407 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863611 ""}
408 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863671 ""}
409 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863741 ""}
410 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863801 ""}
411 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863855 ""}
412 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863921 ""}
413 
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863979 ""}
414 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864040 ""}
415 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864101 ""}
416 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864161 ""}
417 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864253 ""}
418 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864297 ""}
419 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864334 ""}
420 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864391 ""}
421 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864443 ""}
422 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864499 ""}
423 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864548 ""}
424 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864595 ""}
425 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864650 ""}
426 
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" {  } {  } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864729 ""}
427 
{ "Info" "" "" "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735866289 ""}
428 
{ "Info" "" "" "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735866293 ""}
429 
{ "Info" "" "" "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735866347 ""}
430 
{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735866457 ""}
431 
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735866458 ""}
432 
{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735866460 ""}
433 
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735866461 ""}
434 
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735866463 ""}
435 
{ "Info" "" "" "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735866471 ""}
436 
{ "Info" "" "" "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735866481 ""}
437 
{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735866484 ""}
438 
{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" {  } {  } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866484 ""}
439 
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735866489 ""}
440 
{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" {  } {  } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866490 ""}
441 
{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" {  } {  } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866491 ""}
442 
{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735866497 ""}
443 
{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735866516 ""}
444 
{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735866526 ""}
445 
{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735866542 ""}
446 
{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" {  } {  } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866544 ""}
447 
{ "Info" "" "" "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" {  } {  } 0 0 "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735866567 ""}
448 
{ "Info" "" "" "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" {  } {  } 0 0 "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735908549 ""}
449 
{ "Info" "" "" "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" {  } {  } 0 0 "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735908640 ""}
450 
{ "Info" "" "" "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" {  } {  } 0 0 "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" 0 0 "Shell" 0 -1 1516735908640 ""}
451 
{ "Info" "" "" "2018.01.23.17:31:49 Info: qsys-generate succeeded." {  } {  } 0 0 "2018.01.23.17:31:49 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735909794 ""}
452 
{ "Info" "" "" "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" {  } {  } 0 0 "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735909794 ""}
453 
{ "Info" "IIPMAN_IPRGEN_SUCCESSFUL" "Qsys ulight_fifo.qsys " "Completed upgrading IP component Qsys with file \"ulight_fifo.qsys\"" {  } {  } 0 11131 "Completed upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735919862 ""}
454 
{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "/home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script /home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" {  } {  } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1516735929556 ""}
455 
{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 30 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1063 " "Peak virtual memory: 1063 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 23 17:32:09 2018 " "Processing ended: Tue Jan 23 17:32:09 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:09 " "Elapsed time: 00:05:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:27 " "Total CPU time (on all processors): 00:08:27" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1516735929557 ""}

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