OpenCores
URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [hps_isw_handoff/] [ulight_fifo_hps_0/] [sdram_io.h] - Blame information for rev 32

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 redbear
/*
2
 * Copyright Altera Corporation (C) 2012-2014. All rights reserved
3
 *
4
 * SPDX-License-Identifier:    BSD-3-Clause
5
 *
6
 * Redistribution and use in source and binary forms, with or without
7
 * modification, are permitted provided that the following conditions are met:
8
 *    * Redistributions of source code must retain the above copyright
9
 *      notice, this list of conditions and the following disclaimer.
10
 *    * Redistributions in binary form must reproduce the above copyright
11
 *      notice, this list of conditions and the following disclaimer in the
12
 *      documentation and/or other materials provided with the distribution.
13
 *    * Neither the name of Altera Corporation nor the
14
 *      names of its contributors may be used to endorse or promote products
15
 *      derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
18
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
19
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
20
 * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
21
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
#include <sdram.h>
30
 
31
#define MGR_SELECT_MASK   0xf8000
32
 
33
#define APB_BASE_SCC_MGR        SDR_PHYGRP_SCCGRP_ADDRESS
34
#define APB_BASE_PHY_MGR        SDR_PHYGRP_PHYMGRGRP_ADDRESS
35
#define APB_BASE_RW_MGR         SDR_PHYGRP_RWMGRGRP_ADDRESS
36
#define APB_BASE_DATA_MGR       SDR_PHYGRP_DATAMGRGRP_ADDRESS
37
#define APB_BASE_REG_FILE       SDR_PHYGRP_REGFILEGRP_ADDRESS
38
#define APB_BASE_MMR            SDR_CTRLGRP_ADDRESS
39
 
40
#define __AVL_TO_APB(ADDR) \
41
        ((((ADDR) & MGR_SELECT_MASK) == (BASE_PHY_MGR))  ? (APB_BASE_PHY_MGR)  | (((ADDR) >> (14-6)) & (0x1<<6))  | ((ADDR) & 0x3f) : \
42
         (((ADDR) & MGR_SELECT_MASK) == (BASE_RW_MGR))   ? (APB_BASE_RW_MGR)   | ((ADDR) & 0x1fff) : \
43
         (((ADDR) & MGR_SELECT_MASK) == (BASE_DATA_MGR)) ? (APB_BASE_DATA_MGR) | ((ADDR) & 0x7ff) : \
44
         (((ADDR) & MGR_SELECT_MASK) == (BASE_SCC_MGR))  ? (APB_BASE_SCC_MGR)  | ((ADDR) & 0xfff) : \
45
         (((ADDR) & MGR_SELECT_MASK) == (BASE_REG_FILE)) ? (APB_BASE_REG_FILE) | ((ADDR) & 0x7ff) : \
46
         (((ADDR) & MGR_SELECT_MASK) == (BASE_MMR))      ? (APB_BASE_MMR)      | ((ADDR) & 0xfff) : \
47
         -1)
48
 
49
#define IOWR_32DIRECT(BASE, OFFSET, DATA) \
50
        write_register(HPS_SDR_BASE, __AVL_TO_APB((alt_u32)((BASE) + (OFFSET))), DATA)
51
 
52
#define IORD_32DIRECT(BASE, OFFSET) \
53
        read_register(HPS_SDR_BASE, __AVL_TO_APB((alt_u32)((BASE) + (OFFSET))))
54
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.