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redbear |
/*
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* Copyright Altera Corporation (C) 2012-2014. All rights reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Altera Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "sequencer_defines.h"
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#if ENABLE_TCL_DEBUG
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#include "alt_types.h"
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#if HPS_HW
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#include "sdram_io.h"
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#else
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#include "io.h"
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#include "system.h"
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#endif
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#include "tclrpt.h"
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#include "sequencer.h"
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#if BFM_MODE
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#include <stdio.h>
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#endif
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/* TCL io memory */
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volatile debug_summary_report_t *debug_summary_report;
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volatile debug_cal_report_t *debug_cal_report;
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volatile debug_margin_report_t *debug_margin_report;
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volatile debug_printf_output_t *debug_printf_output;
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volatile debug_data_t *debug_data;
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volatile emif_toolkit_debug_data_t *debug_emif_toolkit_debug_data;
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alt_u32 tclrpt_get_protocol(void)
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{
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// Determine the protocol for the interface. Currently this is
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// done with #defines
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alt_u32 protocol_enum = 0;
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#if DDR3
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protocol_enum = 1;
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#endif
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#if DDR2
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protocol_enum = 2;
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#endif
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#if QDRII
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protocol_enum = 3;
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#endif
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#if RLDRAMII
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protocol_enum = 4;
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#endif
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#if RLDRAM3
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protocol_enum = 5;
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#endif
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#if LPDDR2
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protocol_enum = 6;
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#endif
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return protocol_enum;
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}
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alt_u32 tclrpt_get_rate(void)
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{
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alt_u32 rate_enum;
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rate_enum = 0;
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// Right now the rate is determined by ifdefs
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#if QUARTER_RATE
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rate_enum = 4;
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#else
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#if HALF_RATE
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rate_enum = 2;
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#else
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rate_enum = 1;
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#endif
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#endif
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return rate_enum;
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}
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void tclrpt_update_rank_group_mask(void)
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{
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alt_u32 i;
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alt_u32 active_groups;
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alt_u32 active_ranks;
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alt_u32 rank;
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alt_u32 rank_mask_word;
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alt_u32 shadow_reg;
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alt_u32 skip_shadow_reg;
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// Currently the alt_u32 word param->skip_groups keeps all the groups.
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TCLRPT_SET(debug_summary_report->group_mask[0], param->skip_groups);
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active_groups = RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
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for (i = 0; i < 32; i++)
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{
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if (param->skip_groups & (1 << i))
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{
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active_groups--;
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}
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}
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TCLRPT_SET(debug_summary_report->active_groups, active_groups);
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// Iterate through the ranks array and set the bits
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active_ranks = RW_MGR_MEM_NUMBER_OF_RANKS;
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for (rank_mask_word = 0; rank_mask_word < NUM_RANK_MASK_WORDS; rank_mask_word++)
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{
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for (rank = rank_mask_word*32; rank < RW_MGR_MEM_NUMBER_OF_RANKS; rank++)
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{
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if (param->skip_ranks[rank]) {
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active_ranks--;
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TCLRPT_SET(debug_summary_report->rank_mask[rank_mask_word], debug_summary_report->rank_mask[rank_mask_word] | (1 << (rank-(32*rank_mask_word))));
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}
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}
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}
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// Update skip_shadow_regs
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for (shadow_reg = 0, rank = 0; shadow_reg < NUM_SHADOW_REGS; ++shadow_reg, rank += NUM_RANKS_PER_SHADOW_REG)
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{
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skip_shadow_reg = 1;
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for (i = 0; i < NUM_RANKS_PER_SHADOW_REG; ++i)
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{
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if (! param->skip_ranks[rank + i])
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{
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skip_shadow_reg = 0;
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break;
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}
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}
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param->skip_shadow_regs[shadow_reg] = skip_shadow_reg;
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}
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TCLRPT_SET(debug_summary_report->active_ranks, active_ranks);
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}
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void tclrpt_initialize_rank_group_mask(void)
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{
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alt_u32 group_mask;
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alt_u32 rank_mask_word;
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// Initialize the globals
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TCLRPT_SET(debug_summary_report->rank_mask_size, NUM_RANK_MASK_WORDS);
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TCLRPT_SET(debug_summary_report->active_ranks, debug_summary_report->mem_num_ranks);
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TCLRPT_SET(debug_summary_report->group_mask_size, NUM_GROUP_MASK_WORDS);
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TCLRPT_SET(debug_summary_report->active_groups, debug_summary_report->mem_write_dqs_width);
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// Initialize all words to be 0
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for (group_mask = 0; group_mask < NUM_GROUP_MASK_WORDS; group_mask++)
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{
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TCLRPT_SET(debug_summary_report->group_mask[group_mask], 0);
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}
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for (rank_mask_word = 0; rank_mask_word < NUM_RANK_MASK_WORDS; rank_mask_word++)
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{
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TCLRPT_SET(debug_summary_report->rank_mask[rank_mask_word], 0);
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}
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}
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void tclrpt_clear_calibrated_groups_index(void)
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{
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alt_u32 group_mask;
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// Initialize all words to be 0
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for (group_mask = 0; group_mask < NUM_GROUP_MASK_WORDS; group_mask++)
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{
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TCLRPT_SET(debug_summary_report->groups_attempted_calibration[group_mask], 0);
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}
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}
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void tclrpt_set_group_as_calibration_attempted(alt_u32 write_group)
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{
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#if ENABLE_TCL_DEBUG
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alt_u32 group_mask_word;
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alt_u32 group_mask_bit;
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alt_u32 calibrated_groups;
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group_mask_word = write_group / 32;
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group_mask_bit = write_group - group_mask_word*32;
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calibrated_groups = debug_summary_report->groups_attempted_calibration[group_mask_word];
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calibrated_groups |= 1 << group_mask_bit;
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TCLRPT_SET(debug_summary_report->groups_attempted_calibration[group_mask_word], calibrated_groups);
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#endif
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}
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void tclrpt_initialize_calib_settings(void)
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{
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alt_u32 read_group, write_group, dq, dm, sr;
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for (sr = 0; sr < NUM_SHADOW_REGS; sr++) {
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// Initialize the margins observed during calibration
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for (read_group = 0; read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH; read_group++)
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{
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TCLRPT_SET(debug_cal_report->cal_dqs_in_margins[sr][read_group].dq_margin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_in_margins[sr][read_group].dqs_margin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_in_margins[sr][read_group].dqsen_margin, 0);
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}
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for (read_group = 0; read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH; read_group++)
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{
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].vfifo_begin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].phase_begin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].delay_begin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].work_begin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].vfifo_end, 0);
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].phase_end, 0);
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].delay_end, 0);
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TCLRPT_SET(debug_cal_report->cal_dqsen_margins[sr][read_group].work_end, 0);
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}
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for (write_group = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++)
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{
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TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[sr][write_group].dq_margin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[sr][write_group].dm_margin, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[sr][write_group].dqdqs_start, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[sr][write_group].dqdqs_end, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_margins[sr][write_group].dqs_margin, 0);
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}
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for (dq = 0; dq < RW_MGR_MEM_DATA_WIDTH; dq++)
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{
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TCLRPT_SET(debug_cal_report->cal_dq_in_margins[sr][dq].left_edge, 0);
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TCLRPT_SET(debug_cal_report->cal_dq_in_margins[sr][dq].right_edge, 0);
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TCLRPT_SET(debug_cal_report->cal_dq_out_margins[sr][dq].left_edge, 0);
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TCLRPT_SET(debug_cal_report->cal_dq_out_margins[sr][dq].right_edge, 0);
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}
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for (write_group = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++)
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{
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for (dm = 0; dm < RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP; dm++)
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{
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TCLRPT_SET(debug_cal_report->cal_dm_margins[sr][write_group][dm].left_edge, 0);
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TCLRPT_SET(debug_cal_report->cal_dm_margins[sr][write_group][dm].right_edge, 0);
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}
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}
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// Initialize the DQ and DQS settings
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for (read_group = 0; read_group < RW_MGR_MEM_IF_READ_DQS_WIDTH; read_group++)
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{
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TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[sr][read_group].dqs_en_delay, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[sr][read_group].dqs_en_phase, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[sr][read_group].dqs_bus_in_delay, 0);
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#if TRACKING_ERROR_TEST || TRACKING_WATCH_TEST
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TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[sr][read_group].sample_count, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_in_settings[sr][read_group].dtaps_per_ptap, 0);
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#endif
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| 274 |
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}
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| 275 |
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for (write_group = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++)
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| 276 |
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{
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| 277 |
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TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[sr][write_group].dqdqs_out_phase, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[sr][write_group].dqs_out_delay1, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[sr][write_group].dqs_out_delay2, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[sr][write_group].oct_out_delay1, 0);
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TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[sr][write_group].oct_out_delay2, 0);
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| 282 |
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TCLRPT_SET(debug_cal_report->cal_dqs_out_settings[sr][write_group].dqs_io_in_delay, 0);
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| 283 |
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}
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| 284 |
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for (dq = 0; dq < RW_MGR_MEM_DATA_WIDTH; dq++)
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| 285 |
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{
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| 286 |
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TCLRPT_SET(debug_cal_report->cal_dq_settings[sr][dq].dq_in_delay, 0);
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| 287 |
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TCLRPT_SET(debug_cal_report->cal_dq_settings[sr][dq].dq_out_delay1, 0);
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| 288 |
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TCLRPT_SET(debug_cal_report->cal_dq_settings[sr][dq].dq_out_delay2, 0);
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| 289 |
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}
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| 290 |
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| 291 |
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for (write_group = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++)
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| 292 |
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{
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| 293 |
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for (dm = 0; dm < RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP; dm++)
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| 294 |
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{
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| 295 |
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TCLRPT_SET(debug_cal_report->cal_dm_settings[sr][write_group][dm].dm_in_delay, 0);
|
| 296 |
|
|
TCLRPT_SET(debug_cal_report->cal_dm_settings[sr][write_group][dm].dm_out_delay1, 0);
|
| 297 |
|
|
TCLRPT_SET(debug_cal_report->cal_dm_settings[sr][write_group][dm].dm_out_delay2, 0);
|
| 298 |
|
|
}
|
| 299 |
|
|
}
|
| 300 |
|
|
}
|
| 301 |
|
|
}
|
| 302 |
|
|
|
| 303 |
|
|
void tclrpt_initialize_margins(void)
|
| 304 |
|
|
{
|
| 305 |
|
|
alt_u32 write_group, dq, dm, sr;
|
| 306 |
|
|
|
| 307 |
|
|
|
| 308 |
|
|
TCLRPT_SET(debug_margin_report->mem_data_width, RW_MGR_MEM_DATA_WIDTH);
|
| 309 |
|
|
TCLRPT_SET(debug_margin_report->mem_write_dqs_width, RW_MGR_MEM_IF_WRITE_DQS_WIDTH);
|
| 310 |
|
|
TCLRPT_SET(debug_margin_report->num_shadow_regs, NUM_SHADOW_REGS);
|
| 311 |
|
|
|
| 312 |
|
|
// Initialize the margins
|
| 313 |
|
|
for (sr = 0; sr < NUM_SHADOW_REGS; sr++)
|
| 314 |
|
|
{
|
| 315 |
|
|
for (write_group = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++)
|
| 316 |
|
|
{
|
| 317 |
|
|
for (dm = 0; dm < RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP; dm++)
|
| 318 |
|
|
{
|
| 319 |
|
|
TCLRPT_SET(debug_margin_report->margin_dm_margins[sr][write_group][dm].max_working_setting, 0);
|
| 320 |
|
|
TCLRPT_SET(debug_margin_report->margin_dm_margins[sr][write_group][dm].min_working_setting, 0);
|
| 321 |
|
|
}
|
| 322 |
|
|
}
|
| 323 |
|
|
for (dq = 0; dq < RW_MGR_MEM_DATA_WIDTH; dq++)
|
| 324 |
|
|
{
|
| 325 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_in_margins[sr][dq].max_working_setting, 0);
|
| 326 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_in_margins[sr][dq].min_working_setting, 0);
|
| 327 |
|
|
}
|
| 328 |
|
|
for (dq = 0; dq < RW_MGR_MEM_DATA_WIDTH; dq++)
|
| 329 |
|
|
{
|
| 330 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_out_margins[sr][dq].max_working_setting, 0);
|
| 331 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_out_margins[sr][dq].min_working_setting, 0);
|
| 332 |
|
|
}
|
| 333 |
|
|
}
|
| 334 |
|
|
}
|
| 335 |
|
|
|
| 336 |
|
|
void tclrpt_initialize_calib_results(void)
|
| 337 |
|
|
{
|
| 338 |
|
|
alt_u32 write_group, sr;
|
| 339 |
|
|
|
| 340 |
|
|
// Initialize the FOM and error status
|
| 341 |
|
|
TCLRPT_SET(debug_summary_report->error_stage, CAL_STAGE_CAL_SKIPPED);
|
| 342 |
|
|
TCLRPT_SET(debug_summary_report->error_group, 0xff);
|
| 343 |
|
|
TCLRPT_SET(debug_summary_report->fom_in, 0);
|
| 344 |
|
|
TCLRPT_SET(debug_summary_report->fom_out, 0);
|
| 345 |
|
|
|
| 346 |
|
|
for (sr = 0; sr < NUM_SHADOW_REGS; sr++) {
|
| 347 |
|
|
// Initialize the per group calibration report
|
| 348 |
|
|
for (write_group = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++)
|
| 349 |
|
|
{
|
| 350 |
|
|
TCLRPT_SET(debug_cal_report->cal_status_per_group[sr][write_group].fom_in, 0);
|
| 351 |
|
|
TCLRPT_SET(debug_cal_report->cal_status_per_group[sr][write_group].fom_out, 0);
|
| 352 |
|
|
TCLRPT_SET(debug_cal_report->cal_status_per_group[sr][write_group].error_stage, CAL_STAGE_CAL_SKIPPED);
|
| 353 |
|
|
}
|
| 354 |
|
|
}
|
| 355 |
|
|
}
|
| 356 |
|
|
|
| 357 |
|
|
void tclrpt_initialize_calib_latency(void)
|
| 358 |
|
|
{
|
| 359 |
|
|
// KALEN: Need to figure out the best way to return the calibrated
|
| 360 |
|
|
// read and write latencies. For now leave as blank
|
| 361 |
|
|
TCLRPT_SET(debug_summary_report->cal_write_latency, 0);
|
| 362 |
|
|
TCLRPT_SET(debug_summary_report->cal_read_latency, 0);
|
| 363 |
|
|
|
| 364 |
|
|
}
|
| 365 |
|
|
|
| 366 |
|
|
void tclrpt_initialize_printf_output(void)
|
| 367 |
|
|
{
|
| 368 |
|
|
// Initialize the pointers
|
| 369 |
|
|
debug_printf_output->head = 0;
|
| 370 |
|
|
debug_printf_output->count = 0;
|
| 371 |
|
|
debug_printf_output->slave_lock = 0;
|
| 372 |
|
|
debug_printf_output->master_lock = 0;
|
| 373 |
|
|
debug_printf_output->fifo_size = PRINTF_READ_BUFFER_FIFO_WORDS;
|
| 374 |
|
|
debug_printf_output->word_size = PRINTF_READ_BUFFER_SIZE;
|
| 375 |
|
|
}
|
| 376 |
|
|
|
| 377 |
|
|
void tclrpt_initialize_emif_toolkit_debug_data(void)
|
| 378 |
|
|
{
|
| 379 |
|
|
// Initialize the points to the calibration data
|
| 380 |
|
|
debug_emif_toolkit_debug_data->dqs_write_width_ptr = (alt_u32)(&debug_summary_report->mem_write_dqs_width);
|
| 381 |
|
|
debug_emif_toolkit_debug_data->group_mask_ptr = (alt_u32)(&debug_summary_report->group_mask);
|
| 382 |
|
|
debug_emif_toolkit_debug_data->num_ranks_ptr = (alt_u32)(&debug_summary_report->mem_num_ranks);
|
| 383 |
|
|
debug_emif_toolkit_debug_data->rank_mask_ptr = (alt_u32)(&debug_summary_report->rank_mask);
|
| 384 |
|
|
debug_emif_toolkit_debug_data->active_groups_ptr = (alt_u32)(&debug_summary_report->active_groups);
|
| 385 |
|
|
debug_emif_toolkit_debug_data->active_ranks_ptr = (alt_u32)(&debug_summary_report->active_ranks);
|
| 386 |
|
|
debug_emif_toolkit_debug_data->group_mask_size_ptr = (alt_u32)(&debug_summary_report->group_mask_size);
|
| 387 |
|
|
debug_emif_toolkit_debug_data->rank_mask_size_ptr = (alt_u32)(&debug_summary_report->rank_mask_size);
|
| 388 |
|
|
}
|
| 389 |
|
|
|
| 390 |
|
|
void tclrpt_initialize_data(void)
|
| 391 |
|
|
{
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
// Set the initial value of the report flags
|
| 395 |
|
|
debug_summary_report->report_flags = 0;
|
| 396 |
|
|
debug_cal_report->report_flags = 0;
|
| 397 |
|
|
debug_margin_report->report_flags = 0;
|
| 398 |
|
|
|
| 399 |
|
|
// Set which reports are enabled based on the global structure.
|
| 400 |
|
|
// This only applies to the calibration and margining report
|
| 401 |
|
|
TCLRPT_SET(debug_summary_report->report_flags, debug_summary_report->report_flags |= DEBUG_REPORT_STATUS_REPORT_GEN_ENABLED);
|
| 402 |
|
|
|
| 403 |
|
|
if (gbl->phy_debug_mode_flags & PHY_DEBUG_ENABLE_CAL_RPT)
|
| 404 |
|
|
{
|
| 405 |
|
|
TCLRPT_SET(debug_cal_report->report_flags, debug_cal_report->report_flags |= DEBUG_REPORT_STATUS_REPORT_GEN_ENABLED);
|
| 406 |
|
|
}
|
| 407 |
|
|
if (gbl->phy_debug_mode_flags & PHY_DEBUG_ENABLE_MARGIN_RPT)
|
| 408 |
|
|
{
|
| 409 |
|
|
TCLRPT_SET(debug_margin_report->report_flags, debug_margin_report->report_flags |= DEBUG_REPORT_STATUS_REPORT_GEN_ENABLED);
|
| 410 |
|
|
}
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
// Initialize the static data into the report
|
| 414 |
|
|
|
| 415 |
|
|
TCLRPT_SET(debug_summary_report->protocol, tclrpt_get_protocol());
|
| 416 |
|
|
#if !HPS_HW
|
| 417 |
|
|
TCLRPT_SET(debug_summary_report->sequencer_signature, IORD_32DIRECT (REG_FILE_SIGNATURE, 0));
|
| 418 |
|
|
#endif
|
| 419 |
|
|
|
| 420 |
|
|
// If available, use ROW/COL addr width as they have the true width,
|
| 421 |
|
|
// not the static width used by the AC ROM.
|
| 422 |
|
|
#if MEM_IF_ROW_ADDR_WIDTH
|
| 423 |
|
|
#if MEM_IF_COL_ADDR_WIDTH
|
| 424 |
|
|
TCLRPT_SET(debug_summary_report->mem_address_width, (MEM_IF_COL_ADDR_WIDTH > MEM_IF_ROW_ADDR_WIDTH) ? MEM_IF_COL_ADDR_WIDTH : MEM_IF_ROW_ADDR_WIDTH);
|
| 425 |
|
|
#else
|
| 426 |
|
|
TCLRPT_SET(debug_summary_report->mem_address_width, RW_MGR_MEM_ADDRESS_WIDTH);
|
| 427 |
|
|
#endif
|
| 428 |
|
|
#else
|
| 429 |
|
|
TCLRPT_SET(debug_summary_report->mem_address_width, RW_MGR_MEM_ADDRESS_WIDTH);
|
| 430 |
|
|
#endif
|
| 431 |
|
|
|
| 432 |
|
|
TCLRPT_SET(debug_summary_report->mem_bank_width, RW_MGR_MEM_BANK_WIDTH);
|
| 433 |
|
|
TCLRPT_SET(debug_summary_report->mem_control_width, RW_MGR_MEM_CONTROL_WIDTH);
|
| 434 |
|
|
TCLRPT_SET(debug_summary_report->mem_cs_width, RW_MGR_MEM_CHIP_SELECT_WIDTH);
|
| 435 |
|
|
TCLRPT_SET(debug_summary_report->mem_cke_width, RW_MGR_MEM_CLK_EN_WIDTH);
|
| 436 |
|
|
TCLRPT_SET(debug_summary_report->mem_odt_width, RW_MGR_MEM_ODT_WIDTH);
|
| 437 |
|
|
TCLRPT_SET(debug_summary_report->mem_data_width, RW_MGR_MEM_DATA_WIDTH);
|
| 438 |
|
|
TCLRPT_SET(debug_summary_report->mem_dm_width, RW_MGR_TRUE_MEM_DATA_MASK_WIDTH);
|
| 439 |
|
|
TCLRPT_SET(debug_summary_report->mem_read_dqs_width, RW_MGR_MEM_IF_READ_DQS_WIDTH);
|
| 440 |
|
|
TCLRPT_SET(debug_summary_report->mem_write_dqs_width, RW_MGR_MEM_IF_WRITE_DQS_WIDTH);
|
| 441 |
|
|
TCLRPT_SET(debug_summary_report->mem_dq_per_read_dqs, RW_MGR_MEM_DQ_PER_READ_DQS);
|
| 442 |
|
|
TCLRPT_SET(debug_summary_report->mem_num_ranks, RW_MGR_MEM_NUMBER_OF_RANKS);
|
| 443 |
|
|
|
| 444 |
|
|
#if DDRX
|
| 445 |
|
|
#if LPDDR2
|
| 446 |
|
|
TCLRPT_SET(debug_summary_report->mem_mmr_burst_len, MEM_BURST_LEN);
|
| 447 |
|
|
#else
|
| 448 |
|
|
TCLRPT_SET(debug_summary_report->mem_mmr_burst_len, RW_MGR_MR0_BL);
|
| 449 |
|
|
#endif
|
| 450 |
|
|
#else
|
| 451 |
|
|
TCLRPT_SET(debug_summary_report->mem_mmr_burst_len, MEM_BURST_LEN);
|
| 452 |
|
|
#endif
|
| 453 |
|
|
TCLRPT_SET(debug_summary_report->mem_mmr_cas, RW_MGR_MR0_CAS_LATENCY);
|
| 454 |
|
|
|
| 455 |
|
|
TCLRPT_SET(debug_summary_report->mem_num_dm_per_write_group, RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP);
|
| 456 |
|
|
|
| 457 |
|
|
TCLRPT_SET(debug_summary_report->rate, tclrpt_get_rate());
|
| 458 |
|
|
|
| 459 |
|
|
TCLRPT_SET(debug_summary_report->dll_length, IO_DLL_CHAIN_LENGTH);
|
| 460 |
|
|
|
| 461 |
|
|
TCLRPT_SET(debug_summary_report->num_shadow_regs, NUM_SHADOW_REGS);
|
| 462 |
|
|
|
| 463 |
|
|
// Initialize the timing data
|
| 464 |
|
|
TCLRPT_SET(debug_summary_report->computed_dtap_per_ptap, 0);
|
| 465 |
|
|
TCLRPT_SET(debug_summary_report->io_delay_per_opa_tap, IO_DELAY_PER_OPA_TAP);
|
| 466 |
|
|
|
| 467 |
|
|
// Initialize the margin maxes
|
| 468 |
|
|
TCLRPT_SET(debug_summary_report->margin_dq_in_left_delay_chain_len, IO_IO_IN_DELAY_MAX + 1);
|
| 469 |
|
|
TCLRPT_SET(debug_summary_report->margin_dq_in_right_delay_chain_len, IO_DQS_IN_DELAY_MAX + 1);
|
| 470 |
|
|
TCLRPT_SET(debug_summary_report->margin_dq_out_left_delay_chain_len, IO_IO_OUT1_DELAY_MAX + 1);
|
| 471 |
|
|
TCLRPT_SET(debug_summary_report->margin_dq_out_right_delay_chain_len, IO_IO_OUT1_DELAY_MAX + 1);
|
| 472 |
|
|
|
| 473 |
|
|
|
| 474 |
|
|
// Initialize the sizes in the calibration tables
|
| 475 |
|
|
TCLRPT_SET(debug_cal_report->mem_data_width, RW_MGR_MEM_DATA_WIDTH);
|
| 476 |
|
|
TCLRPT_SET(debug_cal_report->mem_dm_width, RW_MGR_TRUE_MEM_DATA_MASK_WIDTH);
|
| 477 |
|
|
TCLRPT_SET(debug_cal_report->mem_num_dm_per_write_group, RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP);
|
| 478 |
|
|
TCLRPT_SET(debug_cal_report->mem_read_dqs_width, RW_MGR_MEM_IF_READ_DQS_WIDTH);
|
| 479 |
|
|
TCLRPT_SET(debug_cal_report->mem_write_dqs_width, RW_MGR_MEM_IF_WRITE_DQS_WIDTH);
|
| 480 |
|
|
TCLRPT_SET(debug_cal_report->num_shadow_regs, NUM_SHADOW_REGS);
|
| 481 |
|
|
|
| 482 |
|
|
// Initialize the other members of the data structures
|
| 483 |
|
|
|
| 484 |
|
|
tclrpt_initialize_calib_latency();
|
| 485 |
|
|
|
| 486 |
|
|
tclrpt_initialize_rank_group_mask();
|
| 487 |
|
|
|
| 488 |
|
|
tclrpt_initialize_calib_results();
|
| 489 |
|
|
|
| 490 |
|
|
tclrpt_update_rank_group_mask();
|
| 491 |
|
|
|
| 492 |
|
|
tclrpt_clear_calibrated_groups_index();
|
| 493 |
|
|
|
| 494 |
|
|
tclrpt_initialize_calib_settings();
|
| 495 |
|
|
|
| 496 |
|
|
tclrpt_initialize_margins();
|
| 497 |
|
|
|
| 498 |
|
|
tclrpt_initialize_emif_toolkit_debug_data();
|
| 499 |
|
|
}
|
| 500 |
|
|
|
| 501 |
|
|
void tclrpt_initialize (debug_data_t *debug_data_ptr)
|
| 502 |
|
|
{
|
| 503 |
|
|
alt_u32 i;
|
| 504 |
|
|
|
| 505 |
|
|
/* Set the pointers to the memory used to communicate
|
| 506 |
|
|
* with the TCL scripts.
|
| 507 |
|
|
*/
|
| 508 |
|
|
|
| 509 |
|
|
if (debug_data_ptr == 0)
|
| 510 |
|
|
{
|
| 511 |
|
|
// If the debug data pointer is NULL then initialize to disallow any access
|
| 512 |
|
|
|
| 513 |
|
|
// Set the register file offset for the data to be 0
|
| 514 |
|
|
#if !HPS_HW
|
| 515 |
|
|
IOWR_32DIRECT (REG_FILE_DEBUG_DATA_ADDR, 0, 0);
|
| 516 |
|
|
#endif
|
| 517 |
|
|
|
| 518 |
|
|
// Initialize all pointers to NULL
|
| 519 |
|
|
debug_summary_report = 0;
|
| 520 |
|
|
debug_cal_report = 0;
|
| 521 |
|
|
debug_margin_report = 0;
|
| 522 |
|
|
debug_printf_output = 0;
|
| 523 |
|
|
|
| 524 |
|
|
debug_data = 0;
|
| 525 |
|
|
}
|
| 526 |
|
|
else
|
| 527 |
|
|
{
|
| 528 |
|
|
// Set the register file offset for the data
|
| 529 |
|
|
#if !HPS_HW
|
| 530 |
|
|
IOWR_32DIRECT (REG_FILE_DEBUG_DATA_ADDR, 0, (alt_u32)debug_data_ptr);
|
| 531 |
|
|
#endif
|
| 532 |
|
|
|
| 533 |
|
|
// Set the global pointers
|
| 534 |
|
|
debug_data = debug_data_ptr;
|
| 535 |
|
|
debug_summary_report = &(debug_data->summary_report);
|
| 536 |
|
|
debug_cal_report = &(debug_data->cal_report);
|
| 537 |
|
|
debug_margin_report = &(debug_data->margin_report);
|
| 538 |
|
|
#if ENABLE_PRINTF_LOG
|
| 539 |
|
|
debug_printf_output = &(debug_data->printf_output);
|
| 540 |
|
|
#else
|
| 541 |
|
|
debug_printf_output = 0;
|
| 542 |
|
|
#endif
|
| 543 |
|
|
debug_emif_toolkit_debug_data = &(debug_data->emif_toolkit_debug_data);
|
| 544 |
|
|
|
| 545 |
|
|
|
| 546 |
|
|
|
| 547 |
|
|
// Initialize the status
|
| 548 |
|
|
debug_data->status = 0;
|
| 549 |
|
|
|
| 550 |
|
|
// Update local pointers
|
| 551 |
|
|
debug_data->summary_report_ptr = (alt_u32)debug_summary_report;
|
| 552 |
|
|
debug_data->cal_report_ptr = (alt_u32)debug_cal_report;
|
| 553 |
|
|
debug_data->margin_report_ptr = (alt_u32)debug_margin_report;
|
| 554 |
|
|
#if ENABLE_DQSEN_SWEEP
|
| 555 |
|
|
debug_data->di_report_ptr = (alt_u32)(&debug_data->di_report);
|
| 556 |
|
|
#endif
|
| 557 |
|
|
debug_data->emif_toolkit_debug_data_ptr = (alt_u32)(&debug_data->emif_toolkit_debug_data);
|
| 558 |
|
|
|
| 559 |
|
|
// Set the sizes of the structs
|
| 560 |
|
|
debug_data->data_size = sizeof(debug_data_t);
|
| 561 |
|
|
debug_summary_report->data_size = sizeof(debug_summary_report_t);
|
| 562 |
|
|
debug_cal_report->data_size = sizeof(debug_cal_report_t);
|
| 563 |
|
|
debug_margin_report->data_size = sizeof(debug_margin_report_t);
|
| 564 |
|
|
#if ENABLE_DQSEN_SWEEP
|
| 565 |
|
|
debug_data->di_report.data_size = sizeof(rw_manager_di_report_t);
|
| 566 |
|
|
debug_data->di_report.max_samples = NUM_DI_SAMPLE;
|
| 567 |
|
|
#endif
|
| 568 |
|
|
debug_emif_toolkit_debug_data->data_size = sizeof(emif_toolkit_debug_data_t);
|
| 569 |
|
|
|
| 570 |
|
|
// Set the initial value of the report flags
|
| 571 |
|
|
debug_summary_report->report_flags = 0;
|
| 572 |
|
|
debug_cal_report->report_flags = 0;
|
| 573 |
|
|
debug_margin_report->report_flags = 0;
|
| 574 |
|
|
#if ENABLE_DQSEN_SWEEP
|
| 575 |
|
|
debug_data->di_report.flags = 0;
|
| 576 |
|
|
#endif
|
| 577 |
|
|
|
| 578 |
|
|
// Initialize the command status
|
| 579 |
|
|
debug_data->command_status = TCLDBG_TX_STATUS_CMD_EXE;
|
| 580 |
|
|
debug_data->requested_command = TCLDBG_CMD_NOP;
|
| 581 |
|
|
for (i = 0; i < COMMAND_PARAM_WORDS; i++)
|
| 582 |
|
|
{
|
| 583 |
|
|
debug_data->command_parameters[i] = 0;
|
| 584 |
|
|
}
|
| 585 |
|
|
|
| 586 |
|
|
#if ENABLE_PRINTF_LOG
|
| 587 |
|
|
// Initialize the size and pointers
|
| 588 |
|
|
debug_data->printf_output_ptr = (alt_u32)debug_printf_output;
|
| 589 |
|
|
debug_printf_output->data_size = sizeof(debug_printf_output_t);
|
| 590 |
|
|
|
| 591 |
|
|
// Initialize the payload
|
| 592 |
|
|
tclrpt_initialize_printf_output();
|
| 593 |
|
|
#else
|
| 594 |
|
|
debug_data->printf_output_ptr = (alt_u32)0;
|
| 595 |
|
|
#endif
|
| 596 |
|
|
|
| 597 |
|
|
}
|
| 598 |
|
|
}
|
| 599 |
|
|
|
| 600 |
|
|
void tclrpt_initialize_debug_status (void)
|
| 601 |
|
|
{
|
| 602 |
|
|
// Initialize the status bits of the status word.
|
| 603 |
|
|
debug_data->status = 0;
|
| 604 |
|
|
|
| 605 |
|
|
// Initialize the debug status to show that printf log is enabled
|
| 606 |
|
|
#if ENABLE_PRINTF_LOG
|
| 607 |
|
|
debug_data->status |= 1 << DEBUG_STATUS_PRINTF_ENABLED_BIT;
|
| 608 |
|
|
#endif
|
| 609 |
|
|
|
| 610 |
|
|
}
|
| 611 |
|
|
|
| 612 |
|
|
|
| 613 |
|
|
void tclrpt_mark_interface_as_ready(void)
|
| 614 |
|
|
{
|
| 615 |
|
|
// Set the debug data command to TCLDBG_CMD_WAIT_CMD and the status to ready.
|
| 616 |
|
|
// This identifies the interface as being ready to accept commands.
|
| 617 |
|
|
// We must write the command first as there is the potential that
|
| 618 |
|
|
// both the JTAG master and NIOS try writing to the same address
|
| 619 |
|
|
|
| 620 |
|
|
debug_data->requested_command = TCLDBG_CMD_WAIT_CMD;
|
| 621 |
|
|
debug_data->command_status = TCLDBG_TX_STATUS_CMD_READY;
|
| 622 |
|
|
}
|
| 623 |
|
|
|
| 624 |
|
|
void tclrpt_mark_interface_as_response_ready(void)
|
| 625 |
|
|
{
|
| 626 |
|
|
// Mark the interface as saying that the response to the requested
|
| 627 |
|
|
// command is ready.
|
| 628 |
|
|
debug_data->command_status = TCLDBG_TX_STATUS_RESPONSE_READY;
|
| 629 |
|
|
}
|
| 630 |
|
|
|
| 631 |
|
|
void tclrpt_mark_interface_as_illegal_command(void)
|
| 632 |
|
|
{
|
| 633 |
|
|
// Mark the interface as saying that the command or parameter requested was
|
| 634 |
|
|
// illegal
|
| 635 |
|
|
debug_data->command_status = TCLDBG_TX_STATUS_ILLEGAL_CMD;
|
| 636 |
|
|
}
|
| 637 |
|
|
|
| 638 |
|
|
#if !HPS_HW
|
| 639 |
|
|
void tclrpt_loop(void)
|
| 640 |
|
|
{
|
| 641 |
|
|
alt_u32 rank, group, pin, pin_in_group, value;
|
| 642 |
|
|
alt_u32 rdimm_control_word_updated;
|
| 643 |
|
|
rdimm_control_word_updated = 0;
|
| 644 |
|
|
// Set up the interface to be ready for access. The initial state is user mode.
|
| 645 |
|
|
tclrpt_mark_interface_as_ready();
|
| 646 |
|
|
|
| 647 |
|
|
// Forever just respond to commands
|
| 648 |
|
|
for (;;)
|
| 649 |
|
|
{
|
| 650 |
|
|
// This is to check if RDIMM Control Word has been updated
|
| 651 |
|
|
if ( rdimm_control_word_updated == 1 )
|
| 652 |
|
|
{
|
| 653 |
|
|
break;
|
| 654 |
|
|
}
|
| 655 |
|
|
|
| 656 |
|
|
// KALEN: Do we need this in debug?
|
| 657 |
|
|
// AIDIL: Yes since debug is turned on by default, not having this means deep
|
| 658 |
|
|
// powerdown would stall controller
|
| 659 |
|
|
user_init_cal_req();
|
| 660 |
|
|
|
| 661 |
|
|
if (debug_data->command_status == TCLDBG_TX_STATUS_RESPONSE_READY
|
| 662 |
|
|
|| debug_data->command_status == TCLDBG_TX_STATUS_ILLEGAL_CMD)
|
| 663 |
|
|
switch (debug_data->requested_command)
|
| 664 |
|
|
{
|
| 665 |
|
|
case TCLDBG_CMD_RESPONSE_ACK :
|
| 666 |
|
|
// The TCL interface has read the response
|
| 667 |
|
|
// Since the TCL interface has read the response we can mark the interface
|
| 668 |
|
|
// As being ready to accept another command
|
| 669 |
|
|
tclrpt_mark_interface_as_ready();
|
| 670 |
|
|
break;
|
| 671 |
|
|
}
|
| 672 |
|
|
else if (debug_data->command_status == TCLDBG_TX_STATUS_CMD_READY)
|
| 673 |
|
|
{
|
| 674 |
|
|
switch (debug_data->requested_command)
|
| 675 |
|
|
{
|
| 676 |
|
|
case TCLDBG_SET_UPDATE_PARAMETERS :
|
| 677 |
|
|
rdimm_control_word_updated = 1;
|
| 678 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 679 |
|
|
break;
|
| 680 |
|
|
case TCLDBG_CMD_WAIT_CMD :
|
| 681 |
|
|
//wait for commands
|
| 682 |
|
|
break;
|
| 683 |
|
|
case TCLDBG_CMD_NOP : //NOOP command
|
| 684 |
|
|
// Perform no operation
|
| 685 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 686 |
|
|
break;
|
| 687 |
|
|
case TCLDBG_RUN_MEM_CALIBRATE :
|
| 688 |
|
|
// Run the full memory calibration
|
| 689 |
|
|
#if ENABLE_NON_DES_CAL
|
| 690 |
|
|
run_mem_calibrate(0);
|
| 691 |
|
|
#else
|
| 692 |
|
|
run_mem_calibrate();
|
| 693 |
|
|
#endif
|
| 694 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 695 |
|
|
break;
|
| 696 |
|
|
case TCLDBG_RUN_NON_DES_MEM_CALIBRATE :
|
| 697 |
|
|
// Run the full memory calibration
|
| 698 |
|
|
#if ENABLE_NON_DES_CAL
|
| 699 |
|
|
run_mem_calibrate(1);
|
| 700 |
|
|
#else
|
| 701 |
|
|
run_mem_calibrate();
|
| 702 |
|
|
#endif
|
| 703 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 704 |
|
|
break;
|
| 705 |
|
|
|
| 706 |
|
|
case TCLDBG_RUN_EYE_DIAGRAM_PATTERN :
|
| 707 |
|
|
// Generate the pattern to view eye diagrams
|
| 708 |
|
|
// This function never returns
|
| 709 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 710 |
|
|
break;
|
| 711 |
|
|
case TCLDBG_MARK_ALL_DQS_GROUPS_AS_VALID :
|
| 712 |
|
|
// Mark all groups as being valid for calibration
|
| 713 |
|
|
param->skip_groups = 0;
|
| 714 |
|
|
tclrpt_update_rank_group_mask();
|
| 715 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 716 |
|
|
break;
|
| 717 |
|
|
case TCLDBG_MARK_GROUP_AS_SKIP :
|
| 718 |
|
|
// Mark the specified group as being skipped for calibration
|
| 719 |
|
|
|
| 720 |
|
|
// Make sure it is a legal group
|
| 721 |
|
|
if (debug_data->command_parameters[0] < RW_MGR_MEM_IF_WRITE_DQS_WIDTH) {
|
| 722 |
|
|
param->skip_groups |= 1 << debug_data->command_parameters[0];
|
| 723 |
|
|
|
| 724 |
|
|
tclrpt_update_rank_group_mask();
|
| 725 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 726 |
|
|
}
|
| 727 |
|
|
else {
|
| 728 |
|
|
// Illegal payload detected
|
| 729 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 730 |
|
|
}
|
| 731 |
|
|
|
| 732 |
|
|
break;
|
| 733 |
|
|
case TCLDBG_MARK_ALL_RANKS_AS_VALID :
|
| 734 |
|
|
// Mark all ranks as being valid for calibration
|
| 735 |
|
|
for (rank = 0; rank < RW_MGR_MEM_NUMBER_OF_RANKS; rank++)
|
| 736 |
|
|
{
|
| 737 |
|
|
param->skip_ranks[rank] = 0;
|
| 738 |
|
|
}
|
| 739 |
|
|
tclrpt_update_rank_group_mask();
|
| 740 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 741 |
|
|
break;
|
| 742 |
|
|
case TCLDBG_MARK_RANK_AS_SKIP :
|
| 743 |
|
|
// Make sure it is a legal group
|
| 744 |
|
|
if (debug_data->command_parameters[0] < RW_MGR_MEM_NUMBER_OF_RANKS) {
|
| 745 |
|
|
param->skip_ranks[debug_data->command_parameters[0]] = 1;
|
| 746 |
|
|
|
| 747 |
|
|
tclrpt_update_rank_group_mask();
|
| 748 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 749 |
|
|
}
|
| 750 |
|
|
else {
|
| 751 |
|
|
// Illegal payload detected
|
| 752 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 753 |
|
|
}
|
| 754 |
|
|
|
| 755 |
|
|
break;
|
| 756 |
|
|
case TCLDBG_ENABLE_MARGIN_REPORT :
|
| 757 |
|
|
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_MARGIN_RPT;
|
| 758 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 759 |
|
|
break;
|
| 760 |
|
|
case TCLDBG_ENABLE_SWEEP_ALL_GROUPS :
|
| 761 |
|
|
gbl->phy_debug_mode_flags |= PHY_DEBUG_SWEEP_ALL_GROUPS;
|
| 762 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 763 |
|
|
break;
|
| 764 |
|
|
case TCLDBG_DISABLE_GUARANTEED_READ :
|
| 765 |
|
|
gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
|
| 766 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 767 |
|
|
break;
|
| 768 |
|
|
case TCLDBG_SET_NON_DESTRUCTIVE_CALIBRATION:
|
| 769 |
|
|
if (debug_data->command_parameters[0]) {
|
| 770 |
|
|
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION;
|
| 771 |
|
|
} else {
|
| 772 |
|
|
gbl->phy_debug_mode_flags &= ~(PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION);
|
| 773 |
|
|
}
|
| 774 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 775 |
|
|
break;
|
| 776 |
|
|
#if ENABLE_DELAY_CHAIN_WRITE
|
| 777 |
|
|
case TCLDBG_SET_DQ_D1_DELAY :
|
| 778 |
|
|
// DQ D1 Delay (I/O buffer to input register)
|
| 779 |
|
|
pin = debug_data->command_parameters[0];
|
| 780 |
|
|
value = debug_data->command_parameters[1];
|
| 781 |
|
|
group = pin/RW_MGR_MEM_DQ_PER_READ_DQS;
|
| 782 |
|
|
pin_in_group = pin%RW_MGR_MEM_DQ_PER_READ_DQS;
|
| 783 |
|
|
|
| 784 |
|
|
// Make sure parameter values are legal
|
| 785 |
|
|
if (pin < RW_MGR_MEM_DATA_WIDTH && value <= IO_IO_IN_DELAY_MAX) {
|
| 786 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 787 |
|
|
scc_mgr_set_dq_in_delay(group, pin_in_group, value);
|
| 788 |
|
|
scc_mgr_load_dq (pin_in_group);
|
| 789 |
|
|
IOWR_32DIRECT (SCC_MGR_UPD, 0, 0);
|
| 790 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 791 |
|
|
} else {
|
| 792 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 793 |
|
|
}
|
| 794 |
|
|
break;
|
| 795 |
|
|
case TCLDBG_SET_DQ_D5_DELAY :
|
| 796 |
|
|
// DQ D5 Delay (output register to I/O buffer)
|
| 797 |
|
|
pin = debug_data->command_parameters[0];
|
| 798 |
|
|
value = debug_data->command_parameters[1];
|
| 799 |
|
|
group = pin/RW_MGR_MEM_DQ_PER_WRITE_DQS;
|
| 800 |
|
|
pin_in_group = pin%RW_MGR_MEM_DQ_PER_WRITE_DQS;
|
| 801 |
|
|
|
| 802 |
|
|
// Make sure parameter values are legal
|
| 803 |
|
|
if (pin < RW_MGR_MEM_DATA_WIDTH && value <= IO_IO_OUT1_DELAY_MAX) {
|
| 804 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 805 |
|
|
scc_mgr_set_dq_out1_delay(group, pin_in_group, value);
|
| 806 |
|
|
scc_mgr_load_dq (pin_in_group);
|
| 807 |
|
|
IOWR_32DIRECT (SCC_MGR_UPD, 0, 0);
|
| 808 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 809 |
|
|
} else {
|
| 810 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 811 |
|
|
}
|
| 812 |
|
|
break;
|
| 813 |
|
|
case TCLDBG_SET_DQ_D6_DELAY :
|
| 814 |
|
|
// DQ D6 Delay (output register to I/O buffer)
|
| 815 |
|
|
pin = debug_data->command_parameters[0];
|
| 816 |
|
|
value = debug_data->command_parameters[1];
|
| 817 |
|
|
group = pin/RW_MGR_MEM_DQ_PER_WRITE_DQS;
|
| 818 |
|
|
pin_in_group = pin%RW_MGR_MEM_DQ_PER_WRITE_DQS;
|
| 819 |
|
|
|
| 820 |
|
|
// Make sure parameter values are legal
|
| 821 |
|
|
if (pin < RW_MGR_MEM_DATA_WIDTH && value <= IO_IO_OUT2_DELAY_MAX) {
|
| 822 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 823 |
|
|
scc_mgr_set_dq_out2_delay(group, pin_in_group, value);
|
| 824 |
|
|
scc_mgr_load_dq (pin_in_group);
|
| 825 |
|
|
IOWR_32DIRECT (SCC_MGR_UPD, 0, 0);
|
| 826 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 827 |
|
|
} else {
|
| 828 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 829 |
|
|
}
|
| 830 |
|
|
break;
|
| 831 |
|
|
case TCLDBG_SET_DQS_D4_DELAY :
|
| 832 |
|
|
// DQS D4 Delay (DQS delay chain)
|
| 833 |
|
|
group = debug_data->command_parameters[0];
|
| 834 |
|
|
value = debug_data->command_parameters[1];
|
| 835 |
|
|
|
| 836 |
|
|
// Make sure parameter values are legal
|
| 837 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH && value <= IO_DQS_IN_DELAY_MAX) {
|
| 838 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 839 |
|
|
scc_mgr_set_dqs_bus_in_delay(group, value);
|
| 840 |
|
|
scc_mgr_load_dqs (group);
|
| 841 |
|
|
IOWR_32DIRECT (SCC_MGR_UPD, 0, 0);
|
| 842 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 843 |
|
|
} else {
|
| 844 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 845 |
|
|
}
|
| 846 |
|
|
break;
|
| 847 |
|
|
case TCLDBG_SET_DQDQS_OUTPUT_PHASE :
|
| 848 |
|
|
// DQS DQ Output Phase (deg) = DQS Output Phase (deg) - 90
|
| 849 |
|
|
group = debug_data->command_parameters[0];
|
| 850 |
|
|
value = debug_data->command_parameters[1];
|
| 851 |
|
|
|
| 852 |
|
|
// Make sure parameter values are legal
|
| 853 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH && value <= IO_DQDQS_OUT_PHASE_MAX) {
|
| 854 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 855 |
|
|
scc_mgr_set_dqdqs_output_phase_all_ranks (group, value);
|
| 856 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 857 |
|
|
} else {
|
| 858 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 859 |
|
|
}
|
| 860 |
|
|
break;
|
| 861 |
|
|
case TCLDBG_SET_DQS_D5_DELAY :
|
| 862 |
|
|
// DQS D5 Delay (output register to I/O buffer) = D5 OCT Delay (OCT to I/O buffer)
|
| 863 |
|
|
group = debug_data->command_parameters[0];
|
| 864 |
|
|
value = debug_data->command_parameters[1];
|
| 865 |
|
|
|
| 866 |
|
|
// Make sure parameter values are legal
|
| 867 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH && value <= IO_IO_OUT1_DELAY_MAX) {
|
| 868 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 869 |
|
|
scc_mgr_set_group_dqs_io_and_oct_out1_gradual (group, value);
|
| 870 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 871 |
|
|
} else {
|
| 872 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 873 |
|
|
}
|
| 874 |
|
|
break;
|
| 875 |
|
|
case TCLDBG_SET_DQS_D6_DELAY :
|
| 876 |
|
|
// DQS D6 Delay (output register to I/O buffer) = D6 OCT Delay (OCT to I/O buffer)
|
| 877 |
|
|
group = debug_data->command_parameters[0];
|
| 878 |
|
|
value = debug_data->command_parameters[1];
|
| 879 |
|
|
|
| 880 |
|
|
// Make sure parameter values are legal
|
| 881 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH && value <= IO_IO_OUT2_DELAY_MAX) {
|
| 882 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 883 |
|
|
scc_mgr_set_group_dqs_io_and_oct_out2_gradual (group, value);
|
| 884 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 885 |
|
|
} else {
|
| 886 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 887 |
|
|
}
|
| 888 |
|
|
break;
|
| 889 |
|
|
case TCLDBG_SET_DQS_EN_PHASE :
|
| 890 |
|
|
// DQS Enable Phase (deg)
|
| 891 |
|
|
group = debug_data->command_parameters[0];
|
| 892 |
|
|
value = debug_data->command_parameters[1];
|
| 893 |
|
|
|
| 894 |
|
|
// Make sure parameter values are legal
|
| 895 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH && value <= IO_DQS_EN_PHASE_MAX) {
|
| 896 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 897 |
|
|
scc_mgr_set_dqs_en_phase_all_ranks (group, value);
|
| 898 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 899 |
|
|
} else {
|
| 900 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 901 |
|
|
}
|
| 902 |
|
|
break;
|
| 903 |
|
|
case TCLDBG_SET_DQS_T11_DELAY :
|
| 904 |
|
|
// DQS T11 Delay (DQS post-amble delay)
|
| 905 |
|
|
group = debug_data->command_parameters[0];
|
| 906 |
|
|
value = debug_data->command_parameters[1];
|
| 907 |
|
|
|
| 908 |
|
|
// Make sure parameter values are legal
|
| 909 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH && value <= IO_DQS_EN_DELAY_MAX) {
|
| 910 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 911 |
|
|
scc_mgr_set_dqs_en_delay_all_ranks (group, value);
|
| 912 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 913 |
|
|
} else {
|
| 914 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 915 |
|
|
}
|
| 916 |
|
|
break;
|
| 917 |
|
|
case TCLDBG_SET_DM_D5_DELAY :
|
| 918 |
|
|
// DM D5 OCT Delay (OCT to I/O buffer)
|
| 919 |
|
|
group = debug_data->command_parameters[0];
|
| 920 |
|
|
pin_in_group = debug_data->command_parameters[1];
|
| 921 |
|
|
value = debug_data->command_parameters[2];
|
| 922 |
|
|
|
| 923 |
|
|
// Make sure parameter values are legal
|
| 924 |
|
|
if (group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH && pin_in_group < RW_MGR_NUM_DM_PER_WRITE_GROUP && value <= IO_IO_OUT1_DELAY_MAX) {
|
| 925 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 926 |
|
|
scc_mgr_set_dm_out1_delay(group, pin_in_group, value);
|
| 927 |
|
|
scc_mgr_load_dm (pin_in_group);
|
| 928 |
|
|
IOWR_32DIRECT (SCC_MGR_UPD, 0, 0);
|
| 929 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 930 |
|
|
} else {
|
| 931 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 932 |
|
|
}
|
| 933 |
|
|
break;
|
| 934 |
|
|
case TCLDBG_SET_DM_D6_DELAY :
|
| 935 |
|
|
// DM D6 OCT Delay (OCT to I/O buffer)
|
| 936 |
|
|
group = debug_data->command_parameters[0];
|
| 937 |
|
|
pin_in_group = debug_data->command_parameters[1];
|
| 938 |
|
|
value = debug_data->command_parameters[2];
|
| 939 |
|
|
|
| 940 |
|
|
// Make sure parameter values are legal
|
| 941 |
|
|
if (group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH && pin_in_group < RW_MGR_NUM_DM_PER_WRITE_GROUP && value <= IO_IO_OUT2_DELAY_MAX) {
|
| 942 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 943 |
|
|
scc_mgr_set_dm_out2_delay(group, pin_in_group, value);
|
| 944 |
|
|
scc_mgr_load_dm (pin_in_group);
|
| 945 |
|
|
IOWR_32DIRECT (SCC_MGR_UPD, 0, 0);
|
| 946 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 947 |
|
|
} else {
|
| 948 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 949 |
|
|
}
|
| 950 |
|
|
break;
|
| 951 |
|
|
case TCLDBG_REMARGIN_DQ :
|
| 952 |
|
|
rank = debug_data->command_parameters[0];
|
| 953 |
|
|
group = debug_data->command_parameters[1];
|
| 954 |
|
|
// Pre-margining process
|
| 955 |
|
|
initialize();
|
| 956 |
|
|
rw_mgr_mem_initialize ();
|
| 957 |
|
|
mem_config ();
|
| 958 |
|
|
|
| 959 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 960 |
|
|
run_dq_margining(rank, group);
|
| 961 |
|
|
|
| 962 |
|
|
// Post-margining process
|
| 963 |
|
|
rw_mgr_mem_handoff ();
|
| 964 |
|
|
IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0); // Give control back to user logic.
|
| 965 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 966 |
|
|
break;
|
| 967 |
|
|
case TCLDBG_REMARGIN_DM :
|
| 968 |
|
|
rank = debug_data->command_parameters[0];
|
| 969 |
|
|
group = debug_data->command_parameters[1];
|
| 970 |
|
|
// Pre-margining process
|
| 971 |
|
|
initialize();
|
| 972 |
|
|
rw_mgr_mem_initialize ();
|
| 973 |
|
|
mem_config ();
|
| 974 |
|
|
|
| 975 |
|
|
IOWR_32DIRECT (SCC_MGR_GROUP_COUNTER, 0, group);
|
| 976 |
|
|
run_dm_margining(rank, group);
|
| 977 |
|
|
|
| 978 |
|
|
// Post-margining process
|
| 979 |
|
|
rw_mgr_mem_handoff ();
|
| 980 |
|
|
IOWR_32DIRECT (PHY_MGR_MUX_SEL, 0, 0); // Give control back to user logic.
|
| 981 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 982 |
|
|
break;
|
| 983 |
|
|
case TCLDBG_INCR_VFIFO :
|
| 984 |
|
|
// Increment the VFIFO by 1 step
|
| 985 |
|
|
group = debug_data->command_parameters[0];
|
| 986 |
|
|
|
| 987 |
|
|
// Make sure parameter values are legal
|
| 988 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH) {
|
| 989 |
|
|
rw_mgr_incr_vfifo_auto(group);
|
| 990 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 991 |
|
|
} else {
|
| 992 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 993 |
|
|
}
|
| 994 |
|
|
break;
|
| 995 |
|
|
case TCLDBG_DECR_VFIFO :
|
| 996 |
|
|
// Decrement the VFIFO by 1 step
|
| 997 |
|
|
group = debug_data->command_parameters[0];
|
| 998 |
|
|
|
| 999 |
|
|
// Make sure parameter values are legal
|
| 1000 |
|
|
if (group < RW_MGR_MEM_IF_READ_DQS_WIDTH) {
|
| 1001 |
|
|
rw_mgr_decr_vfifo_auto(group);
|
| 1002 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 1003 |
|
|
} else {
|
| 1004 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 1005 |
|
|
}
|
| 1006 |
|
|
break;
|
| 1007 |
|
|
case TCLDBG_SELECT_SHADOW_REG :
|
| 1008 |
|
|
rank = debug_data->command_parameters[0];
|
| 1009 |
|
|
if (rank < RW_MGR_MEM_NUMBER_OF_RANKS) {
|
| 1010 |
|
|
select_shadow_regs_for_update (rank, 0, 1);
|
| 1011 |
|
|
tclrpt_mark_interface_as_response_ready();
|
| 1012 |
|
|
} else {
|
| 1013 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 1014 |
|
|
}
|
| 1015 |
|
|
break;
|
| 1016 |
|
|
#endif // ENABLE_DELAY_CHAIN_WRITE
|
| 1017 |
|
|
default :
|
| 1018 |
|
|
// Illegal command
|
| 1019 |
|
|
tclrpt_mark_interface_as_illegal_command();
|
| 1020 |
|
|
break;
|
| 1021 |
|
|
}
|
| 1022 |
|
|
}
|
| 1023 |
|
|
}
|
| 1024 |
|
|
}
|
| 1025 |
|
|
#endif
|
| 1026 |
|
|
|
| 1027 |
|
|
#if BFM_MODE
|
| 1028 |
|
|
const char* const EMITT_XML_CSTR_CONNECTIONS = "connections";
|
| 1029 |
|
|
const char* const EMITT_XML_CSTR_CONNECTION = "connection";
|
| 1030 |
|
|
const char* const EMITT_XML_CSTR_CONNECTION_DATA = "connection_data";
|
| 1031 |
|
|
const char* const EMITT_XML_CSTR_HARDWARE_NAME = "hardware_name";
|
| 1032 |
|
|
const char* const EMITT_XML_CSTR_DEVICE_NAME = "device_name";
|
| 1033 |
|
|
const char* const EMITT_XML_CSTR_CONNECTION_PATH = "connection_path";
|
| 1034 |
|
|
const char* const EMITT_XML_CSTR_CONNECTION_PATH_BASE = "connection_path_base";
|
| 1035 |
|
|
const char* const EMITT_XML_CSTR_HIERARCHY_PATH = "hierarchy_path";
|
| 1036 |
|
|
const char* const EMITT_XML_CSTR_CONNECTION_TYPE = "connection_type";
|
| 1037 |
|
|
const char* const EMITT_XML_CSTR_SLD_TYPE = "sld_type";
|
| 1038 |
|
|
const char* const EMITT_XML_CSTR_EMULATION_DATA = "emulation_data";
|
| 1039 |
|
|
const char* const EMITT_XML_CSTR_EMU_DATA = "emu_data";
|
| 1040 |
|
|
const char* const EMITT_XML_CSTR_EMU_ADDRESS = "address";
|
| 1041 |
|
|
|
| 1042 |
|
|
void tclrpt_dump_internal_data(void)
|
| 1043 |
|
|
{
|
| 1044 |
|
|
alt_u32* base_data;
|
| 1045 |
|
|
FILE *fh;
|
| 1046 |
|
|
int i;
|
| 1047 |
|
|
|
| 1048 |
|
|
// Mark the interface as ready to receive transactions. This is
|
| 1049 |
|
|
// equivalent to what tclrpt_loop() does
|
| 1050 |
|
|
tclrpt_mark_interface_as_ready();
|
| 1051 |
|
|
|
| 1052 |
|
|
fh = fopen("emitt_debug_data.xml", "w");
|
| 1053 |
|
|
|
| 1054 |
|
|
|
| 1055 |
|
|
fprintf(fh, "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n");
|
| 1056 |
|
|
fprintf(fh, "<%s>\n", EMITT_XML_CSTR_CONNECTIONS);
|
| 1057 |
|
|
fprintf(fh, "\t<%s>\n", EMITT_XML_CSTR_CONNECTION);
|
| 1058 |
|
|
fprintf(fh, "\t\t<%s>\n", EMITT_XML_CSTR_CONNECTION_DATA);
|
| 1059 |
|
|
fprintf(fh, "\t\t\t<%s>fake_hardware</%s>\n", EMITT_XML_CSTR_HARDWARE_NAME, EMITT_XML_CSTR_HARDWARE_NAME);
|
| 1060 |
|
|
fprintf(fh, "\t\t\t<%s>fake_device@1</%s>\n", EMITT_XML_CSTR_DEVICE_NAME, EMITT_XML_CSTR_DEVICE_NAME);
|
| 1061 |
|
|
fprintf(fh, "\t\t\t<%s>some_device_connection_path</%s>\n", EMITT_XML_CSTR_CONNECTION_PATH, EMITT_XML_CSTR_CONNECTION_PATH);
|
| 1062 |
|
|
fprintf(fh, "\t\t\t<%s>some_device_connection_path</%s>\n", EMITT_XML_CSTR_CONNECTION_PATH_BASE, EMITT_XML_CSTR_CONNECTION_PATH_BASE);
|
| 1063 |
|
|
fprintf(fh, "\t\t\t<%s></%s>\n", EMITT_XML_CSTR_HIERARCHY_PATH, EMITT_XML_CSTR_HIERARCHY_PATH);
|
| 1064 |
|
|
fprintf(fh, "\t\t\t<%s>EMITT_CONNECTION_TYPE_ENUM::UNKNOWN</%s>\n", EMITT_XML_CSTR_CONNECTION_TYPE, EMITT_XML_CSTR_CONNECTION_TYPE);
|
| 1065 |
|
|
fprintf(fh, "\t\t\t<%s>EMITT_CONNECTION_SLD_TYPE_ENUM::DEVICE</%s>\n", EMITT_XML_CSTR_SLD_TYPE, EMITT_XML_CSTR_SLD_TYPE);
|
| 1066 |
|
|
fprintf(fh, "\t\t</%s>\n", EMITT_XML_CSTR_CONNECTION_DATA);
|
| 1067 |
|
|
fprintf(fh, "\t</%s>\n", EMITT_XML_CSTR_CONNECTION);
|
| 1068 |
|
|
fprintf(fh, "\t<%s>\n", EMITT_XML_CSTR_CONNECTION);
|
| 1069 |
|
|
fprintf(fh, "\t\t<%s>\n", EMITT_XML_CSTR_CONNECTION_DATA);
|
| 1070 |
|
|
fprintf(fh, "\t\t\t<%s>fake_hardware</%s>\n", EMITT_XML_CSTR_HARDWARE_NAME, EMITT_XML_CSTR_HARDWARE_NAME);
|
| 1071 |
|
|
fprintf(fh, "\t\t\t<%s>fake_device@1</%s>\n", EMITT_XML_CSTR_DEVICE_NAME, EMITT_XML_CSTR_DEVICE_NAME);
|
| 1072 |
|
|
fprintf(fh, "\t\t\t<%s>some_connection_path</%s>\n", EMITT_XML_CSTR_CONNECTION_PATH, EMITT_XML_CSTR_CONNECTION_PATH);
|
| 1073 |
|
|
fprintf(fh, "\t\t\t<%s>some_connection_path</%s>\n", EMITT_XML_CSTR_CONNECTION_PATH_BASE, EMITT_XML_CSTR_CONNECTION_PATH_BASE);
|
| 1074 |
|
|
fprintf(fh, "\t\t\t<%s>dut:uniphy_inst|dut_if0:if0|dut_if0_dmaster:dmaster</%s>\n", EMITT_XML_CSTR_HIERARCHY_PATH, EMITT_XML_CSTR_HIERARCHY_PATH);
|
| 1075 |
|
|
fprintf(fh, "\t\t\t<%s>EMITT_CONNECTION_TYPE_ENUM::EMIF_120</%s>\n", EMITT_XML_CSTR_CONNECTION_TYPE, EMITT_XML_CSTR_CONNECTION_TYPE);
|
| 1076 |
|
|
fprintf(fh, "\t\t\t<%s>EMITT_CONNECTION_SLD_TYPE_ENUM::MASTER</%s>\n", EMITT_XML_CSTR_SLD_TYPE, EMITT_XML_CSTR_SLD_TYPE);
|
| 1077 |
|
|
fprintf(fh, "\t\t</%s>\n", EMITT_XML_CSTR_CONNECTION_DATA);
|
| 1078 |
|
|
|
| 1079 |
|
|
fprintf(fh, "\t\t<%s>\n", EMITT_XML_CSTR_EMULATION_DATA);
|
| 1080 |
|
|
|
| 1081 |
|
|
for(i = 0; i < 10; i++)
|
| 1082 |
|
|
{
|
| 1083 |
|
|
fprintf(fh, "\t\t\t<%s %s = \"0x%lx\">0x%lx</%s>\n", EMITT_XML_CSTR_EMU_DATA, EMITT_XML_CSTR_EMU_ADDRESS, BASE_REG_FILE + i*4, IORD_32DIRECT(BASE_REG_FILE, i*4), EMITT_XML_CSTR_EMU_DATA);
|
| 1084 |
|
|
}
|
| 1085 |
|
|
|
| 1086 |
|
|
|
| 1087 |
|
|
base_data = (alt_u32*)debug_data;
|
| 1088 |
|
|
for(i = 0; i < debug_data->data_size/4; i++)
|
| 1089 |
|
|
{
|
| 1090 |
|
|
fprintf(fh, "\t\t\t<%s %s = \"0x%lx\">0x%lx</%s>\n", EMITT_XML_CSTR_EMU_DATA, EMITT_XML_CSTR_EMU_ADDRESS, &base_data[i], base_data[i], EMITT_XML_CSTR_EMU_DATA);
|
| 1091 |
|
|
}
|
| 1092 |
|
|
|
| 1093 |
|
|
fprintf(fh, "\t\t</%s>\n", EMITT_XML_CSTR_EMULATION_DATA);
|
| 1094 |
|
|
|
| 1095 |
|
|
fprintf(fh, "\t</%s>\n", EMITT_XML_CSTR_CONNECTION);
|
| 1096 |
|
|
fprintf(fh, "</%s>\n", EMITT_XML_CSTR_CONNECTIONS);
|
| 1097 |
|
|
fclose(fh);
|
| 1098 |
|
|
|
| 1099 |
|
|
}
|
| 1100 |
|
|
|
| 1101 |
|
|
void tclrpt_populate_fake_margin_data(void)
|
| 1102 |
|
|
{
|
| 1103 |
|
|
alt_u32 write_group, dq, dm, sr;
|
| 1104 |
|
|
|
| 1105 |
|
|
|
| 1106 |
|
|
for (sr = 0; sr < NUM_SHADOW_REGS; sr++) {
|
| 1107 |
|
|
for (write_group = 0; write_group < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++)
|
| 1108 |
|
|
{
|
| 1109 |
|
|
for (dm = 0; dm < RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP; dm++)
|
| 1110 |
|
|
{
|
| 1111 |
|
|
TCLRPT_SET(debug_margin_report->margin_dm_margins[sr][write_group][dm].max_working_setting, debug_cal_report->cal_dm_margins[sr][write_group][dm].left_edge);
|
| 1112 |
|
|
TCLRPT_SET(debug_margin_report->margin_dm_margins[sr][write_group][dm].min_working_setting, debug_cal_report->cal_dm_margins[sr][write_group][dm].right_edge);
|
| 1113 |
|
|
}
|
| 1114 |
|
|
}
|
| 1115 |
|
|
for (dq = 0; dq < RW_MGR_MEM_DATA_WIDTH; dq++)
|
| 1116 |
|
|
{
|
| 1117 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_in_margins[sr][dq].max_working_setting, debug_cal_report->cal_dq_in_margins[sr][dq].left_edge);
|
| 1118 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_in_margins[sr][dq].min_working_setting, debug_cal_report->cal_dq_in_margins[sr][dq].right_edge);
|
| 1119 |
|
|
}
|
| 1120 |
|
|
for (dq = 0; dq < RW_MGR_MEM_DATA_WIDTH; dq++)
|
| 1121 |
|
|
{
|
| 1122 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_out_margins[sr][dq].max_working_setting, debug_cal_report->cal_dq_out_margins[sr][dq].left_edge);
|
| 1123 |
|
|
TCLRPT_SET(debug_margin_report->margin_dq_out_margins[sr][dq].min_working_setting, debug_cal_report->cal_dq_out_margins[sr][dq].right_edge);
|
| 1124 |
|
|
}
|
| 1125 |
|
|
}
|
| 1126 |
|
|
}
|
| 1127 |
|
|
#endif
|
| 1128 |
|
|
|
| 1129 |
|
|
|
| 1130 |
|
|
#endif // ENABLE_TCL_DEBUG
|
