URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.cdf] - Blame information for rev 32

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/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition */
JedecChain;
        FileRevision(JESD32A);
        DefaultMfr(6E);
 
        P ActionCode(Ign)
                Device PartName(SOCVHPS) MfrSpec(OpMask(0));
        P ActionCode(Cfg)
                Device PartName(5CSEMA4U23) Path("/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/output_files/") File("spw_fifo_ulight.sof") MfrSpec(OpMask(1));
 
ChainEnd;
 
AlteraBegin;
        ChainType(JTAG);
AlteraEnd;

Line No.	Rev	Author	Line
1	32	redbear	`/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition */`
2			`JedecChain;`
3			`FileRevision(JESD32A);`
4			`DefaultMfr(6E);`
5
6			`P ActionCode(Ign)`
7			`Device PartName(SOCVHPS) MfrSpec(OpMask(0));`
8			`P ActionCode(Cfg)`
9			`Device PartName(5CSEMA4U23) Path("/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/output_files/") File("spw_fifo_ulight.sof") MfrSpec(OpMask(1));`
10
11			`ChainEnd;`
12
13			`AlteraBegin;`
14			`ChainType(JTAG);`
15			`AlteraEnd;`

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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.cdf] - Blame information for rev 32