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EDA Netlist Writer report for spw_fifo_ulight
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Mon Feb 5 00:59:12 2018
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Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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---------------------
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; Table of Contents ;
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1. Legal Notice
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2. EDA Netlist Writer Summary
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3. Board-Level Settings
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4. Board-Level Generated Files
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5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+-------------------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Mon Feb 5 00:59:12 2018 ;
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; Revision Name ; spw_fifo_ulight ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Family ; Cyclone V ;
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; Board Signal Integrity Files Creation ; Successful ;
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; Board Timing Analysis Files Creation ; Successful ;
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+---------------------------------------+---------------------------------------+
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+-----------------------------------------+
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; Board-Level Settings ;
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+-------------------------------+---------+
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; Option ; Setting ;
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+-------------------------------+---------+
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; Board Signal Integrity Format ; HSPICE ;
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; Board Timing Analysis Format ; STAMP ;
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+-------------------------------+---------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Board-Level Generated Files ;
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Generated Files ;
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Board Signal Integrity ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc ;
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; Board Timing Analysis ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod ;
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; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data ;
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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Info: Processing started: Mon Feb 5 00:59:06 2018
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data"
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Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data"
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Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data"
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Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data"
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Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data"
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Info (199053): Generated 36 HSPICE Output files for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp for board level analysis
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Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp for board level analysis
|
| 142 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp for board level analysis
|
| 143 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp for board level analysis
|
| 144 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib for board level analysis
|
| 145 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib for board level analysis
|
| 146 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib for board level analysis
|
| 147 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib for board level analysis
|
| 148 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib for board level analysis
|
| 149 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib for board level analysis
|
| 150 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc for board level analysis
|
| 151 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc for board level analysis
|
| 152 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc for board level analysis
|
| 153 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc for board level analysis
|
| 154 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc for board level analysis
|
| 155 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc for board level analysis
|
| 156 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib for board level analysis
|
| 157 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc for board level analysis
|
| 158 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib for board level analysis
|
| 159 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc for board level analysis
|
| 160 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc for board level analysis
|
| 161 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib for board level analysis
|
| 162 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc for board level analysis
|
| 163 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc for board level analysis
|
| 164 |
|
|
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc for board level analysis
|
| 165 |
|
|
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
| 166 |
|
|
Info: Peak virtual memory: 1244 megabytes
|
| 167 |
|
|
Info: Processing ended: Mon Feb 5 00:59:13 2018
|
| 168 |
|
|
Info: Elapsed time: 00:00:07
|
| 169 |
|
|
Info: Total CPU time (on all processors): 00:00:06
|
| 170 |
32 |
redbear |
|
| 171 |
|
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