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Fitter report for spw_fifo_ulight
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Mon Feb 5 00:57:17 2018
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Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Fitter Summary
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3. Fitter Settings
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4. Parallel Compilation
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5. Fitter Netlist Optimizations
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6. Ignored Assignments
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7. Incremental Compilation Preservation Summary
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8. Incremental Compilation Partition Settings
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9. Incremental Compilation Placement Preservation
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10. Pin-Out File
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11. Fitter Resource Usage Summary
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12. Fitter Partition Statistics
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13. Input Pins
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14. Output Pins
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15. I/O Bank Usage
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16. All Package Pins
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17. I/O Assignment Warnings
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18. PLL Usage Summary
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19. Fitter Resource Utilization by Entity
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20. Delay Chain Summary
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21. Pad To Core Delay Chain Fanout
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22. Control Signals
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23. Global & Other Fast Signals
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24. Non-Global High Fan-Out Signals
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25. Routing Usage Summary
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26. I/O Rules Summary
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27. I/O Rules Details
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28. I/O Rules Matrix
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29. Fitter Device Options
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30. Operating Settings and Conditions
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31. Estimated Delay Added for Hold Timing Summary
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32. Estimated Delay Added for Hold Timing Details
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33. Fitter Messages
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34. Fitter Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+----------------------------------------------------------------------------------------+
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; Fitter Summary ;
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+---------------------------------+------------------------------------------------------+
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; Fitter Status ; Successful - Mon Feb 5 00:57:17 2018 ;
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; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;
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; Revision Name ; spw_fifo_ulight ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Family ; Cyclone V ;
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; Device ; 5CSEMA4U23C6 ;
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; Timing Models ; Final ;
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; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ;
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; Total registers ; 4633 ;
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; Total pins ; 19 / 314 ( 6 % ) ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
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; Total RAM Blocks ; 0 / 270 ( 0 % ) ;
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; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
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; Total HSSI RX PCSs ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total PLLs ; 1 / 5 ( 20 % ) ;
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; Total DLLs ; 0 / 4 ( 0 % ) ;
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+---------------------------------+------------------------------------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Fitter Settings ;
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+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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; Option ; Setting ; Default Value ;
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+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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; Device ; 5CSEMA4U23C6 ; ;
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; Minimum Core Junction Temperature ; 0 ; ;
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; Maximum Core Junction Temperature ; 85 ; ;
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; Router Timing Optimization Level ; MAXIMUM ; Normal ;
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; Placement Effort Multiplier ; 4.0 ; 1.0 ;
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; Auto RAM to MLAB Conversion ; Off ; On ;
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; Power Optimization During Fitting ; Extra effort ; Normal compilation ;
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; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;
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; Auto Delay Chains for High Fanout Input Pins ; On ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ;
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; Perform Asynchronous Signal Pipelining ; On ; Off ;
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; Physical Synthesis Effort Level ; Extra ; Normal ;
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; Logic Cell Insertion - Logic Duplication ; Off ; Auto ;
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; Auto Register Duplication ; Off ; Auto ;
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; Optimize Design for Metastability ; Off ; On ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
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; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
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; Optimize Hold Timing ; All Paths ; All Paths ;
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; Optimize Multi-Corner Timing ; On ; On ;
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; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
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; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
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; SSN Optimization ; Off ; Off ;
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; Optimize Timing ; Normal compilation ; Normal compilation ;
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; Optimize Timing for ECOs ; Off ; Off ;
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; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
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; Final Placement Optimizations ; Automatically ; Automatically ;
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; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
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; Fitter Initial Placement Seed ; 1 ; 1 ;
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; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
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; Weak Pull-Up Resistor ; Off ; Off ;
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; Enable Bus-Hold Circuitry ; Off ; Off ;
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; Auto Packed Registers ; Auto ; Auto ;
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; Auto Delay Chains ; On ; On ;
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; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
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; Perform Register Duplication for Performance ; Off ; Off ;
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; Perform Register Retiming for Performance ; Off ; Off ;
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; Fitter Effort ; Auto Fit ; Auto Fit ;
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; Auto Global Clock ; On ; On ;
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; Auto Global Register Control Signals ; On ; On ;
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; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
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; Synchronizer Identification ; Auto ; Auto ;
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; Enable Beneficial Skew Optimization ; On ; On ;
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; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
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; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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; Clamping Diode ; Off ; Off ;
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; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
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; Advanced Physical Optimization ; On ; On ;
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+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 2 ;
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; ; ;
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; Average used ; 1.09 ;
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; Maximum used ; 2 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 9.1% ;
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+----------------------------+-------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Fitter Netlist Optimizations ;
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+
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; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+
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; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~41 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add1~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1_RESYN160_BDD161 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_RESYN126_BDD127 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_RESYN148_BDD149 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_RESYN150_BDD151 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_RESYN152_BDD153 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 192 |
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN138_BDD139 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN140_BDD141 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~53 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~56 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~66 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 202 |
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97_RESYN164_BDD165 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98_RESYN166_BDD167 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~99 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100_RESYN168_BDD169 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; debounce_db:db_system_spwulight_b|Add0~62 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; debounce_db:db_system_spwulight_b|counter~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 211 |
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; detector_tokens:m_x|always5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|always5~1_RESYN162_BDD163 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|always5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 215 |
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 216 |
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 218 |
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1_RESYN170_BDD171 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 219 |
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add5~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 221 |
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add7~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Selector18~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 224 |
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|rd_ptr~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add1~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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| 227 |
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add2~26 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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|
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 231 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 232 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 233 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 234 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 235 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 236 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 237 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 238 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 239 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 240 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6_RESYN58_BDD59 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 241 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 242 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7_RESYN60_BDD61 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 243 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 244 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8_RESYN62_BDD63 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 245 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 246 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9_RESYN64_BDD65 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 247 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 248 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10_RESYN66_BDD67 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 249 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 250 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11_RESYN68_BDD69 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 251 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 252 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12_RESYN70_BDD71 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 253 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 254 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|always2~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 255 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 256 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13_RESYN72_BDD73 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 257 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 258 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 259 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 260 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 261 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1_RESYN104_BDD105 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 262 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 263 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 264 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1_RESYN154_BDD155 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 265 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 266 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1_RESYN156_BDD157 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 267 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 268 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0_RESYN158_BDD159 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 269 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Equal4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 270 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 271 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1_RESYN128_BDD129 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 272 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ShiftRight1~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 273 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 274 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4_RESYN146_BDD147 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 275 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 276 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 277 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 278 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~14 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 279 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~15 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 280 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 281 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 282 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 283 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~7 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 284 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~8 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 285 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 286 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 287 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 288 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 289 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18_RESYN130_BDD131 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 290 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 291 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 292 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 293 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN132_BDD133 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 294 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN134_BDD135 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 295 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 296 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25_RESYN136_BDD137 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 297 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~28 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 298 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 299 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 300 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 301 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 302 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1_RESYN120_BDD121 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 303 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 304 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3_RESYN122_BDD123 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 305 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 306 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4_RESYN124_BDD125 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 307 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 308 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1_RESYN142_BDD143 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 309 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 310 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0_RESYN144_BDD145 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 311 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 312 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3_RESYN76_BDD77 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 313 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 314 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5_RESYN78_BDD79 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 315 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 316 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10_RESYN80_BDD81 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 317 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.000~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 318 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 319 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9_RESYN98_BDD99 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 320 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 321 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10_RESYN100_BDD101 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 322 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 323 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 324 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN108_BDD109 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 325 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN110_BDD111 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 326 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 327 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13_RESYN112_BDD113 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 328 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 329 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14_RESYN114_BDD115 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 330 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 331 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 332 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 333 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 334 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 335 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 336 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 337 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 338 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 339 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 340 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3_RESYN84_BDD85 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 341 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 342 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 343 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 344 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 345 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 346 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 347 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
| 348 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0]~_Duplicate_1 ; Q ; ;
|
| 349 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[0]~output ; I ; ;
|
| 350 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1]~_Duplicate_1 ; Q ; ;
|
| 351 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[1]~output ; I ; ;
|
| 352 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2]~_Duplicate_1 ; Q ; ;
|
| 353 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[2]~output ; I ; ;
|
| 354 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3]~_Duplicate_1 ; Q ; ;
|
| 355 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[3]~output ; I ; ;
|
| 356 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4]~_Duplicate_1 ; Q ; ;
|
| 357 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[4]~output ; I ; ;
|
| 358 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+
|
| 359 |
32 |
redbear |
|
| 360 |
|
|
|
| 361 |
|
|
+---------------------------------------------------------------------------------------------+
|
| 362 |
|
|
; Ignored Assignments ;
|
| 363 |
|
|
+--------------+-----------------+--------------+------------+---------------+----------------+
|
| 364 |
|
|
; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
|
| 365 |
|
|
+--------------+-----------------+--------------+------------+---------------+----------------+
|
| 366 |
|
|
; I/O Standard ; SPW_ULIGHT_FIFO ; ; KEY ; 3.3-V LVTTL ; QSF Assignment ;
|
| 367 |
|
|
; I/O Standard ; SPW_ULIGHT_FIFO ; ; LED ; 3.3-V LVTTL ; QSF Assignment ;
|
| 368 |
|
|
+--------------+-----------------+--------------+------------+---------------+----------------+
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
40 |
redbear |
+----------------------------------------------------------------------------------------------------+
|
| 372 |
|
|
; Incremental Compilation Preservation Summary ;
|
| 373 |
|
|
+---------------------+----------------------+----------------------------+--------------------------+
|
| 374 |
|
|
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
| 375 |
|
|
+---------------------+----------------------+----------------------------+--------------------------+
|
| 376 |
|
|
; Placement (by node) ; ; ; ;
|
| 377 |
|
|
; -- Requested ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;
|
| 378 |
|
|
; -- Achieved ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;
|
| 379 |
|
|
; ; ; ; ;
|
| 380 |
|
|
; Routing (by net) ; ; ; ;
|
| 381 |
|
|
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
| 382 |
|
|
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
| 383 |
|
|
+---------------------+----------------------+----------------------------+--------------------------+
|
| 384 |
32 |
redbear |
|
| 385 |
|
|
|
| 386 |
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 387 |
|
|
; Incremental Compilation Partition Settings ;
|
| 388 |
|
|
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
| 389 |
|
|
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
|
| 390 |
|
|
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
| 391 |
|
|
; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
|
| 392 |
|
|
; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
|
| 393 |
|
|
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
| 394 |
|
|
|
| 395 |
|
|
|
| 396 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------+
|
| 397 |
|
|
; Incremental Compilation Placement Preservation ;
|
| 398 |
|
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
| 399 |
|
|
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
| 400 |
|
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
| 401 |
40 |
redbear |
; Top ; 0.00 % ( 0 / 10065 ) ; N/A ; Source File ; N/A ; ;
|
| 402 |
32 |
redbear |
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ;
|
| 403 |
|
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
| 404 |
|
|
|
| 405 |
|
|
|
| 406 |
|
|
+--------------+
|
| 407 |
|
|
; Pin-Out File ;
|
| 408 |
|
|
+--------------+
|
| 409 |
|
|
The pin-out file can be found in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.pin.
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
+---------------------------------------------------------------------------------------------+
|
| 413 |
|
|
; Fitter Resource Usage Summary ;
|
| 414 |
|
|
+-------------------------------------------------------------+-----------------------+-------+
|
| 415 |
|
|
; Resource ; Usage ; % ;
|
| 416 |
|
|
+-------------------------------------------------------------+-----------------------+-------+
|
| 417 |
40 |
redbear |
; Logic utilization (ALMs needed / total ALMs on device) ; 3,362 / 15,880 ; 21 % ;
|
| 418 |
|
|
; ALMs needed [=A-B+C] ; 3,362 ; ;
|
| 419 |
|
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3,835 / 15,880 ; 24 % ;
|
| 420 |
|
|
; [a] ALMs used for LUT logic and registers ; 1,626 ; ;
|
| 421 |
|
|
; [b] ALMs used for LUT logic ; 1,539 ; ;
|
| 422 |
|
|
; [c] ALMs used for registers ; 670 ; ;
|
| 423 |
32 |
redbear |
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
| 424 |
40 |
redbear |
; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15,880 ; 3 % ;
|
| 425 |
|
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15,880 ; < 1 % ;
|
| 426 |
32 |
redbear |
; [a] Due to location constrained logic ; 0 ; ;
|
| 427 |
40 |
redbear |
; [b] Due to LAB-wide signal conflicts ; 10 ; ;
|
| 428 |
|
|
; [c] Due to LAB input limits ; 6 ; ;
|
| 429 |
32 |
redbear |
; [d] Due to virtual I/Os ; 0 ; ;
|
| 430 |
|
|
; ; ; ;
|
| 431 |
|
|
; Difficulty packing design ; Low ; ;
|
| 432 |
|
|
; ; ; ;
|
| 433 |
40 |
redbear |
; Total LABs: partially or completely used ; 464 / 1,588 ; 29 % ;
|
| 434 |
|
|
; -- Logic LABs ; 464 ; ;
|
| 435 |
32 |
redbear |
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
| 436 |
|
|
; ; ; ;
|
| 437 |
40 |
redbear |
; Combinational ALUT usage for logic ; 5,522 ; ;
|
| 438 |
|
|
; -- 7 input functions ; 72 ; ;
|
| 439 |
|
|
; -- 6 input functions ; 1,329 ; ;
|
| 440 |
|
|
; -- 5 input functions ; 874 ; ;
|
| 441 |
|
|
; -- 4 input functions ; 1,532 ; ;
|
| 442 |
|
|
; -- <=3 input functions ; 1,715 ; ;
|
| 443 |
|
|
; Combinational ALUT usage for route-throughs ; 415 ; ;
|
| 444 |
32 |
redbear |
; ; ; ;
|
| 445 |
40 |
redbear |
; Dedicated logic registers ; 4,628 ; ;
|
| 446 |
32 |
redbear |
; -- By type: ; ; ;
|
| 447 |
40 |
redbear |
; -- Primary logic registers ; 4,592 / 31,760 ; 14 % ;
|
| 448 |
|
|
; -- Secondary logic registers ; 36 / 31,760 ; < 1 % ;
|
| 449 |
32 |
redbear |
; -- By function: ; ; ;
|
| 450 |
40 |
redbear |
; -- Design implementation registers ; 4,628 ; ;
|
| 451 |
32 |
redbear |
; -- Routing optimization registers ; 0 ; ;
|
| 452 |
|
|
; ; ; ;
|
| 453 |
|
|
; Virtual pins ; 0 ; ;
|
| 454 |
|
|
; I/O pins ; 19 / 314 ; 6 % ;
|
| 455 |
|
|
; -- Clock pins ; 2 / 6 ; 33 % ;
|
| 456 |
|
|
; -- Dedicated input pins ; 0 / 21 ; 0 % ;
|
| 457 |
40 |
redbear |
; I/O registers ; 5 ; ;
|
| 458 |
32 |
redbear |
; ; ; ;
|
| 459 |
|
|
; Hard processor system peripheral utilization ; ; ;
|
| 460 |
|
|
; -- Boot from FPGA ; 1 / 1 ( 100 % ) ; ;
|
| 461 |
|
|
; -- Clock resets ; 1 / 1 ( 100 % ) ; ;
|
| 462 |
|
|
; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
|
| 463 |
|
|
; -- S2F AXI ; 1 / 1 ( 100 % ) ; ;
|
| 464 |
|
|
; -- F2S AXI ; 1 / 1 ( 100 % ) ; ;
|
| 465 |
|
|
; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
|
| 466 |
|
|
; -- SDRAM ; 1 / 1 ( 100 % ) ; ;
|
| 467 |
|
|
; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
|
| 468 |
|
|
; -- JTAG ; 0 / 1 ( 0 % ) ; ;
|
| 469 |
|
|
; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
|
| 470 |
|
|
; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
|
| 471 |
|
|
; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
|
| 472 |
|
|
; -- STM event ; 0 / 1 ( 0 % ) ; ;
|
| 473 |
|
|
; -- TPIU trace ; 1 / 1 ( 100 % ) ; ;
|
| 474 |
|
|
; -- DMA ; 0 / 1 ( 0 % ) ; ;
|
| 475 |
|
|
; -- CAN ; 0 / 2 ( 0 % ) ; ;
|
| 476 |
|
|
; -- EMAC ; 0 / 2 ( 0 % ) ; ;
|
| 477 |
|
|
; -- I2C ; 0 / 4 ( 0 % ) ; ;
|
| 478 |
|
|
; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
|
| 479 |
|
|
; -- QSPI ; 0 / 1 ( 0 % ) ; ;
|
| 480 |
|
|
; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
|
| 481 |
|
|
; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
|
| 482 |
|
|
; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
|
| 483 |
|
|
; -- UART ; 0 / 2 ( 0 % ) ; ;
|
| 484 |
|
|
; -- USB ; 0 / 2 ( 0 % ) ; ;
|
| 485 |
|
|
; ; ; ;
|
| 486 |
35 |
redbear |
; M10K blocks ; 0 / 270 ; 0 % ;
|
| 487 |
32 |
redbear |
; Total MLAB memory bits ; 0 ; ;
|
| 488 |
35 |
redbear |
; Total block memory bits ; 0 / 2,764,800 ; 0 % ;
|
| 489 |
|
|
; Total block memory implementation bits ; 0 / 2,764,800 ; 0 % ;
|
| 490 |
32 |
redbear |
; ; ; ;
|
| 491 |
|
|
; Total DSP Blocks ; 0 / 84 ; 0 % ;
|
| 492 |
|
|
; ; ; ;
|
| 493 |
|
|
; Fractional PLLs ; 1 / 5 ; 20 % ;
|
| 494 |
|
|
; Global signals ; 4 ; ;
|
| 495 |
40 |
redbear |
; -- Global clocks ; 3 / 16 ; 19 % ;
|
| 496 |
32 |
redbear |
; -- Quadrant clocks ; 0 / 72 ; 0 % ;
|
| 497 |
|
|
; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ;
|
| 498 |
|
|
; SERDES Transmitters ; 0 / 76 ; 0 % ;
|
| 499 |
|
|
; SERDES Receivers ; 0 / 76 ; 0 % ;
|
| 500 |
|
|
; JTAGs ; 0 / 1 ; 0 % ;
|
| 501 |
|
|
; ASMI blocks ; 0 / 1 ; 0 % ;
|
| 502 |
|
|
; CRC blocks ; 0 / 1 ; 0 % ;
|
| 503 |
|
|
; Remote update blocks ; 0 / 1 ; 0 % ;
|
| 504 |
|
|
; Oscillator blocks ; 0 / 1 ; 0 % ;
|
| 505 |
|
|
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
| 506 |
|
|
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
| 507 |
40 |
redbear |
; Average interconnect usage (total/H/V) ; 6.0% / 6.2% / 5.2% ; ;
|
| 508 |
|
|
; Peak interconnect usage (total/H/V) ; 26.6% / 28.9% / 23.3% ; ;
|
| 509 |
|
|
; Maximum fan-out ; 3073 ; ;
|
| 510 |
|
|
; Highest non-global fan-out ; 2974 ; ;
|
| 511 |
|
|
; Total fan-out ; 40291 ; ;
|
| 512 |
|
|
; Average fan-out ; 3.79 ; ;
|
| 513 |
32 |
redbear |
+-------------------------------------------------------------+-----------------------+-------+
|
| 514 |
|
|
|
| 515 |
|
|
|
| 516 |
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 517 |
|
|
; Fitter Partition Statistics ;
|
| 518 |
|
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
| 519 |
|
|
; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ;
|
| 520 |
|
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
| 521 |
40 |
redbear |
; Logic utilization (ALMs needed / total ALMs on device) ; 3362 / 15880 ( 21 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
| 522 |
|
|
; ALMs needed [=A-B+C] ; 3362 ; 0 ; 0 ;
|
| 523 |
|
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3835 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
| 524 |
|
|
; [a] ALMs used for LUT logic and registers ; 1626 ; 0 ; 0 ;
|
| 525 |
|
|
; [b] ALMs used for LUT logic ; 1539 ; 0 ; 0 ;
|
| 526 |
|
|
; [c] ALMs used for registers ; 670 ; 0 ; 0 ;
|
| 527 |
32 |
redbear |
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ;
|
| 528 |
40 |
redbear |
; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15880 ( 3 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
| 529 |
|
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
| 530 |
32 |
redbear |
; [a] Due to location constrained logic ; 0 ; 0 ; 0 ;
|
| 531 |
40 |
redbear |
; [b] Due to LAB-wide signal conflicts ; 10 ; 0 ; 0 ;
|
| 532 |
|
|
; [c] Due to LAB input limits ; 6 ; 0 ; 0 ;
|
| 533 |
32 |
redbear |
; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ;
|
| 534 |
|
|
; ; ; ; ;
|
| 535 |
|
|
; Difficulty packing design ; Low ; Low ; Low ;
|
| 536 |
|
|
; ; ; ; ;
|
| 537 |
40 |
redbear |
; Total LABs: partially or completely used ; 464 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ;
|
| 538 |
|
|
; -- Logic LABs ; 464 ; 0 ; 0 ;
|
| 539 |
32 |
redbear |
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ;
|
| 540 |
|
|
; ; ; ; ;
|
| 541 |
40 |
redbear |
; Combinational ALUT usage for logic ; 5522 ; 0 ; 0 ;
|
| 542 |
|
|
; -- 7 input functions ; 72 ; 0 ; 0 ;
|
| 543 |
|
|
; -- 6 input functions ; 1329 ; 0 ; 0 ;
|
| 544 |
|
|
; -- 5 input functions ; 874 ; 0 ; 0 ;
|
| 545 |
|
|
; -- 4 input functions ; 1532 ; 0 ; 0 ;
|
| 546 |
|
|
; -- <=3 input functions ; 1715 ; 0 ; 0 ;
|
| 547 |
|
|
; Combinational ALUT usage for route-throughs ; 415 ; 0 ; 0 ;
|
| 548 |
32 |
redbear |
; Memory ALUT usage ; 0 ; 0 ; 0 ;
|
| 549 |
|
|
; -- 64-address deep ; 0 ; 0 ; 0 ;
|
| 550 |
|
|
; -- 32-address deep ; 0 ; 0 ; 0 ;
|
| 551 |
|
|
; ; ; ; ;
|
| 552 |
|
|
; Dedicated logic registers ; 0 ; 0 ; 0 ;
|
| 553 |
|
|
; -- By type: ; ; ; ;
|
| 554 |
40 |
redbear |
; -- Primary logic registers ; 4592 / 31760 ( 14 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
| 555 |
|
|
; -- Secondary logic registers ; 36 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
| 556 |
32 |
redbear |
; -- By function: ; ; ; ;
|
| 557 |
40 |
redbear |
; -- Design implementation registers ; 4628 ; 0 ; 0 ;
|
| 558 |
32 |
redbear |
; -- Routing optimization registers ; 0 ; 0 ; 0 ;
|
| 559 |
|
|
; ; ; ; ;
|
| 560 |
|
|
; ; ; ; ;
|
| 561 |
|
|
; Virtual pins ; 0 ; 0 ; 0 ;
|
| 562 |
|
|
; I/O pins ; 17 ; 0 ; 2 ;
|
| 563 |
40 |
redbear |
; I/O registers ; 5 ; 0 ; 0 ;
|
| 564 |
35 |
redbear |
; Total block memory bits ; 0 ; 0 ; 0 ;
|
| 565 |
|
|
; Total block memory implementation bits ; 0 ; 0 ; 0 ;
|
| 566 |
40 |
redbear |
; Clock enable block ; 0 / 110 ( 0 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ;
|
| 567 |
|
|
; Double data rate I/O output circuitry ; 5 / 304 ( 1 % ) ; 0 / 304 ( 0 % ) ; 0 / 304 ( 0 % ) ;
|
| 568 |
32 |
redbear |
; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| 569 |
|
|
; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
| 570 |
|
|
; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| 571 |
|
|
; HPS clock resets interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| 572 |
|
|
; FPGA-to-HPS interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| 573 |
|
|
; HPS FPGA-to-SDRAM interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| 574 |
|
|
; HPS-to-FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| 575 |
|
|
; HPS TPIU trace interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| 576 |
|
|
; PLL Output Counter ; 0 / 45 ( 0 % ) ; 0 / 45 ( 0 % ) ; 1 / 45 ( 2 % ) ;
|
| 577 |
|
|
; PLL Reconfiguration Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
| 578 |
|
|
; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
| 579 |
|
|
; ; ; ; ;
|
| 580 |
|
|
; Connections ; ; ; ;
|
| 581 |
40 |
redbear |
; -- Input Connections ; 4377 ; 0 ; 40 ;
|
| 582 |
|
|
; -- Registered Input Connections ; 3099 ; 0 ; 0 ;
|
| 583 |
|
|
; -- Output Connections ; 40 ; 0 ; 4377 ;
|
| 584 |
32 |
redbear |
; -- Registered Output Connections ; 1 ; 0 ; 0 ;
|
| 585 |
|
|
; ; ; ; ;
|
| 586 |
|
|
; Internal Connections ; ; ; ;
|
| 587 |
40 |
redbear |
; -- Total Connections ; 40728 ; 0 ; 4454 ;
|
| 588 |
|
|
; -- Registered Connections ; 23593 ; 0 ; 0 ;
|
| 589 |
32 |
redbear |
; ; ; ; ;
|
| 590 |
|
|
; External Connections ; ; ; ;
|
| 591 |
40 |
redbear |
; -- Top ; 0 ; 0 ; 4417 ;
|
| 592 |
32 |
redbear |
; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ;
|
| 593 |
40 |
redbear |
; -- hard_block:auto_generated_inst ; 4417 ; 0 ; 0 ;
|
| 594 |
32 |
redbear |
; ; ; ; ;
|
| 595 |
|
|
; Partition Interface ; ; ; ;
|
| 596 |
40 |
redbear |
; -- Input Ports ; 5 ; 0 ; 41 ;
|
| 597 |
32 |
redbear |
; -- Output Ports ; 10 ; 0 ; 106 ;
|
| 598 |
|
|
; -- Bidir Ports ; 0 ; 0 ; 0 ;
|
| 599 |
|
|
; ; ; ; ;
|
| 600 |
|
|
; Registered Ports ; ; ; ;
|
| 601 |
|
|
; -- Registered Input Ports ; 0 ; 0 ; 0 ;
|
| 602 |
|
|
; -- Registered Output Ports ; 0 ; 0 ; 0 ;
|
| 603 |
|
|
; ; ; ; ;
|
| 604 |
|
|
; Port Connectivity ; ; ; ;
|
| 605 |
|
|
; -- Input Ports driven by GND ; 0 ; 0 ; 0 ;
|
| 606 |
|
|
; -- Output Ports driven by GND ; 0 ; 0 ; 0 ;
|
| 607 |
|
|
; -- Input Ports driven by VCC ; 0 ; 0 ; 0 ;
|
| 608 |
|
|
; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ;
|
| 609 |
|
|
; -- Input Ports with no Source ; 0 ; 0 ; 0 ;
|
| 610 |
|
|
; -- Output Ports with no Source ; 0 ; 0 ; 0 ;
|
| 611 |
|
|
; -- Input Ports with no Fanout ; 0 ; 0 ; 0 ;
|
| 612 |
|
|
; -- Output Ports with no Fanout ; 0 ; 0 ; 0 ;
|
| 613 |
|
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
| 614 |
|
|
|
| 615 |
|
|
|
| 616 |
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 617 |
|
|
; Input Pins ;
|
| 618 |
|
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
| 619 |
|
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
| 620 |
|
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
| 621 |
40 |
redbear |
; FPGA_CLK1_50 ; Y13 ; 4A ; 38 ; 0 ; 0 ; 3074 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
| 622 |
32 |
redbear |
; KEY[0] ; AH17 ; 4A ; 46 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
| 623 |
40 |
redbear |
; KEY[1] ; AH16 ; 4A ; 46 ; 0 ; 51 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
| 624 |
|
|
; din_a ; Y15 ; 4A ; 46 ; 0 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
| 625 |
32 |
redbear |
; din_a(n) ; AA15 ; 4A ; 46 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
| 626 |
40 |
redbear |
; sin_a ; AE20 ; 4A ; 51 ; 0 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
| 627 |
32 |
redbear |
; sin_a(n) ; AD20 ; 4A ; 51 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
| 628 |
|
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
| 629 |
|
|
|
| 630 |
|
|
|
| 631 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 632 |
|
|
; Output Pins ;
|
| 633 |
|
|
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
| 634 |
|
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
| 635 |
|
|
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
| 636 |
40 |
redbear |
; LED[0] ; W15 ; 5A ; 68 ; 12 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 637 |
|
|
; LED[1] ; AA24 ; 5A ; 68 ; 13 ; 37 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 638 |
|
|
; LED[2] ; V16 ; 5A ; 68 ; 13 ; 3 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 639 |
|
|
; LED[3] ; V15 ; 5A ; 68 ; 13 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 640 |
|
|
; LED[4] ; AF26 ; 5A ; 68 ; 10 ; 77 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 641 |
32 |
redbear |
; LED[5] ; AE26 ; 5A ; 68 ; 10 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 642 |
|
|
; LED[6] ; Y16 ; 5A ; 68 ; 12 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 643 |
|
|
; LED[7] ; AA23 ; 5A ; 68 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
| 644 |
|
|
; dout_a ; AG28 ; 4A ; 65 ; 0 ; 34 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
| 645 |
|
|
; dout_a(n) ; AH27 ; 4A ; 65 ; 0 ; 51 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
| 646 |
|
|
; sout_a ; AF20 ; 4A ; 53 ; 0 ; 34 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
| 647 |
|
|
; sout_a(n) ; AG20 ; 4A ; 53 ; 0 ; 51 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
| 648 |
|
|
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
| 649 |
|
|
|
| 650 |
|
|
|
| 651 |
|
|
+----------------------------------------------------------------------------+
|
| 652 |
|
|
; I/O Bank Usage ;
|
| 653 |
|
|
+----------+------------------+---------------+--------------+---------------+
|
| 654 |
|
|
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
|
| 655 |
|
|
+----------+------------------+---------------+--------------+---------------+
|
| 656 |
|
|
; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
|
| 657 |
|
|
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 658 |
|
|
; 3B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 659 |
|
|
; 4A ; 11 / 68 ( 16 % ) ; 2.5V ; -- ; 2.5V ;
|
| 660 |
|
|
; 5A ; 8 / 16 ( 50 % ) ; 3.3V ; -- ; 3.3V ;
|
| 661 |
|
|
; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 662 |
|
|
; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 663 |
|
|
; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 664 |
|
|
; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 665 |
|
|
; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 666 |
|
|
; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 667 |
|
|
; 8A ; 0 / 13 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
| 668 |
|
|
+----------+------------------+---------------+--------------+---------------+
|
| 669 |
|
|
|
| 670 |
|
|
|
| 671 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 672 |
|
|
; All Package Pins ;
|
| 673 |
|
|
+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
|
| 674 |
|
|
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
|
| 675 |
|
|
+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
|
| 676 |
|
|
; A2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 677 |
|
|
; A3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 678 |
|
|
; A4 ; 357 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 679 |
|
|
; A5 ; 353 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 680 |
|
|
; A6 ; 347 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 681 |
|
|
; A7 ; 345 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 682 |
|
|
; A8 ; 343 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 683 |
|
|
; A9 ; 341 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 684 |
|
|
; A10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 685 |
|
|
; A11 ; 339 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 686 |
|
|
; A12 ; 337 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 687 |
|
|
; A13 ; 335 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 688 |
|
|
; A14 ; 333 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 689 |
|
|
; A15 ; 331 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 690 |
|
|
; A16 ; 329 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 691 |
|
|
; A17 ; 321 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 692 |
|
|
; A18 ; 317 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 693 |
|
|
; A19 ; 315 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 694 |
|
|
; A20 ; 313 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 695 |
|
|
; A21 ; 311 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 696 |
|
|
; A22 ; 309 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 697 |
|
|
; A23 ; 296 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
|
| 698 |
|
|
; A24 ; 283 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 699 |
|
|
; A25 ; 281 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 700 |
|
|
; A26 ; 279 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 701 |
|
|
; A27 ; 275 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 702 |
|
|
; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 703 |
|
|
; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 704 |
|
|
; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 705 |
|
|
; AA4 ; 45 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 706 |
|
|
; AA5 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 707 |
|
|
; AA6 ; 29 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
| 708 |
|
|
; AA8 ; 36 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
| 709 |
|
|
; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 710 |
|
|
; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 711 |
|
|
; AA11 ; 50 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 712 |
|
|
; AA12 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 713 |
|
|
; AA13 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 714 |
|
|
; AA14 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 715 |
|
|
; AA15 ; 114 ; 4A ; din_a(n) ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 716 |
|
|
; AA16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 717 |
|
|
; AA17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 718 |
|
|
; AA18 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 719 |
|
|
; AA19 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 720 |
|
|
; AA20 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 721 |
|
|
; AA21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 722 |
|
|
; AA23 ; 180 ; 5A ; LED[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 723 |
|
|
; AA24 ; 178 ; 5A ; LED[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 724 |
|
|
; AA25 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
| 725 |
|
|
; AA26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 726 |
|
|
; AA27 ; 201 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 727 |
|
|
; AA28 ; 211 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 728 |
|
|
; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 729 |
|
|
; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 730 |
|
|
; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 731 |
|
|
; AB4 ; 43 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 732 |
|
|
; AB5 ; 32 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
|
| 733 |
|
|
; AB6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
| 734 |
|
|
; AB23 ; 176 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 735 |
|
|
; AB24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 736 |
|
|
; AB25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 737 |
|
|
; AB26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 738 |
|
|
; AB27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 739 |
|
|
; AB28 ; 199 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 740 |
|
|
; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 741 |
|
|
; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 742 |
|
|
; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 743 |
|
|
; AC4 ; 49 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 744 |
|
|
; AC5 ; 33 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
| 745 |
|
|
; AC6 ; 35 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
| 746 |
|
|
; AC7 ; 30 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
|
| 747 |
|
|
; AC8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 748 |
|
|
; AC21 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 749 |
|
|
; AC22 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 750 |
|
|
; AC23 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 751 |
|
|
; AC24 ; 174 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 752 |
|
|
; AC25 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
| 753 |
|
|
; AC26 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
| 754 |
|
|
; AC27 ; 197 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 755 |
|
|
; AC28 ; 195 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 756 |
|
|
; AD1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 757 |
|
|
; AD2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 758 |
|
|
; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 759 |
|
|
; AD4 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 760 |
|
|
; AD5 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 761 |
|
|
; AD6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 762 |
|
|
; AD7 ; 37 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
| 763 |
|
|
; AD8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 764 |
|
|
; AD9 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 765 |
|
|
; AD10 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 766 |
|
|
; AD11 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 767 |
|
|
; AD12 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 768 |
|
|
; AD13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 769 |
|
|
; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 770 |
|
|
; AD15 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 771 |
|
|
; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 772 |
|
|
; AD17 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 773 |
|
|
; AD18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 774 |
|
|
; AD19 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 775 |
|
|
; AD20 ; 127 ; 4A ; sin_a(n) ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 776 |
|
|
; AD21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 777 |
|
|
; AD22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 778 |
|
|
; AD23 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 779 |
|
|
; AD24 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
| 780 |
|
|
; AD25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 781 |
|
|
; AD26 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 782 |
|
|
; AD27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 783 |
|
|
; AD28 ; 185 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 784 |
|
|
; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 785 |
|
|
; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 786 |
|
|
; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 787 |
|
|
; AE4 ; 56 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 788 |
|
|
; AE5 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
| 789 |
|
|
; AE6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 790 |
|
|
; AE7 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 791 |
|
|
; AE8 ; 64 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 792 |
|
|
; AE9 ; 55 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 793 |
|
|
; AE10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 794 |
|
|
; AE11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 795 |
|
|
; AE12 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 796 |
|
|
; AE13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 797 |
|
|
; AE14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 798 |
|
|
; AE15 ; 95 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 799 |
|
|
; AE16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 800 |
|
|
; AE17 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 801 |
|
|
; AE18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 802 |
|
|
; AE19 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 803 |
|
|
; AE20 ; 129 ; 4A ; sin_a ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 804 |
|
|
; AE21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 805 |
|
|
; AE22 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 806 |
|
|
; AE23 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 807 |
|
|
; AE24 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 808 |
|
|
; AE25 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 809 |
|
|
; AE26 ; 168 ; 5A ; LED[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 810 |
|
|
; AE27 ; 187 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 811 |
|
|
; AE28 ; 183 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 812 |
|
|
; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 813 |
|
|
; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 814 |
|
|
; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 815 |
|
|
; AF4 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 816 |
|
|
; AF5 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 817 |
|
|
; AF6 ; 67 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 818 |
|
|
; AF7 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 819 |
|
|
; AF8 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 820 |
|
|
; AF9 ; 62 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 821 |
|
|
; AF10 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 822 |
|
|
; AF11 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 823 |
|
|
; AF12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
|
| 824 |
|
|
; AF13 ; 87 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 825 |
|
|
; AF14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 826 |
|
|
; AF15 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 827 |
|
|
; AF16 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
| 828 |
|
|
; AF17 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 829 |
|
|
; AF18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 830 |
|
|
; AF19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 831 |
|
|
; AF20 ; 133 ; 4A ; sout_a ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 832 |
|
|
; AF21 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 833 |
|
|
; AF22 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 834 |
|
|
; AF23 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 835 |
|
|
; AF24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 836 |
|
|
; AF25 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 837 |
|
|
; AF26 ; 166 ; 5A ; LED[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 838 |
|
|
; AF27 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 839 |
|
|
; AF28 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 840 |
|
|
; AG1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 841 |
|
|
; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 842 |
|
|
; AG3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 843 |
|
|
; AG4 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 844 |
|
|
; AG5 ; 80 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 845 |
|
|
; AG6 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 846 |
|
|
; AG7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 847 |
|
|
; AG8 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 848 |
|
|
; AG9 ; 93 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 849 |
|
|
; AG10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 850 |
|
|
; AG11 ; 101 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 851 |
|
|
; AG12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 852 |
|
|
; AG13 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 853 |
|
|
; AG14 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 854 |
|
|
; AG15 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 855 |
|
|
; AG16 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 856 |
|
|
; AG17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 857 |
|
|
; AG18 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 858 |
|
|
; AG19 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 859 |
|
|
; AG20 ; 131 ; 4A ; sout_a(n) ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 860 |
|
|
; AG21 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 861 |
|
|
; AG22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 862 |
|
|
; AG23 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 863 |
|
|
; AG24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 864 |
|
|
; AG25 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 865 |
|
|
; AG26 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 866 |
|
|
; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 867 |
|
|
; AG28 ; 160 ; 4A ; dout_a ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 868 |
|
|
; AH2 ; 75 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 869 |
|
|
; AH3 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 870 |
|
|
; AH4 ; 78 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 871 |
|
|
; AH5 ; 83 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 872 |
|
|
; AH6 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 873 |
|
|
; AH7 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 874 |
|
|
; AH8 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 875 |
|
|
; AH9 ; 94 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 876 |
|
|
; AH10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 877 |
|
|
; AH11 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 878 |
|
|
; AH12 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 879 |
|
|
; AH13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 880 |
|
|
; AH14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 881 |
|
|
; AH15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 882 |
|
|
; AH16 ; 115 ; 4A ; KEY[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
|
| 883 |
|
|
; AH17 ; 117 ; 4A ; KEY[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
|
| 884 |
|
|
; AH18 ; 123 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 885 |
|
|
; AH19 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 886 |
|
|
; AH20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 887 |
|
|
; AH21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 888 |
|
|
; AH22 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 889 |
|
|
; AH23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 890 |
|
|
; AH24 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 891 |
|
|
; AH25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 892 |
|
|
; AH26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 893 |
|
|
; AH27 ; 158 ; 4A ; dout_a(n) ; output ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 894 |
|
|
; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ;
|
| 895 |
|
|
; B2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 896 |
|
|
; B3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 897 |
|
|
; B4 ; 359 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 898 |
|
|
; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 899 |
|
|
; B6 ; 355 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 900 |
|
|
; B7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 901 |
|
|
; B8 ; 361 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 902 |
|
|
; B9 ; 363 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 903 |
|
|
; B10 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 904 |
|
|
; B11 ; 362 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 905 |
|
|
; B12 ; 360 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 906 |
|
|
; B13 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 907 |
|
|
; B14 ; 349 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 908 |
|
|
; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 909 |
|
|
; B16 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 910 |
|
|
; B17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 911 |
|
|
; B18 ; 319 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 912 |
|
|
; B19 ; 325 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 913 |
|
|
; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 914 |
|
|
; B21 ; 310 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 915 |
|
|
; B22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 916 |
|
|
; B23 ; 298 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
|
| 917 |
|
|
; B24 ; 285 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 918 |
|
|
; B25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 919 |
|
|
; B26 ; 273 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 920 |
|
|
; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 921 |
|
|
; B28 ; 265 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 922 |
|
|
; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 923 |
|
|
; C2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 924 |
|
|
; C3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 925 |
|
|
; C4 ; 368 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 926 |
|
|
; C5 ; 375 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 927 |
|
|
; C6 ; 373 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 928 |
|
|
; C7 ; 371 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 929 |
|
|
; C8 ; 369 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 930 |
|
|
; C9 ; 367 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 931 |
|
|
; C10 ; 365 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 932 |
|
|
; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 933 |
|
|
; C12 ; 382 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 934 |
|
|
; C13 ; 354 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 935 |
|
|
; C14 ; 348 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 936 |
|
|
; C15 ; 340 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 937 |
|
|
; C16 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 938 |
|
|
; C17 ; 318 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 939 |
|
|
; C18 ; 316 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 940 |
|
|
; C19 ; 323 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 941 |
|
|
; C20 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 942 |
|
|
; C21 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 943 |
|
|
; C22 ; 302 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
|
| 944 |
|
|
; C23 ; 300 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
|
| 945 |
|
|
; C24 ; 289 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 946 |
|
|
; C25 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 947 |
|
|
; C26 ; 271 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 948 |
|
|
; C27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 949 |
|
|
; C28 ; 263 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 950 |
|
|
; D1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 951 |
|
|
; D2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 952 |
|
|
; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 953 |
|
|
; D4 ; 370 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 954 |
|
|
; D5 ; 377 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 955 |
|
|
; D6 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 956 |
|
|
; D7 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
| 957 |
|
|
; D8 ; 387 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 958 |
|
|
; D9 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
| 959 |
|
|
; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 960 |
|
|
; D11 ; 398 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 961 |
|
|
; D12 ; 380 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 962 |
|
|
; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 963 |
|
|
; D14 ; 352 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 964 |
|
|
; D15 ; 342 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 965 |
|
|
; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 966 |
|
|
; D17 ; 332 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 967 |
|
|
; D18 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 968 |
|
|
; D19 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
|
| 969 |
|
|
; D20 ; 307 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
|
| 970 |
|
|
; D21 ; 304 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
|
| 971 |
|
|
; D22 ; 303 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
|
| 972 |
|
|
; D23 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 973 |
|
|
; D24 ; 287 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 974 |
|
|
; D25 ; 293 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
|
| 975 |
|
|
; D26 ; 269 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 976 |
|
|
; D27 ; 257 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 977 |
|
|
; D28 ; 255 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 978 |
|
|
; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 979 |
|
|
; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 980 |
|
|
; E3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 981 |
|
|
; E4 ; 364 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 982 |
|
|
; E5 ; 376 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 983 |
|
|
; E6 ; 432 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
|
| 984 |
|
|
; E7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 985 |
|
|
; E8 ; 385 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 986 |
|
|
; E9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 987 |
|
|
; E10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 988 |
|
|
; E11 ; 396 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 989 |
|
|
; E12 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 990 |
|
|
; E13 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 991 |
|
|
; E14 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 992 |
|
|
; E15 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 993 |
|
|
; E16 ; 334 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 994 |
|
|
; E17 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 995 |
|
|
; E18 ; 305 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
|
| 996 |
|
|
; E19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 997 |
|
|
; E20 ; 306 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
|
| 998 |
|
|
; E21 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 999 |
|
|
; E22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1000 |
|
|
; E23 ; 295 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
|
| 1001 |
|
|
; E24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1002 |
|
|
; E25 ; 291 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1003 |
|
|
; E26 ; 267 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1004 |
|
|
; E27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1005 |
|
|
; E28 ; 259 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1006 |
|
|
; F1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1007 |
|
|
; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1008 |
|
|
; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1009 |
|
|
; F4 ; 372 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1010 |
|
|
; F5 ; 366 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1011 |
|
|
; F6 ; 437 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
|
| 1012 |
|
|
; F7 ; 435 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
|
| 1013 |
|
|
; F8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1014 |
|
|
; F21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1015 |
|
|
; F22 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
| 1016 |
|
|
; F23 ; 294 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
|
| 1017 |
|
|
; F24 ; 292 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1018 |
|
|
; F25 ; 284 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1019 |
|
|
; F26 ; 282 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1020 |
|
|
; F27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1021 |
|
|
; F28 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1022 |
|
|
; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1023 |
|
|
; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1024 |
|
|
; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1025 |
|
|
; G4 ; 374 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1026 |
|
|
; G5 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1027 |
|
|
; G6 ; 433 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
|
| 1028 |
|
|
; G23 ; 290 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1029 |
|
|
; G24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1030 |
|
|
; G25 ; 276 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1031 |
|
|
; G26 ; 253 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1032 |
|
|
; G27 ; 251 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1033 |
|
|
; G28 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1034 |
|
|
; H1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1035 |
|
|
; H2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1036 |
|
|
; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1037 |
|
|
; H4 ; 427 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1038 |
|
|
; H5 ; 423 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1039 |
|
|
; H6 ; 421 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1040 |
|
|
; H8 ; 431 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
|
| 1041 |
|
|
; H9 ; 430 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
|
| 1042 |
|
|
; H10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
| 1043 |
|
|
; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1044 |
|
|
; H12 ; 358 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1045 |
|
|
; H13 ; 356 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1046 |
|
|
; H14 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1047 |
|
|
; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1048 |
|
|
; H16 ; 344 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1049 |
|
|
; H17 ; 322 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1050 |
|
|
; H18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1051 |
|
|
; H19 ; 297 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
|
| 1052 |
|
|
; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1053 |
|
|
; H21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1054 |
|
|
; H23 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1055 |
|
|
; H24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1056 |
|
|
; H25 ; 274 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1057 |
|
|
; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1058 |
|
|
; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1059 |
|
|
; H28 ; 261 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
|
| 1060 |
|
|
; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1061 |
|
|
; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1062 |
|
|
; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1063 |
|
|
; J4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1064 |
|
|
; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1065 |
|
|
; J8 ; 429 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
|
| 1066 |
|
|
; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1067 |
|
|
; J10 ; 428 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
|
| 1068 |
|
|
; J11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1069 |
|
|
; J12 ; 338 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1070 |
|
|
; J13 ; 336 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1071 |
|
|
; J14 ; 330 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1072 |
|
|
; J15 ; 328 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1073 |
|
|
; J16 ; 346 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1074 |
|
|
; J17 ; 320 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1075 |
|
|
; J18 ; 314 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1076 |
|
|
; J19 ; 299 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
|
| 1077 |
|
|
; J20 ; 268 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1078 |
|
|
; J21 ; 266 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1079 |
|
|
; J24 ; 258 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1080 |
|
|
; J25 ; 260 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1081 |
|
|
; J26 ; 252 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1082 |
|
|
; J27 ; 243 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1083 |
|
|
; J28 ; 241 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1084 |
|
|
; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1085 |
|
|
; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1086 |
|
|
; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1087 |
|
|
; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1088 |
|
|
; K5 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1089 |
|
|
; K8 ; 426 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1090 |
|
|
; K9 ; 436 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
|
| 1091 |
|
|
; K10 ; 434 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
|
| 1092 |
|
|
; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1093 |
|
|
; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1094 |
|
|
; K13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1095 |
|
|
; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1096 |
|
|
; K15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1097 |
|
|
; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1098 |
|
|
; K17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1099 |
|
|
; K18 ; 312 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1100 |
|
|
; K19 ; 301 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
|
| 1101 |
|
|
; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1102 |
|
|
; K21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1103 |
|
|
; K24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1104 |
|
|
; K25 ; 244 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1105 |
|
|
; K26 ; 250 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1106 |
|
|
; K27 ; 245 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1107 |
|
|
; K28 ; 239 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1108 |
|
|
; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1109 |
|
|
; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1110 |
|
|
; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1111 |
|
|
; L4 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1112 |
|
|
; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1113 |
|
|
; L8 ; 424 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1114 |
|
|
; L9 ; 422 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1115 |
|
|
; L10 ; 420 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1116 |
|
|
; L11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1117 |
|
|
; L12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1118 |
|
|
; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1119 |
|
|
; L14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1120 |
|
|
; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1121 |
|
|
; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1122 |
|
|
; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1123 |
|
|
; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1124 |
|
|
; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1125 |
|
|
; L20 ; 288 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1126 |
|
|
; L21 ; 286 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1127 |
|
|
; L24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1128 |
|
|
; L25 ; 242 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1129 |
|
|
; L26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1130 |
|
|
; L27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1131 |
|
|
; L28 ; 237 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1132 |
|
|
; M1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1133 |
|
|
; M2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1134 |
|
|
; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1135 |
|
|
; M4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1136 |
|
|
; M5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1137 |
|
|
; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1138 |
|
|
; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1139 |
|
|
; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1140 |
|
|
; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1141 |
|
|
; M12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1142 |
|
|
; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1143 |
|
|
; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1144 |
|
|
; M15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1145 |
|
|
; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1146 |
|
|
; M17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1147 |
|
|
; M18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1148 |
|
|
; M19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1149 |
|
|
; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1150 |
|
|
; M21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1151 |
|
|
; M24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1152 |
|
|
; M25 ; 246 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1153 |
|
|
; M26 ; 234 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1154 |
|
|
; M27 ; 236 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1155 |
|
|
; M28 ; 235 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1156 |
|
|
; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1157 |
|
|
; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1158 |
|
|
; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1159 |
|
|
; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1160 |
|
|
; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1161 |
|
|
; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1162 |
|
|
; N9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1163 |
|
|
; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1164 |
|
|
; N11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1165 |
|
|
; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1166 |
|
|
; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1167 |
|
|
; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1168 |
|
|
; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1169 |
|
|
; N16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1170 |
|
|
; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1171 |
|
|
; N18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1172 |
|
|
; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1173 |
|
|
; N20 ; 272 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1174 |
|
|
; N21 ; 270 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1175 |
|
|
; N24 ; 228 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1176 |
|
|
; N25 ; 226 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1177 |
|
|
; N26 ; 220 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1178 |
|
|
; N27 ; 218 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1179 |
|
|
; N28 ; 233 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1180 |
|
|
; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1181 |
|
|
; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1182 |
|
|
; P3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1183 |
|
|
; P4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1184 |
|
|
; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1185 |
|
|
; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1186 |
|
|
; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1187 |
|
|
; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1188 |
|
|
; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1189 |
|
|
; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1190 |
|
|
; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1191 |
|
|
; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1192 |
|
|
; P15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1193 |
|
|
; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1194 |
|
|
; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1195 |
|
|
; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1196 |
|
|
; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1197 |
|
|
; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1198 |
|
|
; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1199 |
|
|
; P24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1200 |
|
|
; P25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1201 |
|
|
; P26 ; 221 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1202 |
|
|
; P27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1203 |
|
|
; P28 ; 231 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1204 |
|
|
; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1205 |
|
|
; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1206 |
|
|
; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1207 |
|
|
; R4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1208 |
|
|
; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1209 |
|
|
; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1210 |
|
|
; R9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1211 |
|
|
; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1212 |
|
|
; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1213 |
|
|
; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1214 |
|
|
; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1215 |
|
|
; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1216 |
|
|
; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1217 |
|
|
; R16 ; 256 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1218 |
|
|
; R17 ; 254 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1219 |
|
|
; R18 ; 240 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1220 |
|
|
; R19 ; 238 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1221 |
|
|
; R20 ; 232 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1222 |
|
|
; R21 ; 230 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1223 |
|
|
; R24 ; 204 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1224 |
|
|
; R25 ; 210 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1225 |
|
|
; R26 ; 212 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1226 |
|
|
; R27 ; 219 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1227 |
|
|
; R28 ; 229 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1228 |
|
|
; T1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1229 |
|
|
; T2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1230 |
|
|
; T3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1231 |
|
|
; T4 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1232 |
|
|
; T5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1233 |
|
|
; T8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1234 |
|
|
; T9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1235 |
|
|
; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1236 |
|
|
; T11 ; 60 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1237 |
|
|
; T12 ; 74 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1238 |
|
|
; T13 ; 76 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1239 |
|
|
; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1240 |
|
|
; T15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1241 |
|
|
; T16 ; 214 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1242 |
|
|
; T17 ; 216 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1243 |
|
|
; T18 ; 224 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1244 |
|
|
; T19 ; 222 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1245 |
|
|
; T20 ; 208 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1246 |
|
|
; T21 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1247 |
|
|
; T24 ; 202 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1248 |
|
|
; T25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1249 |
|
|
; T26 ; 196 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1250 |
|
|
; T27 ; 205 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
|
| 1251 |
|
|
; T28 ; 227 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1252 |
|
|
; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1253 |
|
|
; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1254 |
|
|
; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1255 |
|
|
; U4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1256 |
|
|
; U5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1257 |
|
|
; U8 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1258 |
|
|
; U9 ; 44 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1259 |
|
|
; U10 ; 48 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1260 |
|
|
; U11 ; 58 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1261 |
|
|
; U12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1262 |
|
|
; U13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1263 |
|
|
; U14 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1264 |
|
|
; U15 ; 200 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1265 |
|
|
; U16 ; 198 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1266 |
|
|
; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1267 |
|
|
; U18 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1268 |
|
|
; U19 ; 206 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1269 |
|
|
; U20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1270 |
|
|
; U21 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1271 |
|
|
; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1272 |
|
|
; U25 ; 194 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1273 |
|
|
; U26 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
| 1274 |
|
|
; U27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1275 |
|
|
; U28 ; 225 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1276 |
|
|
; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1277 |
|
|
; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1278 |
|
|
; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1279 |
|
|
; V4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1280 |
|
|
; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1281 |
|
|
; V8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1282 |
|
|
; V9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1283 |
|
|
; V10 ; 46 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1284 |
|
|
; V11 ; 68 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1285 |
|
|
; V12 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1286 |
|
|
; V13 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1287 |
|
|
; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1288 |
|
|
; V15 ; 181 ; 5A ; LED[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 1289 |
|
|
; V16 ; 179 ; 5A ; LED[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 1290 |
|
|
; V17 ; 192 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1291 |
|
|
; V18 ; 190 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1292 |
|
|
; V19 ; 188 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1293 |
|
|
; V20 ; 186 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1294 |
|
|
; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1295 |
|
|
; V24 ; 191 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1296 |
|
|
; V25 ; 193 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1297 |
|
|
; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1298 |
|
|
; V27 ; 217 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1299 |
|
|
; V28 ; 223 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1300 |
|
|
; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1301 |
|
|
; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1302 |
|
|
; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1303 |
|
|
; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1304 |
|
|
; W5 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1305 |
|
|
; W8 ; 40 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1306 |
|
|
; W9 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1307 |
|
|
; W10 ; 34 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
|
| 1308 |
|
|
; W11 ; 66 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1309 |
|
|
; W12 ; 82 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1310 |
|
|
; W13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1311 |
|
|
; W14 ; 108 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1312 |
|
|
; W15 ; 177 ; 5A ; LED[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 1313 |
|
|
; W16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1314 |
|
|
; W17 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
| 1315 |
|
|
; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1316 |
|
|
; W19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
| 1317 |
|
|
; W20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1318 |
|
|
; W21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1319 |
|
|
; W24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1320 |
|
|
; W25 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
| 1321 |
|
|
; W26 ; 209 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1322 |
|
|
; W27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
| 1323 |
|
|
; W28 ; 215 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1324 |
|
|
; Y1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1325 |
|
|
; Y2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
| 1326 |
|
|
; Y3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1327 |
|
|
; Y4 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1328 |
|
|
; Y5 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1329 |
|
|
; Y8 ; 38 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1330 |
|
|
; Y9 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
|
| 1331 |
|
|
; Y10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
| 1332 |
|
|
; Y11 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
| 1333 |
|
|
; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1334 |
|
|
; Y13 ; 100 ; 4A ; FPGA_CLK1_50 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
|
| 1335 |
|
|
; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1336 |
|
|
; Y15 ; 116 ; 4A ; din_a ; input ; LVDS ; ; Column I/O ; Y ; no ; Off ;
|
| 1337 |
|
|
; Y16 ; 175 ; 5A ; LED[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
|
| 1338 |
|
|
; Y17 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1339 |
|
|
; Y18 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1340 |
|
|
; Y19 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1341 |
|
|
; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1342 |
|
|
; Y21 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
| 1343 |
|
|
; Y24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1344 |
|
|
; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
| 1345 |
|
|
; Y26 ; 207 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1346 |
|
|
; Y27 ; 203 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1347 |
|
|
; Y28 ; 213 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
| 1348 |
|
|
+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
|
| 1349 |
|
|
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
|
| 1350 |
|
|
|
| 1351 |
|
|
|
| 1352 |
|
|
+-------------------------------------------------+
|
| 1353 |
|
|
; I/O Assignment Warnings ;
|
| 1354 |
|
|
+----------+--------------------------------------+
|
| 1355 |
|
|
; Pin Name ; Reason ;
|
| 1356 |
|
|
+----------+--------------------------------------+
|
| 1357 |
|
|
; LED[5] ; Missing drive strength and slew rate ;
|
| 1358 |
|
|
; LED[7] ; Missing drive strength and slew rate ;
|
| 1359 |
|
|
; LED[0] ; Missing drive strength and slew rate ;
|
| 1360 |
|
|
; LED[1] ; Missing drive strength and slew rate ;
|
| 1361 |
|
|
; LED[2] ; Missing drive strength and slew rate ;
|
| 1362 |
|
|
; LED[3] ; Missing drive strength and slew rate ;
|
| 1363 |
|
|
; LED[4] ; Missing drive strength and slew rate ;
|
| 1364 |
|
|
; LED[6] ; Missing drive strength and slew rate ;
|
| 1365 |
|
|
+----------+--------------------------------------+
|
| 1366 |
|
|
|
| 1367 |
|
|
|
| 1368 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1369 |
|
|
; PLL Usage Summary ;
|
| 1370 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
|
| 1371 |
|
|
; ; ;
|
| 1372 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
|
| 1373 |
|
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll ; ;
|
| 1374 |
|
|
; -- PLL Type ; Integer PLL ;
|
| 1375 |
|
|
; -- PLL Location ; FRACTIONALPLL_X68_Y1_N0 ;
|
| 1376 |
40 |
redbear |
; -- PLL Feedback clock type ; Global Clock ;
|
| 1377 |
32 |
redbear |
; -- PLL Bandwidth ; Auto ;
|
| 1378 |
40 |
redbear |
; -- PLL Bandwidth Range ; 1200000 to 600000 Hz ;
|
| 1379 |
|
|
; -- Reference Clock Frequency ; 50.0 MHz ;
|
| 1380 |
32 |
redbear |
; -- Reference Clock Sourced by ; Dedicated Pin ;
|
| 1381 |
|
|
; -- PLL VCO Frequency ; 400.0 MHz ;
|
| 1382 |
40 |
redbear |
; -- PLL Operation Mode ; Normal ;
|
| 1383 |
|
|
; -- PLL Freq Min Lock ; 37.500000 MHz ;
|
| 1384 |
|
|
; -- PLL Freq Max Lock ; 100.000000 MHz ;
|
| 1385 |
32 |
redbear |
; -- PLL Enable ; On ;
|
| 1386 |
|
|
; -- PLL Fractional Division ; N/A ;
|
| 1387 |
40 |
redbear |
; -- M Counter ; 16 ;
|
| 1388 |
32 |
redbear |
; -- N Counter ; 2 ;
|
| 1389 |
|
|
; -- PLL Refclk Select ; ;
|
| 1390 |
|
|
; -- PLL Refclk Select Location ; PLLREFCLKSELECT_X68_Y7_N0 ;
|
| 1391 |
|
|
; -- PLL Reference Clock Input 0 source ; clk_0 ;
|
| 1392 |
|
|
; -- PLL Reference Clock Input 1 source ; clk_1 ;
|
| 1393 |
|
|
; -- ADJPLLIN source ; N/A ;
|
| 1394 |
|
|
; -- CORECLKIN source ; N/A ;
|
| 1395 |
|
|
; -- IQTXRXCLKIN source ; N/A ;
|
| 1396 |
|
|
; -- PLLIQCLKIN source ; N/A ;
|
| 1397 |
|
|
; -- RXIQCLKIN source ; N/A ;
|
| 1398 |
|
|
; -- CLKIN(0) source ; FPGA_CLK1_50~input ;
|
| 1399 |
|
|
; -- CLKIN(1) source ; N/A ;
|
| 1400 |
|
|
; -- CLKIN(2) source ; N/A ;
|
| 1401 |
|
|
; -- CLKIN(3) source ; N/A ;
|
| 1402 |
|
|
; -- PLL Output Counter ; ;
|
| 1403 |
|
|
; -- ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter ; ;
|
| 1404 |
|
|
; -- Output Clock Frequency ; 400.0 MHz ;
|
| 1405 |
35 |
redbear |
; -- Output Clock Location ; PLLOUTPUTCOUNTER_X68_Y3_N1 ;
|
| 1406 |
32 |
redbear |
; -- C Counter Odd Divider Even Duty Enable ; Off ;
|
| 1407 |
|
|
; -- Duty Cycle ; 50.0000 ;
|
| 1408 |
|
|
; -- Phase Shift ; 0.000000 degrees ;
|
| 1409 |
|
|
; -- C Counter ; 1 ;
|
| 1410 |
|
|
; -- C Counter PH Mux PRST ; 0 ;
|
| 1411 |
|
|
; -- C Counter PRST ; 1 ;
|
| 1412 |
|
|
; ; ;
|
| 1413 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
|
| 1414 |
|
|
|
| 1415 |
|
|
|
| 1416 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1417 |
|
|
; Fitter Resource Utilization by Entity ;
|
| 1418 |
|
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
| 1419 |
|
|
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
| 1420 |
|
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
| 1421 |
40 |
redbear |
; |SPW_ULIGHT_FIFO ; 3361.5 (0.5) ; 3835.0 (0.5) ; 488.5 (0.0) ; 15.0 (0.0) ; 0.0 (0.0) ; 5522 (1) ; 4628 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ;
|
| 1422 |
|
|
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 109.5 (109.5) ; 117.7 (117.7) ; 9.2 (9.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 184 (184) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ;
|
| 1423 |
|
|
; |debounce_db:db_system_spwulight_b| ; 18.5 (18.5) ; 19.5 (19.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (37) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ;
|
| 1424 |
|
|
; |detector_tokens:m_x| ; 18.8 (9.2) ; 22.5 (10.3) ; 3.7 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (18) ; 38 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ;
|
| 1425 |
|
|
; |bit_capture_control:capture_c| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c ; bit_capture_control ; work ;
|
| 1426 |
|
|
; |bit_capture_data:capture_d| ; 1.7 (1.7) ; 2.8 (2.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d ; bit_capture_data ; work ;
|
| 1427 |
|
|
; |counter_neg:cnt_neg| ; 7.3 (7.3) ; 8.3 (8.3) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg ; counter_neg ; work ;
|
| 1428 |
|
|
; |spw_ulight_con_top_x:A_SPW_TOP| ; 839.8 (0.2) ; 1146.0 (0.5) ; 315.8 (0.2) ; 9.5 (0.0) ; 0.0 (0.0) ; 1060 (1) ; 1499 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ;
|
| 1429 |
|
|
; |fifo_rx:rx_data| ; 291.7 (50.6) ; 440.5 (58.3) ; 150.3 (7.7) ; 1.5 (0.0) ; 0.0 (0.0) ; 340 (87) ; 633 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ;
|
| 1430 |
|
|
; |mem_data:mem_dta_fifo_tx| ; 241.1 (241.1) ; 382.2 (382.2) ; 142.6 (142.6) ; 1.5 (1.5) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;
|
| 1431 |
|
|
; |fifo_tx:tx_data| ; 287.5 (31.0) ; 418.8 (32.3) ; 139.3 (1.3) ; 8.0 (0.0) ; 0.0 (0.0) ; 299 (46) ; 627 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ;
|
| 1432 |
|
|
; |mem_data:mem_dta_fifo_tx| ; 256.5 (256.5) ; 386.6 (386.6) ; 138.1 (138.1) ; 8.0 (8.0) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;
|
| 1433 |
|
|
; |top_spw_ultra_light:SPW| ; 260.3 (0.0) ; 286.2 (0.0) ; 25.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 420 (0) ; 239 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ;
|
| 1434 |
|
|
; |FSM_SPW:FSM| ; 75.6 (75.6) ; 78.3 (78.3) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 130 (130) ; 59 (59) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ;
|
| 1435 |
|
|
; |RX_SPW:RX| ; 41.0 (0.3) ; 50.5 (1.5) ; 9.5 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 66 (3) ; 75 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ;
|
| 1436 |
|
|
; |bit_capture_control:capture_c| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c ; bit_capture_control ; work ;
|
| 1437 |
|
|
; |bit_capture_data:capture_d| ; 2.6 (2.6) ; 3.2 (3.2) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d ; bit_capture_data ; work ;
|
| 1438 |
|
|
; |counter_neg:cnt_neg| ; 7.5 (7.5) ; 8.1 (8.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg ; counter_neg ; work ;
|
| 1439 |
|
|
; |rx_buffer_fsm:buffer_fsm| ; 1.3 (1.3) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm ; rx_buffer_fsm ; work ;
|
| 1440 |
|
|
; |rx_control_data_rdy:control_data_rdy| ; 3.0 (3.0) ; 3.7 (3.7) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy ; rx_control_data_rdy ; work ;
|
| 1441 |
|
|
; |rx_data_buffer_data_w:buffer_data_flag| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag ; rx_data_buffer_data_w ; work ;
|
| 1442 |
|
|
; |rx_data_control_p:data_control| ; 10.6 (10.6) ; 10.7 (10.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control ; rx_data_control_p ; work ;
|
| 1443 |
|
|
; |rx_data_receive:rx_dtarcv| ; 13.7 (13.7) ; 19.8 (19.8) ; 6.1 (6.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ; rx_data_receive ; work ;
|
| 1444 |
|
|
; |TX_SPW:TX| ; 143.8 (0.0) ; 157.3 (0.0) ; 13.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 224 (0) ; 105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ;
|
| 1445 |
|
|
; |tx_data_send:tx_data_snd| ; 23.3 (23.3) ; 23.3 (23.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (30) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd ; tx_data_send ; work ;
|
| 1446 |
|
|
; |tx_fsm_m:tx_fsm| ; 120.1 (81.2) ; 134.0 (91.8) ; 13.9 (10.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 194 (132) ; 76 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm ; tx_fsm_m ; work ;
|
| 1447 |
|
|
; |tx_fct_counter:tx_fct_cnt| ; 25.1 (25.1) ; 26.7 (26.7) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (42) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ; tx_fct_counter ; work ;
|
| 1448 |
|
|
; |tx_fct_send:tx_fct_snd| ; 13.8 (13.8) ; 15.5 (15.5) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ; tx_fct_send ; work ;
|
| 1449 |
|
|
; |ulight_fifo:u0| ; 2374.4 (0.0) ; 2528.8 (0.0) ; 158.9 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4210 (0) ; 3049 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ;
|
| 1450 |
32 |
redbear |
; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ;
|
| 1451 |
|
|
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
|
| 1452 |
40 |
redbear |
; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.5 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ;
|
| 1453 |
|
|
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.5 (1.5) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
|
| 1454 |
|
|
; |ulight_fifo_auto_start:auto_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ;
|
| 1455 |
|
|
; |ulight_fifo_auto_start:data_read_en_rx| ; 0.8 (0.8) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ;
|
| 1456 |
|
|
; |ulight_fifo_auto_start:link_disable| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ;
|
| 1457 |
|
|
; |ulight_fifo_auto_start:link_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ;
|
| 1458 |
|
|
; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.2 (1.2) ; 1.4 (1.4) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ;
|
| 1459 |
|
|
; |ulight_fifo_auto_start:write_en_tx| ; 1.3 (1.3) ; 1.4 (1.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ;
|
| 1460 |
|
|
; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ;
|
| 1461 |
|
|
; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
| 1462 |
|
|
; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 2.6 (2.6) ; 3.0 (3.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
| 1463 |
|
|
; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
| 1464 |
|
|
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 4.1 (4.1) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ;
|
| 1465 |
|
|
; |ulight_fifo_data_info:data_info| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ;
|
| 1466 |
32 |
redbear |
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
| 1467 |
40 |
redbear |
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
| 1468 |
|
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
| 1469 |
32 |
redbear |
; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
| 1470 |
40 |
redbear |
; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
| 1471 |
|
|
; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.5 (0.5) ; 0.7 (0.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
| 1472 |
32 |
redbear |
; |ulight_fifo_hps_0:hps_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ;
|
| 1473 |
|
|
; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ;
|
| 1474 |
40 |
redbear |
; |ulight_fifo_led_pio_test:led_pio_test| ; 2.9 (2.9) ; 4.2 (4.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ;
|
| 1475 |
|
|
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2337.0 (0.0) ; 2478.1 (0.0) ; 145.6 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4124 (0) ; 2969 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ;
|
| 1476 |
|
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.3 (3.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1477 |
|
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 20.1 (20.1) ; 21.0 (21.0) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1478 |
|
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 4.3 (4.3) ; 4.3 (4.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1479 |
|
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 20.2 (20.2) ; 20.2 (20.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1480 |
|
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1481 |
|
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.7 (14.7) ; 17.7 (17.7) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1482 |
|
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 6.1 (6.1) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1483 |
|
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 18.2 (18.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1484 |
|
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.0 (9.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1485 |
|
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 18.3 (18.3) ; 18.5 (18.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1486 |
|
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 4.2 (4.2) ; 4.2 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1487 |
|
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 15.1 (15.1) ; 20.6 (20.6) ; 5.6 (5.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1488 |
|
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1489 |
|
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 20.7 (20.7) ; 22.0 (22.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1490 |
|
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.8 (2.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1491 |
|
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.2 (17.2) ; 18.8 (18.8) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1492 |
|
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1493 |
|
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 19.7 (19.7) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1494 |
|
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.8 (2.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1495 |
|
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 18.7 (18.7) ; 19.3 (19.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1496 |
|
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1497 |
|
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.4 (14.4) ; 17.5 (17.5) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1498 |
|
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.2 (5.2) ; 6.3 (6.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1499 |
|
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 17.7 (17.7) ; 19.0 (19.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1500 |
|
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1501 |
|
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 21.0 (21.0) ; 21.6 (21.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1502 |
|
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1503 |
|
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 19.5 (19.5) ; 20.1 (20.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1504 |
|
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1505 |
|
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 20.8 (20.8) ; 22.2 (22.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1506 |
|
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.4 (2.4) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1507 |
|
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 17.0 (17.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1508 |
|
|
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 7.5 (7.5) ; 8.2 (8.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1509 |
|
|
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 17.6 (17.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1510 |
|
|
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 8.0 (8.0) ; 8.2 (8.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1511 |
|
|
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.8 (20.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1512 |
|
|
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1513 |
|
|
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.5 (20.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1514 |
|
|
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.5 (2.5) ; 3.1 (3.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1515 |
|
|
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 18.1 (18.1) ; 18.7 (18.7) ; 1.0 (1.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1516 |
|
|
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.2 (9.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1517 |
|
|
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 20.3 (20.3) ; 20.6 (20.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1518 |
|
|
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1519 |
|
|
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.6 (20.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
| 1520 |
|
|
; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 61.8 (29.2) ; 65.0 (32.7) ; 3.2 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (57) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ;
|
| 1521 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 32.3 (32.3) ; 32.3 (32.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1522 |
|
|
; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 44.3 (0.0) ; 47.3 (0.0) ; 3.0 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1523 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.3 (47.0) ; 3.0 (3.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1524 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1525 |
40 |
redbear |
; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 44.3 (0.0) ; 47.2 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1526 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.2 (46.9) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1527 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1528 |
40 |
redbear |
; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 41.2 (0.0) ; 43.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1529 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.2 (40.9) ; 43.6 (43.1) ; 2.3 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1530 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1531 |
|
|
; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1532 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 41.5 (41.2) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1533 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1534 |
|
|
; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 38.8 (0.0) ; 40.4 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1535 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.8 (38.5) ; 40.4 (40.1) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1536 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1537 |
|
|
; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 39.0 (0.0) ; 40.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1538 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.0 (38.7) ; 40.5 (40.5) ; 1.5 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1539 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1540 |
|
|
; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 44.6 (0.0) ; 48.7 (0.0) ; 4.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1541 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.6 (44.3) ; 48.7 (48.4) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1542 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1543 |
|
|
; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 39.6 (0.0) ; 41.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1544 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.6 (39.3) ; 41.5 (41.2) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1545 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1546 |
|
|
; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 43.5 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1547 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 43.5 (43.2) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1548 |
35 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1549 |
40 |
redbear |
; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 39.3 (0.0) ; 41.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1550 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (39.0) ; 41.6 (41.2) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1551 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1552 |
|
|
; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1553 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.3) ; 41.5 (41.5) ; 1.7 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1554 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1555 |
|
|
; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 40.2 (0.0) ; 44.7 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1556 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.2 (39.8) ; 44.7 (44.3) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (60) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1557 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1558 |
|
|
; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 44.7 (0.0) ; 48.1 (0.0) ; 3.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1559 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.7 (44.4) ; 48.1 (47.8) ; 3.4 (3.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1560 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1561 |
40 |
redbear |
; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 45.7 (0.0) ; 49.6 (0.0) ; 3.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1562 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.4) ; 49.6 (49.3) ; 3.9 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1563 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1564 |
40 |
redbear |
; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 43.4 (0.0) ; 45.8 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1565 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.4 (43.2) ; 45.8 (45.6) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1566 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1567 |
40 |
redbear |
; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 39.3 (0.0) ; 40.8 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1568 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (38.9) ; 40.8 (40.6) ; 1.6 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1569 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1570 |
|
|
; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 41.5 (0.0) ; 42.3 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1571 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.5 (41.2) ; 42.3 (42.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1572 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1573 |
|
|
; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 47.2 (0.0) ; 52.6 (0.0) ; 5.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1574 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 47.2 (47.0) ; 52.6 (52.3) ; 5.3 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1575 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1576 |
40 |
redbear |
; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 46.0 (0.0) ; 47.6 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1577 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.0 (45.8) ; 47.6 (47.3) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (69) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1578 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1579 |
|
|
; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 40.5 (0.0) ; 42.3 (0.0) ; 1.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1580 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.5 (40.2) ; 42.3 (42.3) ; 1.8 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1581 |
|
|
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1582 |
|
|
; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 46.8 (0.0) ; 50.0 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1583 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.8 (46.6) ; 50.0 (49.7) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1584 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1585 |
40 |
redbear |
; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 45.7 (0.0) ; 48.0 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
|
| 1586 |
|
|
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.5) ; 48.0 (47.7) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
|
| 1587 |
32 |
redbear |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
|
| 1588 |
40 |
redbear |
; |altera_merlin_slave_agent:auto_start_s1_agent| ; 14.8 (5.3) ; 14.8 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1589 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1590 |
|
|
; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 15.3 (5.7) ; 15.5 (5.7) ; 0.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1591 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1592 |
|
|
; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.2 (2.7) ; 12.2 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1593 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1594 |
|
|
; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 12.0 (2.5) ; 13.2 (2.8) ; 1.1 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1595 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.6 (9.6) ; 10.3 (10.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1596 |
|
|
; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 12.2 (2.2) ; 12.2 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1597 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1598 |
|
|
; |altera_merlin_slave_agent:data_info_s1_agent| ; 11.7 (2.2) ; 12.6 (2.4) ; 0.9 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1599 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 10.2 (10.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1600 |
|
|
; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.3 (5.5) ; 17.5 (6.3) ; 2.2 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1601 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 11.2 (11.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1602 |
|
|
; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 11.8 (2.3) ; 11.8 (2.3) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1603 |
35 |
redbear |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1604 |
40 |
redbear |
; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.7 (2.5) ; 13.8 (2.7) ; 1.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1605 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 11.2 (11.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1606 |
|
|
; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 12.1 (2.2) ; 12.1 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1607 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1608 |
|
|
; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 12.1 (2.1) ; 12.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1609 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1610 |
|
|
; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 11.8 (2.2) ; 12.0 (2.3) ; 0.2 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1611 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.7 (9.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1612 |
|
|
; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 14.9 (4.8) ; 16.6 (5.8) ; 1.7 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1613 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.8 (10.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1614 |
|
|
; |altera_merlin_slave_agent:link_disable_s1_agent| ; 14.9 (5.4) ; 16.0 (6.8) ; 1.1 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1615 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1616 |
|
|
; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.2 (5.6) ; 15.5 (5.8) ; 0.3 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1617 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1618 |
|
|
; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 11.6 (2.2) ; 11.7 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1619 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.5 (9.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1620 |
|
|
; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 11.9 (2.2) ; 12.4 (2.5) ; 0.5 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1621 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.9 (9.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1622 |
|
|
; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 15.5 (5.3) ; 15.8 (5.6) ; 0.2 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1623 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.2 (10.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1624 |
|
|
; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 15.1 (5.4) ; 15.7 (5.8) ; 0.6 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1625 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1626 |
|
|
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.1 (2.5) ; 12.1 (2.8) ; 0.0 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1627 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1628 |
|
|
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.5 (5.4) ; 15.5 (5.5) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1629 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1630 |
|
|
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 14.5 (5.2) ; 14.5 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
| 1631 |
|
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
| 1632 |
|
|
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.1 (2.1) ; 3.3 (3.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1633 |
|
|
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 3.1 (3.1) ; 3.8 (3.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1634 |
|
|
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 2.6 (2.6) ; 3.4 (3.4) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1635 |
|
|
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1636 |
|
|
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 3.0 (3.0) ; 4.4 (4.4) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1637 |
|
|
; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1638 |
|
|
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1639 |
|
|
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1640 |
|
|
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 1.2 (1.2) ; 2.1 (2.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1641 |
|
|
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 1.1 (1.1) ; 1.9 (1.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1642 |
|
|
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.4 (1.4) ; 2.1 (2.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1643 |
|
|
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.9 (1.9) ; 2.5 (2.5) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1644 |
|
|
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.6 (3.6) ; 3.8 (3.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1645 |
|
|
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.5 (2.5) ; 2.8 (2.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1646 |
|
|
; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.3 (2.3) ; 3.0 (3.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1647 |
|
|
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 1.7 (1.7) ; 2.0 (2.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1648 |
|
|
; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.4 (2.4) ; 5.0 (5.0) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1649 |
|
|
; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 3.5 (3.5) ; 4.5 (4.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1650 |
|
|
; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 2.2 (2.2) ; 2.9 (2.9) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1651 |
|
|
; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 1.0 (1.0) ; 1.6 (1.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1652 |
|
|
; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.2 (4.2) ; 5.1 (5.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1653 |
|
|
; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.3 (2.3) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
| 1654 |
|
|
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 15.3 (15.3) ; 15.3 (15.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
|
| 1655 |
|
|
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 14.4 (14.4) ; 14.4 (14.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
|
| 1656 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 18.4 (18.4) ; 20.1 (20.1) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (35) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
|
| 1657 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 31.6 (31.6) ; 31.6 (31.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
|
| 1658 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 11.7 (9.8) ; 12.5 (10.5) ; 0.8 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (32) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1659 |
|
|
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 2.0 (2.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1660 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 7.0 (7.0) ; 8.1 (8.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1661 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 7.0 (7.0) ; 8.2 (8.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1662 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.7 (6.7) ; 7.8 (7.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1663 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 11.1 (9.6) ; 12.2 (10.7) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1664 |
|
|
; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1665 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.8 (6.8) ; 7.2 (7.2) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1666 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 7.1 (7.1) ; 8.0 (8.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1667 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 12.3 (10.3) ; 12.7 (10.8) ; 0.3 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1668 |
|
|
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1669 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 12.0 (9.8) ; 11.9 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1670 |
|
|
; |altera_merlin_arbitrator:arb| ; 1.9 (1.9) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1671 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 11.5 (9.7) ; 12.4 (10.6) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1672 |
|
|
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1673 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.5 (12.5) ; 14.5 (12.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1674 |
|
|
; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1675 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 11.6 (9.6) ; 12.8 (10.5) ; 1.3 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1676 |
|
|
; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.3 (2.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1677 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.6 (6.6) ; 6.6 (6.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1678 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1679 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 12.6 (10.8) ; 14.0 (12.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (35) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1680 |
|
|
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1681 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 10.6 (8.6) ; 12.1 (10.1) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1682 |
|
|
; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1683 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1684 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1685 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 11.4 (9.9) ; 13.2 (10.7) ; 1.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1686 |
|
|
; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 2.5 (2.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
|
| 1687 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1688 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 6.7 (6.7) ; 7.1 (7.1) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1689 |
|
|
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
|
| 1690 |
|
|
; |ulight_fifo_mm_interconnect_0_router:router| ; 10.2 (10.2) ; 13.2 (13.2) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
| 1691 |
|
|
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 16.0 (16.0) ; 18.3 (18.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
| 1692 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1693 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1694 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1695 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.1 (1.1) ; 1.2 (1.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1696 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1697 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1698 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1699 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.4 (1.4) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1700 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1701 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 0.8 (0.8) ; 0.9 (0.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
| 1702 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 37.3 (37.3) ; 36.9 (36.9) ; 0.3 (0.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
| 1703 |
|
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 127.2 (127.2) ; 135.9 (135.9) ; 10.3 (10.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 294 (294) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
| 1704 |
32 |
redbear |
; |ulight_fifo_pll_0:pll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ;
|
| 1705 |
|
|
; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ;
|
| 1706 |
|
|
; |altera_cyclonev_pll:cyclonev_pll| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ;
|
| 1707 |
|
|
; |altera_cyclonev_pll_base:fpll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ;
|
| 1708 |
40 |
redbear |
; |ulight_fifo_timecode_rx:timecode_rx| ; 2.8 (2.8) ; 3.3 (3.3) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ;
|
| 1709 |
|
|
; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 3.3 (3.3) ; 6.0 (6.0) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ;
|
| 1710 |
|
|
; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.5 (2.5) ; 7.6 (7.6) ; 5.1 (5.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ;
|
| 1711 |
32 |
redbear |
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
| 1712 |
|
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
| 1713 |
|
|
|
| 1714 |
|
|
|
| 1715 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
| 1716 |
|
|
; Delay Chain Summary ;
|
| 1717 |
|
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
| 1718 |
|
|
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
| 1719 |
|
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
| 1720 |
40 |
redbear |
; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
| 1721 |
|
|
; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
| 1722 |
|
|
; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
| 1723 |
|
|
; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
| 1724 |
|
|
; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
| 1725 |
|
|
; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
| 1726 |
|
|
; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
| 1727 |
|
|
; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
| 1728 |
|
|
; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
| 1729 |
32 |
redbear |
; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
| 1730 |
40 |
redbear |
; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
| 1731 |
32 |
redbear |
; FPGA_CLK1_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
| 1732 |
|
|
; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
| 1733 |
35 |
redbear |
; din_a ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
| 1734 |
32 |
redbear |
; sin_a ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
| 1735 |
|
|
; dout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
| 1736 |
|
|
; sout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
| 1737 |
35 |
redbear |
; din_a(n) ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
| 1738 |
32 |
redbear |
; sin_a(n) ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
| 1739 |
|
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
| 1740 |
|
|
|
| 1741 |
|
|
|
| 1742 |
40 |
redbear |
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1743 |
|
|
; Pad To Core Delay Chain Fanout ;
|
| 1744 |
|
|
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+
|
| 1745 |
|
|
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
| 1746 |
|
|
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+
|
| 1747 |
|
|
; KEY[0] ; ; ;
|
| 1748 |
|
|
; FPGA_CLK1_50 ; ; ;
|
| 1749 |
|
|
; KEY[1] ; ; ;
|
| 1750 |
|
|
; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ;
|
| 1751 |
|
|
; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ;
|
| 1752 |
|
|
; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ;
|
| 1753 |
|
|
; - debounce_db:db_system_spwulight_b|counter~1 ; 0 ; 0 ;
|
| 1754 |
|
|
; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ;
|
| 1755 |
|
|
; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ;
|
| 1756 |
|
|
; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ;
|
| 1757 |
|
|
; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ;
|
| 1758 |
|
|
; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ;
|
| 1759 |
|
|
; - debounce_db:db_system_spwulight_b|counter~7 ; 0 ; 0 ;
|
| 1760 |
|
|
; - debounce_db:db_system_spwulight_b|counter~8 ; 0 ; 0 ;
|
| 1761 |
|
|
; - debounce_db:db_system_spwulight_b|counter~9 ; 0 ; 0 ;
|
| 1762 |
|
|
; - debounce_db:db_system_spwulight_b|counter~10 ; 0 ; 0 ;
|
| 1763 |
|
|
; - debounce_db:db_system_spwulight_b|counter~11 ; 0 ; 0 ;
|
| 1764 |
|
|
; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ;
|
| 1765 |
|
|
; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ;
|
| 1766 |
|
|
; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ;
|
| 1767 |
|
|
; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ;
|
| 1768 |
|
|
; din_a ; ; ;
|
| 1769 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ;
|
| 1770 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
| 1771 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ;
|
| 1772 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ;
|
| 1773 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ;
|
| 1774 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ;
|
| 1775 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ;
|
| 1776 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ;
|
| 1777 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ;
|
| 1778 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ;
|
| 1779 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ;
|
| 1780 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ;
|
| 1781 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ;
|
| 1782 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ;
|
| 1783 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ;
|
| 1784 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ;
|
| 1785 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ;
|
| 1786 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ;
|
| 1787 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ;
|
| 1788 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ;
|
| 1789 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ;
|
| 1790 |
|
|
; sin_a ; ; ;
|
| 1791 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ;
|
| 1792 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
| 1793 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ;
|
| 1794 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ;
|
| 1795 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ;
|
| 1796 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ;
|
| 1797 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ;
|
| 1798 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ;
|
| 1799 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ;
|
| 1800 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ;
|
| 1801 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ;
|
| 1802 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ;
|
| 1803 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ;
|
| 1804 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ;
|
| 1805 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ;
|
| 1806 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ;
|
| 1807 |
|
|
; din_a(n) ; ; ;
|
| 1808 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ;
|
| 1809 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
| 1810 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ;
|
| 1811 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ;
|
| 1812 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ;
|
| 1813 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ;
|
| 1814 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ;
|
| 1815 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ;
|
| 1816 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ;
|
| 1817 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ;
|
| 1818 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ;
|
| 1819 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ;
|
| 1820 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ;
|
| 1821 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ;
|
| 1822 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ;
|
| 1823 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ;
|
| 1824 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ;
|
| 1825 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ;
|
| 1826 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ;
|
| 1827 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ;
|
| 1828 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ;
|
| 1829 |
|
|
; sin_a(n) ; ; ;
|
| 1830 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ;
|
| 1831 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
| 1832 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ;
|
| 1833 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ;
|
| 1834 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ;
|
| 1835 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ;
|
| 1836 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ;
|
| 1837 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ;
|
| 1838 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ;
|
| 1839 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ;
|
| 1840 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ;
|
| 1841 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ;
|
| 1842 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ;
|
| 1843 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ;
|
| 1844 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ;
|
| 1845 |
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ;
|
| 1846 |
|
|
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+
|
| 1847 |
32 |
redbear |
|
| 1848 |
|
|
|
| 1849 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1850 |
|
|
; Control Signals ;
|
| 1851 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
| 1852 |
|
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
| 1853 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
| 1854 |
40 |
redbear |
; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
|
| 1855 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X48_Y7_N35 ; 1319 ; Clock ; no ; -- ; -- ; -- ;
|
| 1856 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X61_Y4_N41 ; 105 ; Clock ; no ; -- ; -- ; -- ;
|
| 1857 |
|
|
; debounce_db:db_system_spwulight_b|aux_pb ; FF_X56_Y3_N59 ; 72 ; Async. clear ; no ; -- ; -- ; -- ;
|
| 1858 |
|
|
; detector_tokens:m_x|always5~1 ; LABCELL_X53_Y3_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1859 |
|
|
; detector_tokens:m_x|comb ; LABCELL_X53_Y3_N27 ; 21 ; Clock ; no ; -- ; -- ; -- ;
|
| 1860 |
|
|
; detector_tokens:m_x|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X51_Y3_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1861 |
|
|
; detector_tokens:m_x|negedge_clk ; LABCELL_X53_Y3_N39 ; 18 ; Clock ; no ; -- ; -- ; -- ;
|
| 1862 |
|
|
; detector_tokens:m_x|state_data_process.01 ; FF_X53_Y3_N11 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1863 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always5~0 ; LABCELL_X48_Y10_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1864 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; LABCELL_X51_Y9_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1865 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; LABCELL_X58_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1866 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; LABCELL_X53_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1867 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X53_Y11_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1868 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; LABCELL_X58_Y9_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1869 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; LABCELL_X53_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1870 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; LABCELL_X53_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1871 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; LABCELL_X53_Y11_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1872 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X58_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1873 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X56_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1874 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X50_Y8_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1875 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X54_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1876 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; LABCELL_X51_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1877 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; LABCELL_X58_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1878 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; MLABCELL_X50_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1879 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; MLABCELL_X50_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1880 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X54_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1881 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X53_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1882 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; LABCELL_X51_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1883 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; MLABCELL_X50_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1884 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X50_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1885 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X51_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1886 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X51_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1887 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X58_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1888 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; LABCELL_X51_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1889 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X51_Y9_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1890 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; LABCELL_X51_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1891 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X58_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1892 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X50_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1893 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; LABCELL_X51_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1894 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; LABCELL_X58_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1895 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; LABCELL_X58_Y9_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1896 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X50_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1897 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X56_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1898 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X56_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1899 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X58_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1900 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; LABCELL_X58_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1901 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; LABCELL_X56_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1902 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X58_Y9_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1903 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; LABCELL_X58_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1904 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; LABCELL_X58_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1905 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X50_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1906 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; LABCELL_X56_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1907 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X53_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1908 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X53_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1909 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X58_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1910 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X58_Y8_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1911 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X53_Y10_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1912 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; LABCELL_X54_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1913 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; LABCELL_X53_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1914 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X56_Y9_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1915 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X56_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1916 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; LABCELL_X51_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1917 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X53_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1918 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; MLABCELL_X50_Y10_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1919 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; MLABCELL_X50_Y10_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1920 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; MLABCELL_X50_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1921 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; LABCELL_X54_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1922 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; LABCELL_X54_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1923 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X58_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1924 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X53_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1925 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X58_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1926 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; LABCELL_X58_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1927 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; LABCELL_X51_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1928 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; MLABCELL_X42_Y5_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1929 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; MLABCELL_X42_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1930 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; MLABCELL_X42_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1931 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X40_Y8_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1932 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; MLABCELL_X42_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1933 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; MLABCELL_X42_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1934 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; MLABCELL_X42_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1935 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; MLABCELL_X42_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1936 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X41_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1937 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X41_Y6_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1938 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X42_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1939 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X41_Y6_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1940 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; MLABCELL_X42_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1941 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; MLABCELL_X42_Y5_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1942 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; LABCELL_X40_Y5_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1943 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; LABCELL_X41_Y5_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1944 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X40_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1945 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X40_Y5_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1946 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; MLABCELL_X42_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1947 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; LABCELL_X40_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1948 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X42_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1949 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X41_Y7_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1950 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X41_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1951 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X40_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1952 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; MLABCELL_X42_Y5_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1953 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X41_Y7_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1954 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; MLABCELL_X42_Y6_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1955 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X40_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1956 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X42_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1957 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; MLABCELL_X42_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1958 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; MLABCELL_X42_Y6_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1959 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; MLABCELL_X42_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1960 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X42_Y6_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1961 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X41_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1962 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X41_Y5_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1963 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X40_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1964 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; MLABCELL_X42_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1965 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; MLABCELL_X42_Y5_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1966 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X41_Y7_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1967 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; MLABCELL_X42_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1968 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; MLABCELL_X42_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1969 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X42_Y5_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1970 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; MLABCELL_X42_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1971 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X41_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1972 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X41_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1973 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X41_Y6_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1974 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X41_Y6_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1975 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X41_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1976 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; MLABCELL_X42_Y6_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1977 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; MLABCELL_X42_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1978 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X41_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1979 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X40_Y5_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1980 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; MLABCELL_X42_Y6_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1981 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X40_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1982 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; LABCELL_X41_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1983 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; LABCELL_X40_Y8_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1984 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; LABCELL_X40_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1985 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; MLABCELL_X42_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1986 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; MLABCELL_X42_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1987 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X40_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1988 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X41_Y7_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1989 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X40_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1990 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; MLABCELL_X42_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1991 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; MLABCELL_X42_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1992 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|next_state_data_read.11~0 ; LABCELL_X49_Y5_N48 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1993 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.10 ; FF_X41_Y9_N50 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1994 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X50_Y3_N32 ; 104 ; Async. clear ; no ; -- ; -- ; -- ;
|
| 1995 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X49_Y3_N44 ; 75 ; Async. clear ; no ; -- ; -- ; -- ;
|
| 1996 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; LABCELL_X54_Y5_N51 ; 60 ; Clock ; no ; -- ; -- ; -- ;
|
| 1997 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X53_Y6_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 1998 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|negedge_clk ; LABCELL_X53_Y6_N0 ; 17 ; Clock ; no ; -- ; -- ; -- ;
|
| 1999 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; LABCELL_X56_Y6_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2000 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; LABCELL_X54_Y6_N27 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2001 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; LABCELL_X54_Y6_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2002 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; FF_X53_Y6_N44 ; 26 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2003 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X48_Y5_N12 ; 1260 ; Async. clear ; no ; -- ; -- ; -- ;
|
| 2004 |
|
|
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X22_Y29_N56 ; 74 ; Async. clear ; no ; -- ; -- ; -- ;
|
| 2005 |
|
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X61_Y6_N44 ; 2974 ; Async. clear ; no ; -- ; -- ; -- ;
|
| 2006 |
|
|
; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; LABCELL_X17_Y18_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2007 |
|
|
; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; LABCELL_X17_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2008 |
|
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X17_Y19_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2009 |
|
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; MLABCELL_X14_Y15_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2010 |
|
|
; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; MLABCELL_X14_Y22_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2011 |
|
|
; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; LABCELL_X21_Y27_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2012 |
|
|
; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; LABCELL_X21_Y25_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2013 |
|
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ;
|
| 2014 |
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X33_Y16_N48 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2015 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y18_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2016 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y18_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2017 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y25_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2018 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y25_N36 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2019 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X42_Y11_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2020 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y12_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2021 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y11_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2022 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y12_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2023 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2024 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y13_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2025 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X40_Y10_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2026 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y10_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2027 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2028 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y14_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2029 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y12_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2030 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y12_N39 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2031 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y9_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2032 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y9_N0 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2033 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y10_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2034 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y10_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2035 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X18_Y10_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2036 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y10_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2037 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y15_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2038 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X40_Y15_N6 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2039 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X35_Y15_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2040 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X33_Y16_N51 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2041 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y19_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2042 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y19_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2043 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X11_Y15_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2044 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X11_Y15_N21 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2045 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X31_Y11_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2046 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X32_Y11_N51 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2047 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2048 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y9_N27 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2049 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y27_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2050 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X27_Y27_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2051 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y23_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2052 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y22_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2053 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X25_Y8_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2054 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y8_N42 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2055 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X28_Y19_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2056 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y19_N30 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2057 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y27_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2058 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y27_N24 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2059 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y20_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2060 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y18_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2061 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y24_N27 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2062 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y25_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2063 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y13_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2064 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X37_Y13_N36 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2065 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X41_Y12_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2066 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X41_Y12_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2067 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y14_N45 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2068 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y14_N42 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2069 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2070 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y10_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2071 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y16_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2072 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y14_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2073 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y13_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2074 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X14_Y13_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2075 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y11_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2076 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y11_N57 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2077 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y9_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2078 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y9_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2079 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y11_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2080 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y11_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2081 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X38_Y15_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2082 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y15_N54 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2083 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X30_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2084 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X32_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2085 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y18_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2086 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y19_N0 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2087 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y16_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2088 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X11_Y16_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2089 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y9_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2090 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y9_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2091 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X33_Y12_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2092 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y9_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2093 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y26_N24 ; 37 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2094 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y26_N36 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2095 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y23_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2096 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y23_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2097 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y12_N33 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2098 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y12_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2099 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y20_N18 ; 38 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2100 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y20_N30 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2101 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y28_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2102 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y27_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2103 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y18_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2104 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y25_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2105 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X37_Y12_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2106 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y12_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2107 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X42_Y13_N3 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2108 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X40_Y10_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2109 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y14_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2110 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y12_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2111 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y9_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2112 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y10_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2113 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y10_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2114 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y15_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2115 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X35_Y16_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2116 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X25_Y19_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2117 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X11_Y15_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2118 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X32_Y11_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2119 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X38_Y9_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2120 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y27_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2121 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y22_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2122 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y8_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2123 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y19_N45 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2124 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y27_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2125 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|always1~0 ; LABCELL_X21_Y20_N27 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2126 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; LABCELL_X23_Y16_N36 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2127 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|always1~0 ; MLABCELL_X25_Y24_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2128 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X22_Y24_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2129 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; MLABCELL_X25_Y24_N33 ; 26 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2130 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; LABCELL_X33_Y12_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2131 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; LABCELL_X31_Y9_N9 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2132 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; MLABCELL_X37_Y14_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2133 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; MLABCELL_X19_Y16_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2134 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; LABCELL_X22_Y9_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2135 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; LABCELL_X15_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2136 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; LABCELL_X21_Y16_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2137 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X15_Y20_N51 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2138 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; MLABCELL_X19_Y18_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2139 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X22_Y20_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2140 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X23_Y28_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2141 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; MLABCELL_X19_Y11_N39 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2142 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; LABCELL_X22_Y11_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2143 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; LABCELL_X23_Y26_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2144 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; LABCELL_X18_Y23_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2145 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; LABCELL_X27_Y12_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2146 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; LABCELL_X31_Y11_N18 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2147 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X21_Y24_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2148 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X38_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2149 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X41_Y12_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2150 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X38_Y13_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2151 |
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; LABCELL_X30_Y16_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2152 |
|
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK8 ; -- ;
|
| 2153 |
|
|
; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X30_Y25_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2154 |
|
|
; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X30_Y19_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
| 2155 |
32 |
redbear |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
| 2156 |
|
|
|
| 2157 |
|
|
|
| 2158 |
40 |
redbear |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 2159 |
|
|
; Global & Other Fast Signals ;
|
| 2160 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
| 2161 |
|
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
| 2162 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
| 2163 |
|
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Global Clock ; GCLK4 ; -- ;
|
| 2164 |
|
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK11 ; -- ;
|
| 2165 |
|
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fboutclk_wire[0] ; FRACTIONALPLL_X68_Y1_N0 ; 1 ; Global Clock ; -- ; -- ;
|
| 2166 |
|
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Global Clock ; GCLK8 ; -- ;
|
| 2167 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
| 2168 |
32 |
redbear |
|
| 2169 |
|
|
|
| 2170 |
40 |
redbear |
+----------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 2171 |
|
|
; Non-Global High Fan-Out Signals ;
|
| 2172 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
| 2173 |
|
|
; Name ; Fan-Out ;
|
| 2174 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
| 2175 |
|
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 2974 ;
|
| 2176 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1319 ;
|
| 2177 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; 1260 ;
|
| 2178 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
| 2179 |
32 |
redbear |
|
| 2180 |
|
|
|
| 2181 |
40 |
redbear |
+------------------------------------------------------------------------+
|
| 2182 |
|
|
; Routing Usage Summary ;
|
| 2183 |
|
|
+---------------------------------------------+--------------------------+
|
| 2184 |
|
|
; Routing Resource Type ; Usage ;
|
| 2185 |
|
|
+---------------------------------------------+--------------------------+
|
| 2186 |
|
|
; Block interconnects ; 10,851 / 130,276 ( 8 % ) ;
|
| 2187 |
|
|
; C12 interconnects ; 122 / 6,848 ( 2 % ) ;
|
| 2188 |
|
|
; C2 interconnects ; 2,619 / 51,436 ( 5 % ) ;
|
| 2189 |
|
|
; C4 interconnects ; 1,582 / 25,120 ( 6 % ) ;
|
| 2190 |
|
|
; DQS bus muxes ; 0 / 19 ( 0 % ) ;
|
| 2191 |
|
|
; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ;
|
| 2192 |
|
|
; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ;
|
| 2193 |
|
|
; Direct links ; 1,438 / 130,276 ( 1 % ) ;
|
| 2194 |
|
|
; Global clocks ; 3 / 16 ( 19 % ) ;
|
| 2195 |
|
|
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
|
| 2196 |
|
|
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
|
| 2197 |
|
|
; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
|
| 2198 |
|
|
; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
|
| 2199 |
|
|
; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 1 / 6 ( 17 % ) ;
|
| 2200 |
|
|
; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
|
| 2201 |
|
|
; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
|
| 2202 |
|
|
; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
|
| 2203 |
|
|
; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
|
| 2204 |
|
|
; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
|
| 2205 |
|
|
; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
|
| 2206 |
|
|
; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
|
| 2207 |
|
|
; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
|
| 2208 |
|
|
; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
|
| 2209 |
|
|
; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
|
| 2210 |
|
|
; HPS_INTERFACE_HPS2FPGA_INPUTs ; 40 / 165 ( 24 % ) ;
|
| 2211 |
|
|
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
|
| 2212 |
|
|
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
|
| 2213 |
|
|
; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 101 / 282 ( 36 % ) ;
|
| 2214 |
|
|
; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
|
| 2215 |
|
|
; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
|
| 2216 |
|
|
; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
|
| 2217 |
|
|
; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
|
| 2218 |
|
|
; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
|
| 2219 |
|
|
; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
|
| 2220 |
|
|
; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
|
| 2221 |
|
|
; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
|
| 2222 |
|
|
; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
|
| 2223 |
|
|
; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
|
| 2224 |
|
|
; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
|
| 2225 |
|
|
; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
|
| 2226 |
|
|
; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
|
| 2227 |
|
|
; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
|
| 2228 |
|
|
; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
|
| 2229 |
|
|
; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
|
| 2230 |
|
|
; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
|
| 2231 |
|
|
; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
|
| 2232 |
|
|
; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
|
| 2233 |
|
|
; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
|
| 2234 |
|
|
; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
|
| 2235 |
|
|
; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
|
| 2236 |
|
|
; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
|
| 2237 |
|
|
; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
|
| 2238 |
|
|
; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
|
| 2239 |
|
|
; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
|
| 2240 |
|
|
; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
|
| 2241 |
|
|
; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
|
| 2242 |
|
|
; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
|
| 2243 |
|
|
; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
|
| 2244 |
|
|
; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
|
| 2245 |
|
|
; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
|
| 2246 |
|
|
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
|
| 2247 |
|
|
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
|
| 2248 |
|
|
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
| 2249 |
|
|
; Local interconnects ; 3,340 / 31,760 ( 11 % ) ;
|
| 2250 |
|
|
; Quadrant clocks ; 0 / 72 ( 0 % ) ;
|
| 2251 |
|
|
; R14 interconnects ; 250 / 6,046 ( 4 % ) ;
|
| 2252 |
|
|
; R14/C12 interconnect drivers ; 333 / 8,584 ( 4 % ) ;
|
| 2253 |
|
|
; R3 interconnects ; 4,393 / 56,712 ( 8 % ) ;
|
| 2254 |
|
|
; R6 interconnects ; 6,014 / 131,000 ( 5 % ) ;
|
| 2255 |
|
|
; Spine clocks ; 6 / 150 ( 4 % ) ;
|
| 2256 |
|
|
; Wire stub REs ; 0 / 6,650 ( 0 % ) ;
|
| 2257 |
|
|
+---------------------------------------------+--------------------------+
|
| 2258 |
32 |
redbear |
|
| 2259 |
|
|
|
| 2260 |
|
|
+------------------------------------------+
|
| 2261 |
|
|
; I/O Rules Summary ;
|
| 2262 |
|
|
+----------------------------------+-------+
|
| 2263 |
|
|
; I/O Rules Statistic ; Total ;
|
| 2264 |
|
|
+----------------------------------+-------+
|
| 2265 |
|
|
; Total I/O Rules ; 28 ;
|
| 2266 |
40 |
redbear |
; Number of I/O Rules Passed ; 8 ;
|
| 2267 |
32 |
redbear |
; Number of I/O Rules Failed ; 0 ;
|
| 2268 |
|
|
; Number of I/O Rules Unchecked ; 0 ;
|
| 2269 |
40 |
redbear |
; Number of I/O Rules Inapplicable ; 20 ;
|
| 2270 |
32 |
redbear |
+----------------------------------+-------+
|
| 2271 |
|
|
|
| 2272 |
|
|
|
| 2273 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 2274 |
|
|
; I/O Rules Details ;
|
| 2275 |
|
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+
|
| 2276 |
|
|
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
|
| 2277 |
|
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+
|
| 2278 |
40 |
redbear |
; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ;
|
| 2279 |
32 |
redbear |
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
| 2280 |
|
|
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
| 2281 |
|
|
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
|
| 2282 |
|
|
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
|
| 2283 |
|
|
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
|
| 2284 |
|
|
; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
|
| 2285 |
|
|
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
|
| 2286 |
|
|
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
| 2287 |
|
|
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
| 2288 |
|
|
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
| 2289 |
|
|
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
|
| 2290 |
|
|
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
|
| 2291 |
|
|
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
|
| 2292 |
|
|
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
| 2293 |
|
|
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
| 2294 |
|
|
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
| 2295 |
|
|
; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
|
| 2296 |
|
|
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
|
| 2297 |
|
|
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
| 2298 |
|
|
; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
|
| 2299 |
|
|
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
| 2300 |
|
|
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
| 2301 |
|
|
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
|
| 2302 |
|
|
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
| 2303 |
|
|
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
|
| 2304 |
|
|
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
|
| 2305 |
|
|
; Pass ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; 0 such failures found. ; I/O ; ;
|
| 2306 |
|
|
; ---- ; ---- ; Disclaimer ; LVDS rules are checked but not reported. ; None ; ---- ; Differential Signaling ; ;
|
| 2307 |
|
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+
|
| 2308 |
|
|
|
| 2309 |
|
|
|
| 2310 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 2311 |
|
|
; I/O Rules Matrix ;
|
| 2312 |
|
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
| 2313 |
|
|
; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
| 2314 |
|
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
| 2315 |
40 |
redbear |
; Total Pass ; 5 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ;
|
| 2316 |
32 |
redbear |
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
| 2317 |
40 |
redbear |
; Total Inapplicable ; 14 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ;
|
| 2318 |
32 |
redbear |
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
| 2319 |
40 |
redbear |
; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2320 |
|
|
; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2321 |
35 |
redbear |
; dout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2322 |
|
|
; sout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2323 |
40 |
redbear |
; LED[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2324 |
|
|
; LED[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2325 |
|
|
; LED[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2326 |
|
|
; LED[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2327 |
|
|
; LED[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2328 |
32 |
redbear |
; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
| 2329 |
|
|
; LED[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2330 |
|
|
; FPGA_CLK1_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
| 2331 |
|
|
; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
| 2332 |
|
|
; din_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2333 |
|
|
; sin_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2334 |
|
|
; dout_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2335 |
|
|
; sout_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2336 |
|
|
; din_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2337 |
|
|
; sin_a(n) ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| 2338 |
|
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
| 2339 |
|
|
|
| 2340 |
|
|
|
| 2341 |
|
|
+------------------------------------------------------------------------------------------------+
|
| 2342 |
|
|
; Fitter Device Options ;
|
| 2343 |
|
|
+------------------------------------------------------------------+-----------------------------+
|
| 2344 |
|
|
; Option ; Setting ;
|
| 2345 |
|
|
+------------------------------------------------------------------+-----------------------------+
|
| 2346 |
|
|
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
|
| 2347 |
|
|
; Enable device-wide reset (DEV_CLRn) ; Off ;
|
| 2348 |
|
|
; Enable device-wide output enable (DEV_OE) ; Off ;
|
| 2349 |
|
|
; Enable INIT_DONE output ; Off ;
|
| 2350 |
|
|
; Configuration scheme ; Passive Serial ;
|
| 2351 |
|
|
; Enable Error Detection CRC_ERROR pin ; Off ;
|
| 2352 |
|
|
; Enable CvP_CONFDONE pin ; Off ;
|
| 2353 |
|
|
; Enable open drain on CRC_ERROR pin ; On ;
|
| 2354 |
|
|
; Enable open drain on CvP_CONFDONE pin ; On ;
|
| 2355 |
|
|
; Enable open drain on INIT_DONE pin ; On ;
|
| 2356 |
|
|
; Enable open drain on Partial Reconfiguration pins ; Off ;
|
| 2357 |
|
|
; Enable open drain on nCEO pin ; On ;
|
| 2358 |
|
|
; Enable Partial Reconfiguration pins ; Off ;
|
| 2359 |
|
|
; Enable input tri-state on active configuration pins in user mode ; Off ;
|
| 2360 |
|
|
; Enable internal scrubbing ; Off ;
|
| 2361 |
|
|
; Active Serial clock source ; 100 MHz Internal Oscillator ;
|
| 2362 |
|
|
; Device initialization clock source ; Internal Oscillator ;
|
| 2363 |
|
|
; Configuration via Protocol ; Off ;
|
| 2364 |
|
|
; Configuration Voltage Level ; Auto ;
|
| 2365 |
|
|
; Force Configuration Voltage Level ; Off ;
|
| 2366 |
|
|
; Enable nCEO output ; Off ;
|
| 2367 |
|
|
; Data[15..8] ; Unreserved ;
|
| 2368 |
|
|
; Data[7..5] ; Unreserved ;
|
| 2369 |
|
|
; Base pin-out file on sameframe device ; Off ;
|
| 2370 |
|
|
+------------------------------------------------------------------+-----------------------------+
|
| 2371 |
|
|
|
| 2372 |
|
|
|
| 2373 |
|
|
+------------------------------------+
|
| 2374 |
|
|
; Operating Settings and Conditions ;
|
| 2375 |
|
|
+---------------------------+--------+
|
| 2376 |
|
|
; Setting ; Value ;
|
| 2377 |
|
|
+---------------------------+--------+
|
| 2378 |
|
|
; Nominal Core Voltage ; 1.10 V ;
|
| 2379 |
|
|
; Low Junction Temperature ; 0 °C ;
|
| 2380 |
|
|
; High Junction Temperature ; 85 °C ;
|
| 2381 |
|
|
+---------------------------+--------+
|
| 2382 |
|
|
|
| 2383 |
|
|
|
| 2384 |
40 |
redbear |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 2385 |
|
|
; Estimated Delay Added for Hold Timing Summary ;
|
| 2386 |
|
|
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+
|
| 2387 |
|
|
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
| 2388 |
|
|
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+
|
| 2389 |
|
|
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 603.1 ;
|
| 2390 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 152.8 ;
|
| 2391 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 85.5 ;
|
| 2392 |
|
|
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 83.9 ;
|
| 2393 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 65.3 ;
|
| 2394 |
|
|
; din_a ; din_a ; 47.9 ;
|
| 2395 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 39.2 ;
|
| 2396 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 31.9 ;
|
| 2397 |
|
|
; I/O ; din_a ; 25.0 ;
|
| 2398 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 23.3 ;
|
| 2399 |
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i,clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 23.3 ;
|
| 2400 |
|
|
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+
|
| 2401 |
32 |
redbear |
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
| 2402 |
|
|
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
|
| 2403 |
|
|
|
| 2404 |
|
|
|
| 2405 |
40 |
redbear |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 2406 |
|
|
; Estimated Delay Added for Hold Timing Details ;
|
| 2407 |
|
|
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
| 2408 |
|
|
; Source Register ; Destination Register ; Delay Added in ns ;
|
| 2409 |
|
|
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
| 2410 |
|
|
; din_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 4.535 ;
|
| 2411 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; detector_tokens:m_x|bit_capture_data:capture_d|bit_d_0 ; 4.290 ;
|
| 2412 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[1] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[1] ; 2.916 ;
|
| 2413 |
|
|
; sin_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; 2.828 ;
|
| 2414 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[4] ; 2.799 ;
|
| 2415 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[7] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[7] ; 2.654 ;
|
| 2416 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[3] ; 2.645 ;
|
| 2417 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[0] ; 2.639 ;
|
| 2418 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[1] ; 2.638 ;
|
| 2419 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[2] ; 2.608 ;
|
| 2420 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[5] ; 2.608 ;
|
| 2421 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[3] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[3] ; 2.546 ;
|
| 2422 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[5] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[5] ; 2.540 ;
|
| 2423 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_sout_e ; detector_tokens:m_x|info[4] ; 2.341 ;
|
| 2424 |
|
|
; detector_tokens:m_x|info[5] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[5] ; 2.334 ;
|
| 2425 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.run ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[4] ; 2.323 ;
|
| 2426 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.ready ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[1] ; 2.323 ;
|
| 2427 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_wait ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[0] ; 2.310 ;
|
| 2428 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[4] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[4] ; 2.289 ;
|
| 2429 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[2] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[2] ; 2.289 ;
|
| 2430 |
|
|
; detector_tokens:m_x|info[2] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[2] ; 2.265 ;
|
| 2431 |
|
|
; detector_tokens:m_x|info[4] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[4] ; 2.253 ;
|
| 2432 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[8] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[8] ; 2.240 ;
|
| 2433 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[0] ; 2.076 ;
|
| 2434 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[0] ; 2.018 ;
|
| 2435 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.started ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[2] ; 2.009 ;
|
| 2436 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|open_slot_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.001 ; 2.008 ;
|
| 2437 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[6] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[6] ; 2.007 ;
|
| 2438 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[3] ; 2.001 ;
|
| 2439 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[1] ; 1.991 ;
|
| 2440 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[2] ; 1.983 ;
|
| 2441 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[3] ; 1.970 ;
|
| 2442 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[0] ; 1.934 ;
|
| 2443 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|send_null_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.862 ;
|
| 2444 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[4] ; 1.857 ;
|
| 2445 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[5] ; 1.839 ;
|
| 2446 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.702 ;
|
| 2447 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.687 ;
|
| 2448 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_timecode ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[0] ; 1.682 ;
|
| 2449 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[0] ; 1.670 ;
|
| 2450 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.599 ;
|
| 2451 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_got_fct_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; 1.540 ;
|
| 2452 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c_0 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.518 ;
|
| 2453 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2454 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2455 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2456 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2457 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2458 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2459 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2460 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2461 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2462 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2463 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_timec ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2464 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|data_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2465 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|eop_eep_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2466 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|fct_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2467 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|null_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2468 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2469 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2470 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2471 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2472 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2473 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2474 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2475 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2476 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2477 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2478 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2479 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2480 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2481 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2482 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2483 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2484 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_time_code_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2485 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2486 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2487 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2488 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2489 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_start ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2490 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2491 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2492 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2493 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2494 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
| 2495 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[0] ; 1.346 ;
|
| 2496 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[0] ; 1.343 ;
|
| 2497 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.343 ;
|
| 2498 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.318 ;
|
| 2499 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; 1.260 ;
|
| 2500 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|overflow_credit_error ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_credit_error_b ; 1.259 ;
|
| 2501 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|write_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|process_data ; 1.258 ;
|
| 2502 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_data ; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read~5 ; 1.255 ;
|
| 2503 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.249 ;
|
| 2504 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.238 ;
|
| 2505 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[10] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.230 ;
|
| 2506 |
|
|
; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[5] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.228 ;
|
| 2507 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.215 ;
|
| 2508 |
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.169 ;
|
| 2509 |
|
|
; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[3] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.153 ;
|
| 2510 |
|
|
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
| 2511 |
32 |
redbear |
Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
|
| 2512 |
|
|
|
| 2513 |
|
|
|
| 2514 |
|
|
+-----------------+
|
| 2515 |
|
|
; Fitter Messages ;
|
| 2516 |
|
|
+-----------------+
|
| 2517 |
40 |
redbear |
Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time
|
| 2518 |
|
|
Info (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)
|
| 2519 |
|
|
Info (16304): Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)
|
| 2520 |
32 |
redbear |
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
| 2521 |
|
|
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
| 2522 |
|
|
Info (119006): Selected device 5CSEMA4U23C6 for design "spw_fifo_ulight"
|
| 2523 |
|
|
Info (21077): Low junction temperature is 0 degrees C
|
| 2524 |
|
|
Info (21077): High junction temperature is 85 degrees C
|
| 2525 |
|
|
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
| 2526 |
|
|
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
| 2527 |
|
|
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
| 2528 |
|
|
Info (184025): 4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins.
|
| 2529 |
|
|
Info (184026): differential I/O pin "dout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "dout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 9
|
| 2530 |
|
|
Info (184026): differential I/O pin "sout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 10
|
| 2531 |
|
|
Info (184026): differential I/O pin "din_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "din_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 5
|
| 2532 |
|
|
Info (184026): differential I/O pin "sin_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sin_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 6
|
| 2533 |
|
|
Info (184020): Starting Fitter periphery placement operations
|
| 2534 |
40 |
redbear |
Warning (177007): PLL(s) placed in location FRACTIONALPLL_X68_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
|
| 2535 |
|
|
Info (177008): PLL ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll
|
| 2536 |
32 |
redbear |
Info (11178): Promoted 2 clocks (2 global)
|
| 2537 |
40 |
redbear |
Info (11162): ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G11
|
| 2538 |
|
|
Info (11162): ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G8
|
| 2539 |
|
|
Info (11191): Automatically promoted 1 clock (1 global)
|
| 2540 |
|
|
Info (11162): FPGA_CLK1_50~inputCLKENA0 with 3068 fanout uses global clock CLKCTRL_G4
|
| 2541 |
32 |
redbear |
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
|
| 2542 |
|
|
Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'
|
| 2543 |
|
|
Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'
|
| 2544 |
|
|
Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.
|
| 2545 |
40 |
redbear |
Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataa to: combout
|
| 2546 |
|
|
Info (332098): Cell: m_x|comb from: datab to: combout
|
| 2547 |
32 |
redbear |
Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457
|
| 2548 |
|
|
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk
|
| 2549 |
|
|
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout
|
| 2550 |
|
|
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk
|
| 2551 |
|
|
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
|
| 2552 |
|
|
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
|
| 2553 |
|
|
Info (332111): Found 7 clocks
|
| 2554 |
|
|
Info (332111): Period Clock Name
|
| 2555 |
|
|
Info (332111): ======== ============
|
| 2556 |
40 |
redbear |
Info (332111): 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i
|
| 2557 |
|
|
Info (332111): 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i
|
| 2558 |
|
|
Info (332111): 4.000 din_a
|
| 2559 |
|
|
Info (332111): 20.000 FPGA_CLK1_50
|
| 2560 |
|
|
Info (332111): 4.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e
|
| 2561 |
32 |
redbear |
Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
|
| 2562 |
|
|
Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
|
| 2563 |
|
|
Info (176233): Starting register packing
|
| 2564 |
40 |
redbear |
Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
|
| 2565 |
32 |
redbear |
Info (176235): Finished register packing
|
| 2566 |
40 |
redbear |
Extra Info (176218): Packed 5 registers into blocks of type I/O output buffer
|
| 2567 |
|
|
Extra Info (176220): Created 5 register duplicates
|
| 2568 |
32 |
redbear |
Info (223000): Starting Vectorless Power Activity Estimation
|
| 2569 |
|
|
Info (223001): Completed Vectorless Power Activity Estimation
|
| 2570 |
40 |
redbear |
Info (128000): Starting physical synthesis optimizations for speed
|
| 2571 |
|
|
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
|
| 2572 |
|
|
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 662 ps
|
| 2573 |
|
|
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
|
| 2574 |
|
|
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
|
| 2575 |
|
|
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:09
|
| 2576 |
|
|
Info (176233): Starting register packing
|
| 2577 |
|
|
Info (176235): Finished register packing
|
| 2578 |
|
|
Extra Info (176219): No registers were packed into other blocks
|
| 2579 |
|
|
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:30
|
| 2580 |
|
|
Warning (170136): Design uses Placement Effort Multiplier = 4.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt.
|
| 2581 |
32 |
redbear |
Info (170189): Fitter placement preparation operations beginning
|
| 2582 |
|
|
Info (223000): Starting Vectorless Power Activity Estimation
|
| 2583 |
|
|
Info (223001): Completed Vectorless Power Activity Estimation
|
| 2584 |
|
|
Info (14951): The Fitter is using Advanced Physical Optimization.
|
| 2585 |
40 |
redbear |
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:35
|
| 2586 |
35 |
redbear |
Info (223000): Starting Vectorless Power Activity Estimation
|
| 2587 |
|
|
Info (223001): Completed Vectorless Power Activity Estimation
|
| 2588 |
32 |
redbear |
Info (170191): Fitter placement operations beginning
|
| 2589 |
|
|
Info (170137): Fitter placement was successful
|
| 2590 |
40 |
redbear |
Info (170192): Fitter placement operations ending: elapsed time is 00:00:58
|
| 2591 |
32 |
redbear |
Info (170193): Fitter routing operations beginning
|
| 2592 |
|
|
Info (223000): Starting Vectorless Power Activity Estimation
|
| 2593 |
|
|
Info (223001): Completed Vectorless Power Activity Estimation
|
| 2594 |
40 |
redbear |
Info (170195): Router estimated average interconnect usage is 4% of the available device resources
|
| 2595 |
|
|
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11
|
| 2596 |
|
|
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
|
| 2597 |
|
|
Info (170194): Fitter routing operations ending: elapsed time is 00:01:16
|
| 2598 |
|
|
Info (11888): Total time spent on timing analysis during the Fitter is 27.50 seconds.
|
| 2599 |
|
|
Info (334003): Started post-fitting delay annotation
|
| 2600 |
|
|
Info (334004): Delay annotation completed successfully
|
| 2601 |
|
|
Info (334003): Started post-fitting delay annotation
|
| 2602 |
|
|
Info (334004): Delay annotation completed successfully
|
| 2603 |
|
|
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:38
|
| 2604 |
32 |
redbear |
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
| 2605 |
|
|
Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg
|
| 2606 |
40 |
redbear |
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
| 2607 |
|
|
Info: Peak virtual memory: 2473 megabytes
|
| 2608 |
|
|
Info: Processing ended: Mon Feb 5 00:57:20 2018
|
| 2609 |
|
|
Info: Elapsed time: 00:05:09
|
| 2610 |
|
|
Info: Total CPU time (on all processors): 00:08:50
|
| 2611 |
32 |
redbear |
|
| 2612 |
|
|
|
| 2613 |
|
|
+----------------------------+
|
| 2614 |
|
|
; Fitter Suppressed Messages ;
|
| 2615 |
|
|
+----------------------------+
|
| 2616 |
|
|
The suppressed messages can be found in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg.
|
| 2617 |
|
|
|
| 2618 |
|
|
|
