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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.map.summary] - Blame information for rev 40

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Analysis & Synthesis Status : Successful - Mon Feb  5 00:52:09 2018
Quartus Prime Version : 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
Revision Name : spw_fifo_ulight
Top-level Entity Name : SPW_ULIGHT_FIFO
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 4628
Total pins : 15
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 1
Total DLLs : 0

Line No.	Rev	Author	Line
1	40	redbear	`Analysis & Synthesis Status : Successful - Mon Feb 5 00:52:09 2018`
2			`Quartus Prime Version : 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition`
3	32	redbear	`Revision Name : spw_fifo_ulight`
4			`Top-level Entity Name : SPW_ULIGHT_FIFO`
5			`Family : Cyclone V`
6			`Logic utilization (in ALMs) : N/A`
7	40	redbear	`Total registers : 4628`
8	32	redbear	`Total pins : 15`
9			`Total virtual pins : 0`
10	35	redbear	`Total block memory bits : 0`
11	32	redbear	`Total DSP Blocks : 0`
12			`Total HSSI RX PCSs : 0`
13			`Total HSSI PMA RX Deserializers : 0`
14			`Total HSSI TX PCSs : 0`
15			`Total HSSI PMA TX Serializers : 0`
16			`Total PLLs : 1`
17			`Total DLLs : 0`

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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.map.summary] - Blame information for rev 40