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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.map.summary] - Blame information for rev 35

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Line No. Rev Author Line
1 35 redbear 
Analysis & Synthesis Status : Successful - Fri Sep 15 08:13:05 2017
2 32 redbear 
Quartus Prime Version : 17.0.1 Build 598 06/07/2017 SJ Lite Edition
3 
Revision Name : spw_fifo_ulight
4 
Top-level Entity Name : SPW_ULIGHT_FIFO
5 
Family : Cyclone V
6 
Logic utilization (in ALMs) : N/A
7 35 redbear 
Total registers : 4692
8 32 redbear 
Total pins : 15
9 
Total virtual pins : 0
10 35 redbear 
Total block memory bits : 0
11 32 redbear 
Total DSP Blocks : 0
12 
Total HSSI RX PCSs : 0
13 
Total HSSI PMA RX Deserializers : 0
14 
Total HSSI TX PCSs : 0
15 
Total HSSI PMA TX Serializers : 0
16 
Total PLLs : 1
17 
Total DLLs : 0

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