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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.sta.summary] - Blame information for rev 40

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------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
 
Type  : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -4.369
TNS   : -113.702
 
Type  : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -3.697
TNS   : -1112.931
 
Type  : Slow 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -3.138
TNS   : -13.527
 
Type  : Slow 1100mV 85C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -2.473
TNS   : -27.460
 
Type  : Slow 1100mV 85C Model Setup 'din_a'
Slack : -2.037
TNS   : -45.867
 
Type  : Slow 1100mV 85C Model Setup 'FPGA_CLK1_50'
Slack : -1.110
TNS   : -2.017
 
Type  : Slow 1100mV 85C Model Hold 'FPGA_CLK1_50'
Slack : 0.322
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.336
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.393
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.470
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Hold 'din_a'
Slack : 0.547
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.624
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -0.289
TNS   : -4.795
 
Type  : Slow 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 5.248
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Recovery 'FPGA_CLK1_50'
Slack : 14.466
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Removal 'FPGA_CLK1_50'
Slack : 0.563
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 1.308
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.746
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.533
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.575
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Minimum Pulse Width 'din_a'
Slack : 0.994
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.301
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 3.952
TNS   : 0.000
 
Type  : Slow 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.195
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -4.207
TNS   : -109.829
 
Type  : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -3.461
TNS   : -1038.103
 
Type  : Slow 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -2.976
TNS   : -12.650
 
Type  : Slow 1100mV 0C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -2.359
TNS   : -27.122
 
Type  : Slow 1100mV 0C Model Setup 'din_a'
Slack : -1.919
TNS   : -41.436
 
Type  : Slow 1100mV 0C Model Setup 'FPGA_CLK1_50'
Slack : -0.765
TNS   : -1.140
 
Type  : Slow 1100mV 0C Model Hold 'FPGA_CLK1_50'
Slack : 0.211
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.325
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.388
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.478
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Hold 'din_a'
Slack : 0.530
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.599
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -0.346
TNS   : -5.707
 
Type  : Slow 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 5.377
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Recovery 'FPGA_CLK1_50'
Slack : 14.772
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Removal 'FPGA_CLK1_50'
Slack : 0.464
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 1.288
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.777
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.499
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.523
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Minimum Pulse Width 'din_a'
Slack : 0.986
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.324
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 3.980
TNS   : 0.000
 
Type  : Slow 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.277
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -2.086
TNS   : -3.029
 
Type  : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -1.935
TNS   : -13.800
 
Type  : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -1.826
TNS   : -329.386
 
Type  : Fast 1100mV 85C Model Setup 'din_a'
Slack : -1.068
TNS   : -12.429
 
Type  : Fast 1100mV 85C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -0.558
TNS   : -5.149
 
Type  : Fast 1100mV 85C Model Setup 'FPGA_CLK1_50'
Slack : -0.405
TNS   : -0.405
 
Type  : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.122
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Hold 'FPGA_CLK1_50'
Slack : 0.175
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.179
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.217
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Hold 'din_a'
Slack : 0.242
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.302
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.648
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 6.842
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Recovery 'FPGA_CLK1_50'
Slack : 16.136
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Removal 'FPGA_CLK1_50'
Slack : 0.424
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.665
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.750
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.732
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.833
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Minimum Pulse Width 'din_a'
Slack : 1.215
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.480
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 4.240
TNS   : 0.000
 
Type  : Fast 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.073
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -1.794
TNS   : -2.071
 
Type  : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -1.717
TNS   : -6.939
 
Type  : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -1.507
TNS   : -230.983
 
Type  : Fast 1100mV 0C Model Setup 'din_a'
Slack : -0.704
TNS   : -5.641
 
Type  : Fast 1100mV 0C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -0.395
TNS   : -3.443
 
Type  : Fast 1100mV 0C Model Setup 'FPGA_CLK1_50'
Slack : -0.113
TNS   : -0.113
 
Type  : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.104
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.164
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Hold 'FPGA_CLK1_50'
Slack : 0.166
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.199
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Hold 'din_a'
Slack : 0.208
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.263
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.654
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 7.148
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Recovery 'FPGA_CLK1_50'
Slack : 16.628
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Removal 'FPGA_CLK1_50'
Slack : 0.327
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.616
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.684
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.757
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.823
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Minimum Pulse Width 'din_a'
Slack : 1.293
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.525
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 4.335
TNS   : 0.000
 
Type  : Fast 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.039
TNS   : 0.000
 
------------------------------------------------------------

Line No.	Rev	Author	Line
1	32	redbear	`------------------------------------------------------------`
2			`TimeQuest Timing Analyzer Summary`
3			`------------------------------------------------------------`
4
5	40	redbear	`Type : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
6			`Slack : -4.369`
7			`TNS : -113.702`
8
9			`Type : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
10			`Slack : -3.697`
11			`TNS : -1112.931`
12
13			`Type : Slow 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
14			`Slack : -3.138`
15			`TNS : -13.527`
16
17			`Type : Slow 1100mV 85C Model Setup 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
18			`Slack : -2.473`
19			`TNS : -27.460`
20
21			`Type : Slow 1100mV 85C Model Setup 'din_a'`
22			`Slack : -2.037`
23			`TNS : -45.867`
24
25	32	redbear	`Type : Slow 1100mV 85C Model Setup 'FPGA_CLK1_50'`
26	40	redbear	`Slack : -1.110`
27			`TNS : -2.017`
28	32	redbear
29			`Type : Slow 1100mV 85C Model Hold 'FPGA_CLK1_50'`
30	40	redbear	`Slack : 0.322`
31	32	redbear	`TNS : 0.000`
32
33	40	redbear	`Type : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
34			`Slack : 0.336`
35			`TNS : 0.000`
36
37			`Type : Slow 1100mV 85C Model Hold 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
38			`Slack : 0.393`
39			`TNS : 0.000`
40
41			`Type : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
42			`Slack : 0.470`
43			`TNS : 0.000`
44
45			`Type : Slow 1100mV 85C Model Hold 'din_a'`
46			`Slack : 0.547`
47			`TNS : 0.000`
48
49			`Type : Slow 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
50			`Slack : 0.624`
51			`TNS : 0.000`
52
53			`Type : Slow 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
54			`Slack : -0.289`
55			`TNS : -4.795`
56
57			`Type : Slow 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
58			`Slack : 5.248`
59			`TNS : 0.000`
60
61	32	redbear	`Type : Slow 1100mV 85C Model Recovery 'FPGA_CLK1_50'`
62	40	redbear	`Slack : 14.466`
63	32	redbear	`TNS : 0.000`
64
65			`Type : Slow 1100mV 85C Model Removal 'FPGA_CLK1_50'`
66	40	redbear	`Slack : 0.563`
67	32	redbear	`TNS : 0.000`
68
69	40	redbear	`Type : Slow 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
70			`Slack : 1.308`
71	35	redbear	`TNS : 0.000`
72
73	40	redbear	`Type : Slow 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
74			`Slack : 1.746`
75	32	redbear	`TNS : 0.000`
76
77	35	redbear	`Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
78	40	redbear	`Slack : 0.533`
79	32	redbear	`TNS : 0.000`
80
81	40	redbear	`Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
82			`Slack : 0.575`
83	32	redbear	`TNS : 0.000`
84
85	40	redbear	`Type : Slow 1100mV 85C Model Minimum Pulse Width 'din_a'`
86			`Slack : 0.994`
87	32	redbear	`TNS : 0.000`
88
89			`Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]'`
90			`Slack : 1.250`
91			`TNS : 0.000`
92
93	40	redbear	`Type : Slow 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
94			`Slack : 1.301`
95			`TNS : 0.000`
96
97			`Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
98			`Slack : 3.952`
99			`TNS : 0.000`
100
101	32	redbear	`Type : Slow 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'`
102	40	redbear	`Slack : 9.195`
103	32	redbear	`TNS : 0.000`
104
105	40	redbear	`Type : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
106			`Slack : -4.207`
107			`TNS : -109.829`
108
109			`Type : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
110			`Slack : -3.461`
111			`TNS : -1038.103`
112
113			`Type : Slow 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
114			`Slack : -2.976`
115			`TNS : -12.650`
116
117			`Type : Slow 1100mV 0C Model Setup 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
118			`Slack : -2.359`
119			`TNS : -27.122`
120
121			`Type : Slow 1100mV 0C Model Setup 'din_a'`
122			`Slack : -1.919`
123			`TNS : -41.436`
124
125	32	redbear	`Type : Slow 1100mV 0C Model Setup 'FPGA_CLK1_50'`
126	40	redbear	`Slack : -0.765`
127			`TNS : -1.140`
128	32	redbear
129			`Type : Slow 1100mV 0C Model Hold 'FPGA_CLK1_50'`
130	40	redbear	`Slack : 0.211`
131	32	redbear	`TNS : 0.000`
132
133	40	redbear	`Type : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
134			`Slack : 0.325`
135			`TNS : 0.000`
136
137			`Type : Slow 1100mV 0C Model Hold 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
138			`Slack : 0.388`
139			`TNS : 0.000`
140
141			`Type : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
142			`Slack : 0.478`
143			`TNS : 0.000`
144
145			`Type : Slow 1100mV 0C Model Hold 'din_a'`
146			`Slack : 0.530`
147			`TNS : 0.000`
148
149			`Type : Slow 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
150			`Slack : 0.599`
151			`TNS : 0.000`
152
153			`Type : Slow 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
154			`Slack : -0.346`
155			`TNS : -5.707`
156
157			`Type : Slow 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
158			`Slack : 5.377`
159			`TNS : 0.000`
160
161	32	redbear	`Type : Slow 1100mV 0C Model Recovery 'FPGA_CLK1_50'`
162	40	redbear	`Slack : 14.772`
163	32	redbear	`TNS : 0.000`
164
165			`Type : Slow 1100mV 0C Model Removal 'FPGA_CLK1_50'`
166	40	redbear	`Slack : 0.464`
167	32	redbear	`TNS : 0.000`
168
169	40	redbear	`Type : Slow 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
170			`Slack : 1.288`
171	32	redbear	`TNS : 0.000`
172
173	40	redbear	`Type : Slow 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
174			`Slack : 1.777`
175	32	redbear	`TNS : 0.000`
176
177	40	redbear	`Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
178			`Slack : 0.499`
179	32	redbear	`TNS : 0.000`
180
181	40	redbear	`Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
182			`Slack : 0.523`
183	32	redbear	`TNS : 0.000`
184
185	40	redbear	`Type : Slow 1100mV 0C Model Minimum Pulse Width 'din_a'`
186			`Slack : 0.986`
187	32	redbear	`TNS : 0.000`
188
189			`Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]'`
190			`Slack : 1.250`
191			`TNS : 0.000`
192
193	40	redbear	`Type : Slow 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
194			`Slack : 1.324`
195			`TNS : 0.000`
196
197			`Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
198			`Slack : 3.980`
199			`TNS : 0.000`
200
201	32	redbear	`Type : Slow 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'`
202	40	redbear	`Slack : 9.277`
203	32	redbear	`TNS : 0.000`
204
205	40	redbear	`Type : Fast 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
206			`Slack : -2.086`
207			`TNS : -3.029`
208
209			`Type : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
210			`Slack : -1.935`
211			`TNS : -13.800`
212
213			`Type : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
214			`Slack : -1.826`
215			`TNS : -329.386`
216
217			`Type : Fast 1100mV 85C Model Setup 'din_a'`
218			`Slack : -1.068`
219			`TNS : -12.429`
220
221			`Type : Fast 1100mV 85C Model Setup 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
222			`Slack : -0.558`
223			`TNS : -5.149`
224
225	32	redbear	`Type : Fast 1100mV 85C Model Setup 'FPGA_CLK1_50'`
226	40	redbear	`Slack : -0.405`
227			`TNS : -0.405`
228
229			`Type : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
230			`Slack : 0.122`
231	32	redbear	`TNS : 0.000`
232
233			`Type : Fast 1100mV 85C Model Hold 'FPGA_CLK1_50'`
234	40	redbear	`Slack : 0.175`
235	32	redbear	`TNS : 0.000`
236
237	40	redbear	`Type : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
238			`Slack : 0.179`
239			`TNS : 0.000`
240
241			`Type : Fast 1100mV 85C Model Hold 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
242			`Slack : 0.217`
243			`TNS : 0.000`
244
245			`Type : Fast 1100mV 85C Model Hold 'din_a'`
246			`Slack : 0.242`
247			`TNS : 0.000`
248
249			`Type : Fast 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
250			`Slack : 0.302`
251			`TNS : 0.000`
252
253			`Type : Fast 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
254			`Slack : 0.648`
255			`TNS : 0.000`
256
257			`Type : Fast 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
258			`Slack : 6.842`
259			`TNS : 0.000`
260
261	32	redbear	`Type : Fast 1100mV 85C Model Recovery 'FPGA_CLK1_50'`
262	40	redbear	`Slack : 16.136`
263	32	redbear	`TNS : 0.000`
264
265			`Type : Fast 1100mV 85C Model Removal 'FPGA_CLK1_50'`
266	40	redbear	`Slack : 0.424`
267	32	redbear	`TNS : 0.000`
268
269	40	redbear	`Type : Fast 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
270			`Slack : 0.665`
271	32	redbear	`TNS : 0.000`
272
273	40	redbear	`Type : Fast 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
274			`Slack : 0.750`
275	32	redbear	`TNS : 0.000`
276
277	40	redbear	`Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
278			`Slack : 0.732`
279	32	redbear	`TNS : 0.000`
280
281	40	redbear	`Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
282			`Slack : 0.833`
283	32	redbear	`TNS : 0.000`
284
285	40	redbear	`Type : Fast 1100mV 85C Model Minimum Pulse Width 'din_a'`
286			`Slack : 1.215`
287			`TNS : 0.000`
288
289	32	redbear	`Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]'`
290			`Slack : 1.250`
291			`TNS : 0.000`
292
293	40	redbear	`Type : Fast 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
294			`Slack : 1.480`
295			`TNS : 0.000`
296
297	35	redbear	`Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
298	40	redbear	`Slack : 4.240`
299	35	redbear	`TNS : 0.000`
300
301	32	redbear	`Type : Fast 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'`
302	40	redbear	`Slack : 9.073`
303	32	redbear	`TNS : 0.000`
304
305	40	redbear	`Type : Fast 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
306			`Slack : -1.794`
307			`TNS : -2.071`
308
309			`Type : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
310			`Slack : -1.717`
311			`TNS : -6.939`
312
313			`Type : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
314			`Slack : -1.507`
315			`TNS : -230.983`
316
317			`Type : Fast 1100mV 0C Model Setup 'din_a'`
318			`Slack : -0.704`
319			`TNS : -5.641`
320
321			`Type : Fast 1100mV 0C Model Setup 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
322			`Slack : -0.395`
323			`TNS : -3.443`
324
325	32	redbear	`Type : Fast 1100mV 0C Model Setup 'FPGA_CLK1_50'`
326	40	redbear	`Slack : -0.113`
327			`TNS : -0.113`
328
329			`Type : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
330			`Slack : 0.104`
331	32	redbear	`TNS : 0.000`
332
333	40	redbear	`Type : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
334			`Slack : 0.164`
335			`TNS : 0.000`
336
337	32	redbear	`Type : Fast 1100mV 0C Model Hold 'FPGA_CLK1_50'`
338	40	redbear	`Slack : 0.166`
339	32	redbear	`TNS : 0.000`
340
341	40	redbear	`Type : Fast 1100mV 0C Model Hold 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
342			`Slack : 0.199`
343			`TNS : 0.000`
344
345			`Type : Fast 1100mV 0C Model Hold 'din_a'`
346			`Slack : 0.208`
347			`TNS : 0.000`
348
349			`Type : Fast 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
350			`Slack : 0.263`
351			`TNS : 0.000`
352
353			`Type : Fast 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
354			`Slack : 0.654`
355			`TNS : 0.000`
356
357			`Type : Fast 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
358			`Slack : 7.148`
359			`TNS : 0.000`
360
361	32	redbear	`Type : Fast 1100mV 0C Model Recovery 'FPGA_CLK1_50'`
362	40	redbear	`Slack : 16.628`
363	32	redbear	`TNS : 0.000`
364
365			`Type : Fast 1100mV 0C Model Removal 'FPGA_CLK1_50'`
366	40	redbear	`Slack : 0.327`
367	32	redbear	`TNS : 0.000`
368
369	40	redbear	`Type : Fast 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
370			`Slack : 0.616`
371	32	redbear	`TNS : 0.000`
372
373	40	redbear	`Type : Fast 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
374			`Slack : 0.684`
375	32	redbear	`TNS : 0.000`
376
377	40	redbear	`Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i'`
378			`Slack : 0.757`
379	32	redbear	`TNS : 0.000`
380
381	40	redbear	`Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter[0].output_counter\|divclk'`
382			`Slack : 0.823`
383	32	redbear	`TNS : 0.000`
384
385			`Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph[0]'`
386			`Slack : 1.250`
387			`TNS : 0.000`
388
389	40	redbear	`Type : Fast 1100mV 0C Model Minimum Pulse Width 'din_a'`
390			`Slack : 1.293`
391			`TNS : 0.000`
392
393			`Type : Fast 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e'`
394			`Slack : 1.525`
395			`TNS : 0.000`
396
397	35	redbear	`Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i'`
398	40	redbear	`Slack : 4.335`
399	35	redbear	`TNS : 0.000`
400
401	32	redbear	`Type : Fast 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'`
402	40	redbear	`Slack : 9.039`
403	32	redbear	`TNS : 0.000`
404
405			`------------------------------------------------------------`

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