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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [altera_avalon_st_pipeline_base.v] - Blame information for rev 40

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// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.
 
 
// $File: //acds/rel/17.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2017/07/30 $
// $Author: swbranch $
//------------------------------------------------------------------------------
 
`timescale 1ns / 1ns
 
module altera_avalon_st_pipeline_base (
                                       clk,
                                       reset,
                                       in_ready,
                                       in_valid,
                                       in_data,
                                       out_ready,
                                       out_valid,
                                       out_data
                                       );
 
   parameter  SYMBOLS_PER_BEAT  = 1;
   parameter  BITS_PER_SYMBOL   = 8;
   parameter  PIPELINE_READY    = 1;
   localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
 
   input clk;
   input reset;
 
   output in_ready;
   input  in_valid;
   input [DATA_WIDTH-1:0] in_data;
 
   input                  out_ready;
   output                 out_valid;
   output [DATA_WIDTH-1:0] out_data;
 
   reg                     full0;
   reg                     full1;
   reg [DATA_WIDTH-1:0]    data0;
   reg [DATA_WIDTH-1:0]    data1;
 
   assign out_valid = full1;
   assign out_data  = data1;
 
   generate if (PIPELINE_READY == 1)
     begin : REGISTERED_READY_PLINE
 
        assign in_ready  = !full0;
 
        always @(posedge clk, posedge reset) begin
           if (reset) begin
              data0 <= {DATA_WIDTH{1'b0}};
              data1 <= {DATA_WIDTH{1'b0}};
           end else begin
              // ----------------------------
              // always load the second slot if we can
              // ----------------------------
              if (~full0)
                data0 <= in_data;
              // ----------------------------
              // first slot is loaded either from the second,
              // or with new data
              // ----------------------------
              if (~full1 || (out_ready && out_valid)) begin
                 if (full0)
                   data1 <= data0;
                 else
                   data1 <= in_data;
              end
           end
        end
 
        always @(posedge clk or posedge reset) begin
           if (reset) begin
              full0    <= 1'b0;
              full1    <= 1'b0;
           end else begin
              // no data in pipeline
              if (~full0 & ~full1) begin
                 if (in_valid) begin
                    full1 <= 1'b1;
                 end
              end // ~f1 & ~f0
 
              // one datum in pipeline 
              if (full1 & ~full0) begin
                 if (in_valid & ~out_ready) begin
                    full0 <= 1'b1;
                 end
                 // back to empty
                 if (~in_valid & out_ready) begin
                    full1 <= 1'b0;
                 end
              end // f1 & ~f0
 
              // two data in pipeline 
              if (full1 & full0) begin
                 // go back to one datum state
                 if (out_ready) begin
                    full0 <= 1'b0;
                 end
              end // end go back to one datum stage
           end
        end
 
     end
   else
     begin : UNREGISTERED_READY_PLINE
 
        // in_ready will be a pass through of the out_ready signal as it is not registered
        assign in_ready = (~full1) | out_ready;
 
        always @(posedge clk or posedge reset) begin
           if (reset) begin
              data1 <= 'b0;
              full1 <= 1'b0;
           end
           else begin
              if (in_ready) begin
                 data1 <= in_data;
                 full1 <= in_valid;
              end
           end
        end
     end
   endgenerate
endmodule

Line No.	Rev	Author	Line
1	32	redbear	`// (C) 2001-2017 Intel Corporation. All rights reserved.`
2			`// Your use of Intel Corporation's design tools, logic functions and other`
3			`// software and tools, and its AMPP partner logic functions, and any output`
4	40	redbear	`// files from any of the foregoing (including device programming or simulation`
5	32	redbear	`// files), and any associated documentation or information are expressly subject`
6			`// to the terms and conditions of the Intel Program License Subscription`
7	40	redbear	`// Agreement, Intel FPGA IP License Agreement, or other applicable`
8	32	redbear	`// license agreement, including, without limitation, that your use is for the`
9			`// sole purpose of programming logic devices manufactured by Intel and sold by`
10			`// Intel or its authorized distributors. Please refer to the applicable`
11			`// agreement for further details.`
12
13
14	40	redbear	`// $File: //acds/rel/17.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $`
15	32	redbear	`// $Revision: #1 $`
16	40	redbear	`// $Date: 2017/07/30 $`
17	32	redbear	`// $Author: swbranch $`
18			`//------------------------------------------------------------------------------`
19
20			`timescale 1ns / 1ns
21
22			`module altera_avalon_st_pipeline_base (`
23			`clk,`
24			`reset,`
25			`in_ready,`
26			`in_valid,`
27			`in_data,`
28			`out_ready,`
29			`out_valid,`
30			`out_data`
31			`);`
32
33			`parameter SYMBOLS_PER_BEAT = 1;`
34			`parameter BITS_PER_SYMBOL = 8;`
35			`parameter PIPELINE_READY = 1;`
36			`localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;`
37
38			`input clk;`
39			`input reset;`
40
41			`output in_ready;`
42			`input in_valid;`
43			`input [DATA_WIDTH-1:0] in_data;`
44
45			`input out_ready;`
46			`output out_valid;`
47			`output [DATA_WIDTH-1:0] out_data;`
48
49			`reg full0;`
50			`reg full1;`
51			`reg [DATA_WIDTH-1:0] data0;`
52			`reg [DATA_WIDTH-1:0] data1;`
53
54			`assign out_valid = full1;`
55			`assign out_data = data1;`
56
57			`generate if (PIPELINE_READY == 1)`
58			`begin : REGISTERED_READY_PLINE`
59
60			`assign in_ready = !full0;`
61
62			`always @(posedge clk, posedge reset) begin`
63			`if (reset) begin`
64			`data0 <= {DATA_WIDTH{1'b0}};`
65			`data1 <= {DATA_WIDTH{1'b0}};`
66			`end else begin`
67			`// ----------------------------`
68			`// always load the second slot if we can`
69			`// ----------------------------`
70			`if (~full0)`
71			`data0 <= in_data;`
72			`// ----------------------------`
73			`// first slot is loaded either from the second,`
74			`// or with new data`
75			`// ----------------------------`
76			`if (~full1 \|\| (out_ready && out_valid)) begin`
77			`if (full0)`
78			`data1 <= data0;`
79			`else`
80			`data1 <= in_data;`
81			`end`
82			`end`
83			`end`
84
85			`always @(posedge clk or posedge reset) begin`
86			`if (reset) begin`
87			`full0 <= 1'b0;`
88			`full1 <= 1'b0;`
89			`end else begin`
90			`// no data in pipeline`
91			`if (~full0 & ~full1) begin`
92			`if (in_valid) begin`
93			`full1 <= 1'b1;`
94			`end`
95			`end // ~f1 & ~f0`
96
97			`// one datum in pipeline`
98			`if (full1 & ~full0) begin`
99			`if (in_valid & ~out_ready) begin`
100			`full0 <= 1'b1;`
101			`end`
102			`// back to empty`
103			`if (~in_valid & out_ready) begin`
104			`full1 <= 1'b0;`
105			`end`
106			`end // f1 & ~f0`
107
108			`// two data in pipeline`
109			`if (full1 & full0) begin`
110			`// go back to one datum state`
111			`if (out_ready) begin`
112			`full0 <= 1'b0;`
113			`end`
114			`end // end go back to one datum stage`
115			`end`
116			`end`
117
118			`end`
119			`else`
120			`begin : UNREGISTERED_READY_PLINE`
121
122			`// in_ready will be a pass through of the out_ready signal as it is not registered`
123			`assign in_ready = (~full1) \| out_ready;`
124
125			`always @(posedge clk or posedge reset) begin`
126			`if (reset) begin`
127			`data1 <= 'b0;`
128			`full1 <= 1'b0;`
129			`end`
130			`else begin`
131			`if (in_ready) begin`
132			`data1 <= in_data;`
133			`full1 <= in_valid;`
134			`end`
135			`end`
136			`end`
137			`end`
138			`endgenerate`
139			`endmodule`

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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [altera_avalon_st_pipeline_base.v] - Blame information for rev 40