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redbear |
// hps_sdram.v
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// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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40 |
redbear |
// Generated using ACDS version 17.1 593
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32 |
redbear |
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`timescale 1 ps / 1 ps
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module hps_sdram (
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input wire pll_ref_clk, // pll_ref_clk.clk
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input wire global_reset_n, // global_reset.reset_n
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| 12 |
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input wire soft_reset_n, // soft_reset.reset_n
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output wire [12:0] mem_a, // memory.mem_a
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output wire [2:0] mem_ba, // .mem_ba
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output wire [0:0] mem_ck, // .mem_ck
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output wire [0:0] mem_ck_n, // .mem_ck_n
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output wire [0:0] mem_cke, // .mem_cke
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output wire [0:0] mem_cs_n, // .mem_cs_n
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output wire [0:0] mem_dm, // .mem_dm
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output wire [0:0] mem_ras_n, // .mem_ras_n
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output wire [0:0] mem_cas_n, // .mem_cas_n
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output wire [0:0] mem_we_n, // .mem_we_n
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output wire mem_reset_n, // .mem_reset_n
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inout wire [7:0] mem_dq, // .mem_dq
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inout wire [0:0] mem_dqs, // .mem_dqs
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inout wire [0:0] mem_dqs_n, // .mem_dqs_n
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output wire [0:0] mem_odt, // .mem_odt
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input wire oct_rzqin // oct.rzqin
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);
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wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
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wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
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wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
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wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
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wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
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wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
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wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
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wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
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wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
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wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
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wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
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wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
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wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
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wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
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wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
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wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
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wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
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wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
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wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
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wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
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wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
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wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
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wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
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wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
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wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
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wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
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wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
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wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
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wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
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wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
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wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
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wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
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wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
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wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
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wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
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wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
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wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
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wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
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wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
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wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
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wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
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wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
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wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
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wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
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wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
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wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
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wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
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wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
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wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
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wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
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wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
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wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
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wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
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wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
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hps_sdram_pll pll (
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.global_reset_n (global_reset_n), // global_reset.reset_n
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.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
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.afi_clk (pll_afi_clk_clk), // afi_clk.clk
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.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
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.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
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.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
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.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
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.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
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.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
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.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
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.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
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.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
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.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
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.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
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);
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hps_sdram_p0 p0 (
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.global_reset_n (global_reset_n), // global_reset.reset_n
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.soft_reset_n (soft_reset_n), // soft_reset.reset_n
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.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
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.afi_reset_export_n (), // afi_reset_export.reset_n
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.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
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.afi_clk (pll_afi_clk_clk), // afi_clk.clk
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.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
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.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
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.avl_clk (), // avl_clk.clk
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.avl_reset_n (), // avl_reset.reset_n
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.scc_clk (), // scc_clk.clk
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.scc_reset_n (), // scc_reset.reset_n
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.avl_address (), // avl.address
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.avl_write (), // .write
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.avl_writedata (), // .writedata
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.avl_read (), // .read
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.avl_readdata (), // .readdata
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.avl_waitrequest (), // .waitrequest
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.dll_clk (p0_dll_clk_clk), // dll_clk.clk
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.afi_addr (c0_afi_afi_addr), // afi.afi_addr
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.afi_ba (c0_afi_afi_ba), // .afi_ba
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.afi_cke (c0_afi_afi_cke), // .afi_cke
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.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
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.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
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.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
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.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
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.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
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.afi_odt (c0_afi_afi_odt), // .afi_odt
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.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
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.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
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.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
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.afi_dm (c0_afi_afi_dm), // .afi_dm
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.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
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.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
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.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
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.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
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.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
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.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
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.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
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.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
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.scc_data (), // scc.scc_data
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.scc_dqs_ena (), // .scc_dqs_ena
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.scc_dqs_io_ena (), // .scc_dqs_io_ena
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.scc_dq_ena (), // .scc_dq_ena
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| 152 |
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.scc_dm_ena (), // .scc_dm_ena
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| 153 |
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.capture_strobe_tracking (), // .capture_strobe_tracking
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| 154 |
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.scc_upd (), // .scc_upd
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| 155 |
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.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
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| 156 |
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.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
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| 157 |
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.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
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| 158 |
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.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
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| 159 |
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.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
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| 160 |
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.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
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| 161 |
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.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
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| 162 |
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.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
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| 163 |
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.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
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| 164 |
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.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
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| 165 |
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.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
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| 166 |
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.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
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| 167 |
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.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
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| 168 |
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.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
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| 169 |
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.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
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| 170 |
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.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
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| 171 |
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.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
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| 172 |
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.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
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| 173 |
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.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
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| 174 |
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.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
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| 175 |
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.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
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| 176 |
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.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
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| 177 |
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.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
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| 178 |
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.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
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| 179 |
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.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
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| 180 |
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.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
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| 181 |
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.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
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| 182 |
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.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
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| 183 |
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.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
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| 184 |
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.mem_a (mem_a), // memory.mem_a
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| 185 |
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.mem_ba (mem_ba), // .mem_ba
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| 186 |
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.mem_ck (mem_ck), // .mem_ck
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| 187 |
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.mem_ck_n (mem_ck_n), // .mem_ck_n
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| 188 |
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.mem_cke (mem_cke), // .mem_cke
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| 189 |
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.mem_cs_n (mem_cs_n), // .mem_cs_n
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| 190 |
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.mem_dm (mem_dm), // .mem_dm
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| 191 |
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.mem_ras_n (mem_ras_n), // .mem_ras_n
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| 192 |
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.mem_cas_n (mem_cas_n), // .mem_cas_n
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| 193 |
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.mem_we_n (mem_we_n), // .mem_we_n
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| 194 |
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.mem_reset_n (mem_reset_n), // .mem_reset_n
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| 195 |
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.mem_dq (mem_dq), // .mem_dq
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| 196 |
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.mem_dqs (mem_dqs), // .mem_dqs
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| 197 |
|
|
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
|
| 198 |
|
|
.mem_odt (mem_odt), // .mem_odt
|
| 199 |
|
|
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
|
| 200 |
|
|
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
|
| 201 |
|
|
.csr_soft_reset_req (1'b0), // (terminated)
|
| 202 |
|
|
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
|
| 203 |
|
|
.io_intbadout (12'b000000000000), // (terminated)
|
| 204 |
|
|
.io_intcasndout (4'b0000), // (terminated)
|
| 205 |
|
|
.io_intckdout (4'b0000), // (terminated)
|
| 206 |
|
|
.io_intckedout (8'b00000000), // (terminated)
|
| 207 |
|
|
.io_intckndout (4'b0000), // (terminated)
|
| 208 |
|
|
.io_intcsndout (8'b00000000), // (terminated)
|
| 209 |
|
|
.io_intdmdout (20'b00000000000000000000), // (terminated)
|
| 210 |
|
|
.io_intdqdin (), // (terminated)
|
| 211 |
|
|
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
|
| 212 |
|
|
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
|
| 213 |
|
|
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
|
| 214 |
|
|
.io_intdqsboe (10'b0000000000), // (terminated)
|
| 215 |
|
|
.io_intdqsdout (20'b00000000000000000000), // (terminated)
|
| 216 |
|
|
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
|
| 217 |
|
|
.io_intdqslogicfiforeset (5'b00000), // (terminated)
|
| 218 |
|
|
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
|
| 219 |
|
|
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
|
| 220 |
|
|
.io_intdqslogicoct (10'b0000000000), // (terminated)
|
| 221 |
|
|
.io_intdqslogicrdatavalid (), // (terminated)
|
| 222 |
|
|
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
|
| 223 |
|
|
.io_intdqsoe (10'b0000000000), // (terminated)
|
| 224 |
|
|
.io_intodtdout (8'b00000000), // (terminated)
|
| 225 |
|
|
.io_intrasndout (4'b0000), // (terminated)
|
| 226 |
|
|
.io_intresetndout (4'b0000), // (terminated)
|
| 227 |
|
|
.io_intwendout (4'b0000), // (terminated)
|
| 228 |
|
|
.io_intafirlat (), // (terminated)
|
| 229 |
|
|
.io_intafiwlat () // (terminated)
|
| 230 |
|
|
);
|
| 231 |
|
|
|
| 232 |
|
|
altera_mem_if_hhp_qseq_synth_top #(
|
| 233 |
|
|
.MEM_IF_DM_WIDTH (1),
|
| 234 |
|
|
.MEM_IF_DQS_WIDTH (1),
|
| 235 |
|
|
.MEM_IF_CS_WIDTH (1),
|
| 236 |
|
|
.MEM_IF_DQ_WIDTH (8)
|
| 237 |
|
|
) seq (
|
| 238 |
|
|
);
|
| 239 |
|
|
|
| 240 |
|
|
altera_mem_if_hard_memory_controller_top_cyclonev #(
|
| 241 |
|
|
.MEM_IF_DQS_WIDTH (1),
|
| 242 |
|
|
.MEM_IF_CS_WIDTH (1),
|
| 243 |
|
|
.MEM_IF_CHIP_BITS (1),
|
| 244 |
|
|
.MEM_IF_CLK_PAIR_COUNT (1),
|
| 245 |
|
|
.CSR_ADDR_WIDTH (10),
|
| 246 |
|
|
.CSR_DATA_WIDTH (8),
|
| 247 |
|
|
.CSR_BE_WIDTH (1),
|
| 248 |
|
|
.AVL_ADDR_WIDTH (22),
|
| 249 |
|
|
.AVL_DATA_WIDTH (16),
|
| 250 |
|
|
.AVL_SIZE_WIDTH (3),
|
| 251 |
|
|
.AVL_DATA_WIDTH_PORT_0 (1),
|
| 252 |
|
|
.AVL_ADDR_WIDTH_PORT_0 (1),
|
| 253 |
|
|
.AVL_NUM_SYMBOLS_PORT_0 (1),
|
| 254 |
|
|
.LSB_WFIFO_PORT_0 (5),
|
| 255 |
|
|
.MSB_WFIFO_PORT_0 (5),
|
| 256 |
|
|
.LSB_RFIFO_PORT_0 (5),
|
| 257 |
|
|
.MSB_RFIFO_PORT_0 (5),
|
| 258 |
|
|
.AVL_DATA_WIDTH_PORT_1 (1),
|
| 259 |
|
|
.AVL_ADDR_WIDTH_PORT_1 (1),
|
| 260 |
|
|
.AVL_NUM_SYMBOLS_PORT_1 (1),
|
| 261 |
|
|
.LSB_WFIFO_PORT_1 (5),
|
| 262 |
|
|
.MSB_WFIFO_PORT_1 (5),
|
| 263 |
|
|
.LSB_RFIFO_PORT_1 (5),
|
| 264 |
|
|
.MSB_RFIFO_PORT_1 (5),
|
| 265 |
|
|
.AVL_DATA_WIDTH_PORT_2 (1),
|
| 266 |
|
|
.AVL_ADDR_WIDTH_PORT_2 (1),
|
| 267 |
|
|
.AVL_NUM_SYMBOLS_PORT_2 (1),
|
| 268 |
|
|
.LSB_WFIFO_PORT_2 (5),
|
| 269 |
|
|
.MSB_WFIFO_PORT_2 (5),
|
| 270 |
|
|
.LSB_RFIFO_PORT_2 (5),
|
| 271 |
|
|
.MSB_RFIFO_PORT_2 (5),
|
| 272 |
|
|
.AVL_DATA_WIDTH_PORT_3 (1),
|
| 273 |
|
|
.AVL_ADDR_WIDTH_PORT_3 (1),
|
| 274 |
|
|
.AVL_NUM_SYMBOLS_PORT_3 (1),
|
| 275 |
|
|
.LSB_WFIFO_PORT_3 (5),
|
| 276 |
|
|
.MSB_WFIFO_PORT_3 (5),
|
| 277 |
|
|
.LSB_RFIFO_PORT_3 (5),
|
| 278 |
|
|
.MSB_RFIFO_PORT_3 (5),
|
| 279 |
|
|
.AVL_DATA_WIDTH_PORT_4 (1),
|
| 280 |
|
|
.AVL_ADDR_WIDTH_PORT_4 (1),
|
| 281 |
|
|
.AVL_NUM_SYMBOLS_PORT_4 (1),
|
| 282 |
|
|
.LSB_WFIFO_PORT_4 (5),
|
| 283 |
|
|
.MSB_WFIFO_PORT_4 (5),
|
| 284 |
|
|
.LSB_RFIFO_PORT_4 (5),
|
| 285 |
|
|
.MSB_RFIFO_PORT_4 (5),
|
| 286 |
|
|
.AVL_DATA_WIDTH_PORT_5 (1),
|
| 287 |
|
|
.AVL_ADDR_WIDTH_PORT_5 (1),
|
| 288 |
|
|
.AVL_NUM_SYMBOLS_PORT_5 (1),
|
| 289 |
|
|
.LSB_WFIFO_PORT_5 (5),
|
| 290 |
|
|
.MSB_WFIFO_PORT_5 (5),
|
| 291 |
|
|
.LSB_RFIFO_PORT_5 (5),
|
| 292 |
|
|
.MSB_RFIFO_PORT_5 (5),
|
| 293 |
|
|
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
|
| 294 |
|
|
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
|
| 295 |
|
|
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
|
| 296 |
|
|
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
|
| 297 |
|
|
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
|
| 298 |
|
|
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
|
| 299 |
|
|
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
|
| 300 |
|
|
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
|
| 301 |
|
|
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
|
| 302 |
|
|
.ENUM_CAL_REQ ("DISABLED"),
|
| 303 |
|
|
.ENUM_CFG_BURST_LENGTH ("BL_8"),
|
| 304 |
|
|
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_8"),
|
| 305 |
|
|
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
|
| 306 |
|
|
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
|
| 307 |
|
|
.ENUM_CFG_TYPE ("DDR3"),
|
| 308 |
|
|
.ENUM_CLOCK_OFF_0 ("DISABLED"),
|
| 309 |
|
|
.ENUM_CLOCK_OFF_1 ("DISABLED"),
|
| 310 |
|
|
.ENUM_CLOCK_OFF_2 ("DISABLED"),
|
| 311 |
|
|
.ENUM_CLOCK_OFF_3 ("DISABLED"),
|
| 312 |
|
|
.ENUM_CLOCK_OFF_4 ("DISABLED"),
|
| 313 |
|
|
.ENUM_CLOCK_OFF_5 ("DISABLED"),
|
| 314 |
|
|
.ENUM_CLR_INTR ("NO_CLR_INTR"),
|
| 315 |
|
|
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
|
| 316 |
|
|
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
|
| 317 |
|
|
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
|
| 318 |
|
|
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
|
| 319 |
|
|
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
|
| 320 |
|
|
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
|
| 321 |
|
|
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 322 |
|
|
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
|
| 323 |
|
|
.ENUM_CPORT0_TYPE ("DISABLE"),
|
| 324 |
|
|
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
|
| 325 |
|
|
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 326 |
|
|
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
|
| 327 |
|
|
.ENUM_CPORT1_TYPE ("DISABLE"),
|
| 328 |
|
|
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
|
| 329 |
|
|
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 330 |
|
|
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
|
| 331 |
|
|
.ENUM_CPORT2_TYPE ("DISABLE"),
|
| 332 |
|
|
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
|
| 333 |
|
|
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 334 |
|
|
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
|
| 335 |
|
|
.ENUM_CPORT3_TYPE ("DISABLE"),
|
| 336 |
|
|
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
|
| 337 |
|
|
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 338 |
|
|
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
|
| 339 |
|
|
.ENUM_CPORT4_TYPE ("DISABLE"),
|
| 340 |
|
|
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
|
| 341 |
|
|
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 342 |
|
|
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
|
| 343 |
|
|
.ENUM_CPORT5_TYPE ("DISABLE"),
|
| 344 |
|
|
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
|
| 345 |
|
|
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
|
| 346 |
|
|
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
|
| 347 |
|
|
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
|
| 348 |
|
|
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
|
| 349 |
|
|
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
|
| 350 |
|
|
.ENUM_CTRL_WIDTH ("DATA_WIDTH_16_BIT"),
|
| 351 |
|
|
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
|
| 352 |
|
|
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
|
| 353 |
|
|
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
|
| 354 |
|
|
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
|
| 355 |
|
|
.ENUM_ENABLE_ATPG ("DISABLED"),
|
| 356 |
|
|
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
|
| 357 |
|
|
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
|
| 358 |
|
|
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
|
| 359 |
|
|
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
|
| 360 |
|
|
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
|
| 361 |
|
|
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
|
| 362 |
|
|
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
|
| 363 |
|
|
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
|
| 364 |
|
|
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
|
| 365 |
|
|
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
|
| 366 |
|
|
.ENUM_ENABLE_INTR ("DISABLED"),
|
| 367 |
|
|
.ENUM_ENABLE_NO_DM ("DISABLED"),
|
| 368 |
|
|
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
|
| 369 |
|
|
.ENUM_GANGED_ARF ("DISABLED"),
|
| 370 |
|
|
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
|
| 371 |
|
|
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
|
| 372 |
|
|
.ENUM_INC_SYNC ("FIFO_SET_2"),
|
| 373 |
|
|
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
|
| 374 |
|
|
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
|
| 375 |
|
|
.ENUM_MASK_DBE_INTR ("DISABLED"),
|
| 376 |
|
|
.ENUM_MASK_SBE_INTR ("DISABLED"),
|
| 377 |
|
|
.ENUM_MEM_IF_AL ("AL_0"),
|
| 378 |
|
|
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
|
| 379 |
|
|
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
|
| 380 |
|
|
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_8"),
|
| 381 |
|
|
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
|
| 382 |
|
|
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
|
| 383 |
|
|
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
|
| 384 |
|
|
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_1"),
|
| 385 |
|
|
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_8"),
|
| 386 |
|
|
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
|
| 387 |
|
|
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_12"),
|
| 388 |
|
|
.ENUM_MEM_IF_SPEEDBIN ("DDR3_800_5_5_5"),
|
| 389 |
|
|
.ENUM_MEM_IF_TCCD ("TCCD_4"),
|
| 390 |
|
|
.ENUM_MEM_IF_TCL ("TCL_7"),
|
| 391 |
|
|
.ENUM_MEM_IF_TCWL ("TCWL_6"),
|
| 392 |
|
|
.ENUM_MEM_IF_TFAW ("TFAW_12"),
|
| 393 |
|
|
.ENUM_MEM_IF_TMRD ("TMRD_4"),
|
| 394 |
|
|
.ENUM_MEM_IF_TRAS ("TRAS_13"),
|
| 395 |
|
|
.ENUM_MEM_IF_TRC ("TRC_17"),
|
| 396 |
|
|
.ENUM_MEM_IF_TRCD ("TRCD_5"),
|
| 397 |
|
|
.ENUM_MEM_IF_TRP ("TRP_5"),
|
| 398 |
|
|
.ENUM_MEM_IF_TRRD ("TRRD_3"),
|
| 399 |
|
|
.ENUM_MEM_IF_TRTP ("TRTP_3"),
|
| 400 |
|
|
.ENUM_MEM_IF_TWR ("TWR_5"),
|
| 401 |
|
|
.ENUM_MEM_IF_TWTR ("TWTR_2"),
|
| 402 |
|
|
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
|
| 403 |
|
|
.ENUM_OUTPUT_REGD ("DISABLED"),
|
| 404 |
|
|
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
|
| 405 |
|
|
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
|
| 406 |
|
|
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
|
| 407 |
|
|
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
|
| 408 |
|
|
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
|
| 409 |
|
|
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
|
| 410 |
|
|
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
|
| 411 |
|
|
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
|
| 412 |
|
|
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
|
| 413 |
|
|
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
|
| 414 |
|
|
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
|
| 415 |
|
|
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
|
| 416 |
|
|
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
|
| 417 |
|
|
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
|
| 418 |
|
|
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
|
| 419 |
|
|
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
|
| 420 |
|
|
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
|
| 421 |
|
|
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
|
| 422 |
|
|
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
|
| 423 |
|
|
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
|
| 424 |
|
|
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
|
| 425 |
|
|
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
|
| 426 |
|
|
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
|
| 427 |
|
|
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
|
| 428 |
|
|
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
|
| 429 |
|
|
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
|
| 430 |
|
|
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
|
| 431 |
|
|
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
|
| 432 |
|
|
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
|
| 433 |
|
|
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
|
| 434 |
|
|
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
|
| 435 |
|
|
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
|
| 436 |
|
|
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
|
| 437 |
|
|
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
|
| 438 |
|
|
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
|
| 439 |
|
|
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
|
| 440 |
|
|
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
|
| 441 |
|
|
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
|
| 442 |
|
|
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
|
| 443 |
|
|
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
|
| 444 |
|
|
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
|
| 445 |
|
|
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
|
| 446 |
|
|
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
|
| 447 |
|
|
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
|
| 448 |
|
|
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
|
| 449 |
|
|
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
|
| 450 |
|
|
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
|
| 451 |
|
|
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
|
| 452 |
|
|
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
|
| 453 |
|
|
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
|
| 454 |
|
|
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
|
| 455 |
|
|
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
|
| 456 |
|
|
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
|
| 457 |
|
|
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
|
| 458 |
|
|
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
|
| 459 |
|
|
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
|
| 460 |
|
|
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
|
| 461 |
|
|
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
|
| 462 |
|
|
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
|
| 463 |
|
|
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
|
| 464 |
|
|
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
|
| 465 |
|
|
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
|
| 466 |
|
|
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
|
| 467 |
|
|
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
|
| 468 |
|
|
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
|
| 469 |
|
|
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
|
| 470 |
|
|
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
|
| 471 |
|
|
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
|
| 472 |
|
|
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
|
| 473 |
|
|
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
|
| 474 |
|
|
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
|
| 475 |
|
|
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
|
| 476 |
|
|
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
|
| 477 |
|
|
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
|
| 478 |
|
|
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
|
| 479 |
|
|
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
|
| 480 |
|
|
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
|
| 481 |
|
|
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
|
| 482 |
|
|
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
|
| 483 |
|
|
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
|
| 484 |
|
|
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
|
| 485 |
|
|
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
|
| 486 |
|
|
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
|
| 487 |
|
|
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
|
| 488 |
|
|
.ENUM_REORDER_DATA ("DATA_REORDERING"),
|
| 489 |
|
|
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
|
| 490 |
|
|
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
|
| 491 |
|
|
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
|
| 492 |
|
|
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
|
| 493 |
|
|
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
|
| 494 |
|
|
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
|
| 495 |
|
|
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
|
| 496 |
|
|
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
|
| 497 |
|
|
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
|
| 498 |
|
|
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
|
| 499 |
|
|
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
|
| 500 |
|
|
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
|
| 501 |
|
|
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
|
| 502 |
|
|
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
|
| 503 |
|
|
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
|
| 504 |
|
|
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
|
| 505 |
|
|
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
|
| 506 |
|
|
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
|
| 507 |
|
|
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
|
| 508 |
|
|
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
|
| 509 |
|
|
.ENUM_TEST_MODE ("NORMAL_MODE"),
|
| 510 |
|
|
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
|
| 511 |
|
|
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
|
| 512 |
|
|
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
|
| 513 |
|
|
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
|
| 514 |
|
|
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
|
| 515 |
|
|
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
|
| 516 |
|
|
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
|
| 517 |
|
|
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
|
| 518 |
|
|
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
|
| 519 |
|
|
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
|
| 520 |
|
|
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
|
| 521 |
|
|
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
|
| 522 |
|
|
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
|
| 523 |
|
|
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
|
| 524 |
|
|
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
|
| 525 |
|
|
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
|
| 526 |
|
|
.ENUM_USER_ECC_EN ("DISABLE"),
|
| 527 |
|
|
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
|
| 528 |
|
|
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
|
| 529 |
|
|
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
|
| 530 |
|
|
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
|
| 531 |
|
|
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
|
| 532 |
|
|
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
|
| 533 |
|
|
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
|
| 534 |
|
|
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 535 |
|
|
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
|
| 536 |
|
|
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 537 |
|
|
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
|
| 538 |
|
|
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 539 |
|
|
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
|
| 540 |
|
|
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
|
| 541 |
|
|
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
|
| 542 |
|
|
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
|
| 543 |
|
|
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
|
| 544 |
|
|
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
|
| 545 |
|
|
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
|
| 546 |
|
|
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
|
| 547 |
|
|
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
|
| 548 |
|
|
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
|
| 549 |
|
|
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
|
| 550 |
|
|
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
|
| 551 |
|
|
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
|
| 552 |
|
|
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
|
| 553 |
|
|
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
|
| 554 |
|
|
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
|
| 555 |
|
|
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
|
| 556 |
|
|
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
|
| 557 |
|
|
.ENUM_WRITE_ODT_CHIP ("ODT_DISABLED"),
|
| 558 |
|
|
.INTG_MEM_AUTO_PD_CYCLES (0),
|
| 559 |
|
|
.INTG_CYC_TO_RLD_JARS_0 (1),
|
| 560 |
|
|
.INTG_CYC_TO_RLD_JARS_1 (1),
|
| 561 |
|
|
.INTG_CYC_TO_RLD_JARS_2 (1),
|
| 562 |
|
|
.INTG_CYC_TO_RLD_JARS_3 (1),
|
| 563 |
|
|
.INTG_CYC_TO_RLD_JARS_4 (1),
|
| 564 |
|
|
.INTG_CYC_TO_RLD_JARS_5 (1),
|
| 565 |
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
|
| 566 |
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
|
| 567 |
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
|
| 568 |
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
|
| 569 |
|
|
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
|
| 570 |
|
|
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
|
| 571 |
|
|
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
|
| 572 |
|
|
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
|
| 573 |
|
|
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
|
| 574 |
|
|
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
|
| 575 |
|
|
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
|
| 576 |
|
|
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
|
| 577 |
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
|
| 578 |
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
|
| 579 |
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
|
| 580 |
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
|
| 581 |
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
|
| 582 |
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
|
| 583 |
|
|
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
|
| 584 |
|
|
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
|
| 585 |
|
|
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
|
| 586 |
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
|
| 587 |
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
|
| 588 |
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
|
| 589 |
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
|
| 590 |
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
|
| 591 |
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
|
| 592 |
|
|
.INTG_MEM_IF_TREFI (2101),
|
| 593 |
|
|
.INTG_MEM_IF_TRFC (23),
|
| 594 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
|
| 595 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
|
| 596 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
|
| 597 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
|
| 598 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
|
| 599 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
|
| 600 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
|
| 601 |
|
|
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
|
| 602 |
|
|
.INTG_SUM_WT_PRIORITY_0 (0),
|
| 603 |
|
|
.INTG_SUM_WT_PRIORITY_1 (0),
|
| 604 |
|
|
.INTG_SUM_WT_PRIORITY_2 (0),
|
| 605 |
|
|
.INTG_SUM_WT_PRIORITY_3 (0),
|
| 606 |
|
|
.INTG_SUM_WT_PRIORITY_4 (0),
|
| 607 |
|
|
.INTG_SUM_WT_PRIORITY_5 (0),
|
| 608 |
|
|
.INTG_SUM_WT_PRIORITY_6 (0),
|
| 609 |
|
|
.INTG_SUM_WT_PRIORITY_7 (0),
|
| 610 |
|
|
.INTG_POWER_SAVING_EXIT_CYCLES (5),
|
| 611 |
|
|
.INTG_MEM_CLK_ENTRY_CYCLES (10),
|
| 612 |
|
|
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
|
| 613 |
|
|
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
|
| 614 |
|
|
.AFI_RATE_RATIO (1),
|
| 615 |
|
|
.AFI_ADDR_WIDTH (13),
|
| 616 |
|
|
.AFI_BANKADDR_WIDTH (3),
|
| 617 |
|
|
.AFI_CONTROL_WIDTH (1),
|
| 618 |
|
|
.AFI_CS_WIDTH (1),
|
| 619 |
|
|
.AFI_DM_WIDTH (2),
|
| 620 |
|
|
.AFI_DQ_WIDTH (16),
|
| 621 |
|
|
.AFI_ODT_WIDTH (1),
|
| 622 |
|
|
.AFI_WRITE_DQS_WIDTH (1),
|
| 623 |
|
|
.AFI_RLAT_WIDTH (6),
|
| 624 |
|
|
.AFI_WLAT_WIDTH (6),
|
| 625 |
|
|
.HARD_PHY (1)
|
| 626 |
|
|
) c0 (
|
| 627 |
|
|
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
|
| 628 |
|
|
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
|
| 629 |
|
|
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
|
| 630 |
|
|
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
|
| 631 |
|
|
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
|
| 632 |
|
|
.local_init_done (), // status.local_init_done
|
| 633 |
|
|
.local_cal_success (), // .local_cal_success
|
| 634 |
|
|
.local_cal_fail (), // .local_cal_fail
|
| 635 |
|
|
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
|
| 636 |
|
|
.afi_ba (c0_afi_afi_ba), // .afi_ba
|
| 637 |
|
|
.afi_cke (c0_afi_afi_cke), // .afi_cke
|
| 638 |
|
|
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
|
| 639 |
|
|
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
|
| 640 |
|
|
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
|
| 641 |
|
|
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
|
| 642 |
|
|
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
|
| 643 |
|
|
.afi_odt (c0_afi_afi_odt), // .afi_odt
|
| 644 |
|
|
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
|
| 645 |
|
|
.afi_init_req (), // .afi_init_req
|
| 646 |
|
|
.afi_cal_req (), // .afi_cal_req
|
| 647 |
|
|
.afi_seq_busy (), // .afi_seq_busy
|
| 648 |
|
|
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
|
| 649 |
|
|
.afi_ctl_long_idle (), // .afi_ctl_long_idle
|
| 650 |
|
|
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
|
| 651 |
|
|
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
|
| 652 |
|
|
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
|
| 653 |
|
|
.afi_dm (c0_afi_afi_dm), // .afi_dm
|
| 654 |
|
|
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
|
| 655 |
|
|
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
|
| 656 |
|
|
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
|
| 657 |
|
|
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
|
| 658 |
|
|
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
|
| 659 |
|
|
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
|
| 660 |
|
|
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
|
| 661 |
|
|
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
|
| 662 |
|
|
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
|
| 663 |
|
|
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
|
| 664 |
|
|
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
|
| 665 |
|
|
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
|
| 666 |
|
|
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
|
| 667 |
|
|
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
|
| 668 |
|
|
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
|
| 669 |
|
|
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
|
| 670 |
|
|
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
|
| 671 |
|
|
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
|
| 672 |
|
|
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
|
| 673 |
|
|
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
|
| 674 |
|
|
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
|
| 675 |
|
|
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
|
| 676 |
|
|
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
|
| 677 |
|
|
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
|
| 678 |
|
|
.mp_cmd_clk_0 (1'b0), // (terminated)
|
| 679 |
|
|
.mp_cmd_reset_n_0 (1'b1), // (terminated)
|
| 680 |
|
|
.mp_cmd_clk_1 (1'b0), // (terminated)
|
| 681 |
|
|
.mp_cmd_reset_n_1 (1'b1), // (terminated)
|
| 682 |
|
|
.mp_cmd_clk_2 (1'b0), // (terminated)
|
| 683 |
|
|
.mp_cmd_reset_n_2 (1'b1), // (terminated)
|
| 684 |
|
|
.mp_cmd_clk_3 (1'b0), // (terminated)
|
| 685 |
|
|
.mp_cmd_reset_n_3 (1'b1), // (terminated)
|
| 686 |
|
|
.mp_cmd_clk_4 (1'b0), // (terminated)
|
| 687 |
|
|
.mp_cmd_reset_n_4 (1'b1), // (terminated)
|
| 688 |
|
|
.mp_cmd_clk_5 (1'b0), // (terminated)
|
| 689 |
|
|
.mp_cmd_reset_n_5 (1'b1), // (terminated)
|
| 690 |
|
|
.mp_rfifo_clk_0 (1'b0), // (terminated)
|
| 691 |
|
|
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
|
| 692 |
|
|
.mp_wfifo_clk_0 (1'b0), // (terminated)
|
| 693 |
|
|
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
|
| 694 |
|
|
.mp_rfifo_clk_1 (1'b0), // (terminated)
|
| 695 |
|
|
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
|
| 696 |
|
|
.mp_wfifo_clk_1 (1'b0), // (terminated)
|
| 697 |
|
|
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
|
| 698 |
|
|
.mp_rfifo_clk_2 (1'b0), // (terminated)
|
| 699 |
|
|
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
|
| 700 |
|
|
.mp_wfifo_clk_2 (1'b0), // (terminated)
|
| 701 |
|
|
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
|
| 702 |
|
|
.mp_rfifo_clk_3 (1'b0), // (terminated)
|
| 703 |
|
|
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
|
| 704 |
|
|
.mp_wfifo_clk_3 (1'b0), // (terminated)
|
| 705 |
|
|
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
|
| 706 |
|
|
.csr_clk (1'b0), // (terminated)
|
| 707 |
|
|
.csr_reset_n (1'b1), // (terminated)
|
| 708 |
|
|
.avl_ready_0 (), // (terminated)
|
| 709 |
|
|
.avl_burstbegin_0 (1'b0), // (terminated)
|
| 710 |
|
|
.avl_addr_0 (1'b0), // (terminated)
|
| 711 |
|
|
.avl_rdata_valid_0 (), // (terminated)
|
| 712 |
|
|
.avl_rdata_0 (), // (terminated)
|
| 713 |
|
|
.avl_wdata_0 (1'b0), // (terminated)
|
| 714 |
|
|
.avl_be_0 (1'b0), // (terminated)
|
| 715 |
|
|
.avl_read_req_0 (1'b0), // (terminated)
|
| 716 |
|
|
.avl_write_req_0 (1'b0), // (terminated)
|
| 717 |
|
|
.avl_size_0 (3'b000), // (terminated)
|
| 718 |
|
|
.avl_ready_1 (), // (terminated)
|
| 719 |
|
|
.avl_burstbegin_1 (1'b0), // (terminated)
|
| 720 |
|
|
.avl_addr_1 (1'b0), // (terminated)
|
| 721 |
|
|
.avl_rdata_valid_1 (), // (terminated)
|
| 722 |
|
|
.avl_rdata_1 (), // (terminated)
|
| 723 |
|
|
.avl_wdata_1 (1'b0), // (terminated)
|
| 724 |
|
|
.avl_be_1 (1'b0), // (terminated)
|
| 725 |
|
|
.avl_read_req_1 (1'b0), // (terminated)
|
| 726 |
|
|
.avl_write_req_1 (1'b0), // (terminated)
|
| 727 |
|
|
.avl_size_1 (3'b000), // (terminated)
|
| 728 |
|
|
.avl_ready_2 (), // (terminated)
|
| 729 |
|
|
.avl_burstbegin_2 (1'b0), // (terminated)
|
| 730 |
|
|
.avl_addr_2 (1'b0), // (terminated)
|
| 731 |
|
|
.avl_rdata_valid_2 (), // (terminated)
|
| 732 |
|
|
.avl_rdata_2 (), // (terminated)
|
| 733 |
|
|
.avl_wdata_2 (1'b0), // (terminated)
|
| 734 |
|
|
.avl_be_2 (1'b0), // (terminated)
|
| 735 |
|
|
.avl_read_req_2 (1'b0), // (terminated)
|
| 736 |
|
|
.avl_write_req_2 (1'b0), // (terminated)
|
| 737 |
|
|
.avl_size_2 (3'b000), // (terminated)
|
| 738 |
|
|
.avl_ready_3 (), // (terminated)
|
| 739 |
|
|
.avl_burstbegin_3 (1'b0), // (terminated)
|
| 740 |
|
|
.avl_addr_3 (1'b0), // (terminated)
|
| 741 |
|
|
.avl_rdata_valid_3 (), // (terminated)
|
| 742 |
|
|
.avl_rdata_3 (), // (terminated)
|
| 743 |
|
|
.avl_wdata_3 (1'b0), // (terminated)
|
| 744 |
|
|
.avl_be_3 (1'b0), // (terminated)
|
| 745 |
|
|
.avl_read_req_3 (1'b0), // (terminated)
|
| 746 |
|
|
.avl_write_req_3 (1'b0), // (terminated)
|
| 747 |
|
|
.avl_size_3 (3'b000), // (terminated)
|
| 748 |
|
|
.avl_ready_4 (), // (terminated)
|
| 749 |
|
|
.avl_burstbegin_4 (1'b0), // (terminated)
|
| 750 |
|
|
.avl_addr_4 (1'b0), // (terminated)
|
| 751 |
|
|
.avl_rdata_valid_4 (), // (terminated)
|
| 752 |
|
|
.avl_rdata_4 (), // (terminated)
|
| 753 |
|
|
.avl_wdata_4 (1'b0), // (terminated)
|
| 754 |
|
|
.avl_be_4 (1'b0), // (terminated)
|
| 755 |
|
|
.avl_read_req_4 (1'b0), // (terminated)
|
| 756 |
|
|
.avl_write_req_4 (1'b0), // (terminated)
|
| 757 |
|
|
.avl_size_4 (3'b000), // (terminated)
|
| 758 |
|
|
.avl_ready_5 (), // (terminated)
|
| 759 |
|
|
.avl_burstbegin_5 (1'b0), // (terminated)
|
| 760 |
|
|
.avl_addr_5 (1'b0), // (terminated)
|
| 761 |
|
|
.avl_rdata_valid_5 (), // (terminated)
|
| 762 |
|
|
.avl_rdata_5 (), // (terminated)
|
| 763 |
|
|
.avl_wdata_5 (1'b0), // (terminated)
|
| 764 |
|
|
.avl_be_5 (1'b0), // (terminated)
|
| 765 |
|
|
.avl_read_req_5 (1'b0), // (terminated)
|
| 766 |
|
|
.avl_write_req_5 (1'b0), // (terminated)
|
| 767 |
|
|
.avl_size_5 (3'b000), // (terminated)
|
| 768 |
|
|
.csr_write_req (1'b0), // (terminated)
|
| 769 |
|
|
.csr_read_req (1'b0), // (terminated)
|
| 770 |
|
|
.csr_waitrequest (), // (terminated)
|
| 771 |
|
|
.csr_addr (10'b0000000000), // (terminated)
|
| 772 |
|
|
.csr_be (1'b0), // (terminated)
|
| 773 |
|
|
.csr_wdata (8'b00000000), // (terminated)
|
| 774 |
|
|
.csr_rdata (), // (terminated)
|
| 775 |
|
|
.csr_rdata_valid (), // (terminated)
|
| 776 |
|
|
.local_multicast (1'b0), // (terminated)
|
| 777 |
|
|
.local_refresh_req (1'b0), // (terminated)
|
| 778 |
|
|
.local_refresh_chip (1'b0), // (terminated)
|
| 779 |
|
|
.local_refresh_ack (), // (terminated)
|
| 780 |
|
|
.local_self_rfsh_req (1'b0), // (terminated)
|
| 781 |
|
|
.local_self_rfsh_chip (1'b0), // (terminated)
|
| 782 |
|
|
.local_self_rfsh_ack (), // (terminated)
|
| 783 |
|
|
.local_deep_powerdn_req (1'b0), // (terminated)
|
| 784 |
|
|
.local_deep_powerdn_chip (1'b0), // (terminated)
|
| 785 |
|
|
.local_deep_powerdn_ack (), // (terminated)
|
| 786 |
|
|
.local_powerdn_ack (), // (terminated)
|
| 787 |
|
|
.local_priority (1'b0), // (terminated)
|
| 788 |
|
|
.bonding_in_1 (4'b0000), // (terminated)
|
| 789 |
|
|
.bonding_in_2 (6'b000000), // (terminated)
|
| 790 |
|
|
.bonding_in_3 (6'b000000), // (terminated)
|
| 791 |
|
|
.bonding_out_1 (), // (terminated)
|
| 792 |
|
|
.bonding_out_2 (), // (terminated)
|
| 793 |
|
|
.bonding_out_3 () // (terminated)
|
| 794 |
|
|
);
|
| 795 |
|
|
|
| 796 |
|
|
altera_mem_if_oct_cyclonev #(
|
| 797 |
|
|
.OCT_TERM_CONTROL_WIDTH (16)
|
| 798 |
|
|
) oct (
|
| 799 |
|
|
.oct_rzqin (oct_rzqin), // oct.rzqin
|
| 800 |
|
|
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
|
| 801 |
|
|
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
|
| 802 |
|
|
);
|
| 803 |
|
|
|
| 804 |
|
|
altera_mem_if_dll_cyclonev #(
|
| 805 |
|
|
.DLL_DELAY_CTRL_WIDTH (7),
|
| 806 |
|
|
.DLL_OFFSET_CTRL_WIDTH (6),
|
| 807 |
|
|
.DELAY_BUFFER_MODE ("HIGH"),
|
| 808 |
|
|
.DELAY_CHAIN_LENGTH (8),
|
| 809 |
|
|
.DLL_INPUT_FREQUENCY_PS_STR ("3333 ps")
|
| 810 |
|
|
) dll (
|
| 811 |
|
|
.clk (p0_dll_clk_clk), // clk.clk
|
| 812 |
|
|
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
|
| 813 |
|
|
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
|
| 814 |
|
|
);
|
| 815 |
|
|
|
| 816 |
|
|
endmodule
|
