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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [hps_sdram_p0_clock_pair_generator.v] - Blame information for rev 32

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1 32 redbear 
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
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//VERSION_BEGIN 17.0 cbx_altiobuf_out 2017:06:01:09:22:16:SJ cbx_mgl 2017:06:01:10:52:00:SJ cbx_stratixiii 2017:06:01:09:22:16:SJ cbx_stratixv 2017:06:01:09:22:16:SJ  VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2017  Intel Corporation. All rights reserved.
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//  Your use of Intel Corporation's design tools, logic functions
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//  and other software and tools, and its AMPP partner logic
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//  functions, and any output files from any of the foregoing
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//  (including device programming or simulation files), and any
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//  associated documentation or information are expressly subject
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//  to the terms and conditions of the Intel Program License
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//  Subscription Agreement, the Intel Quartus Prime License Agreement,
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//  the Intel MegaCore Function License Agreement, or other
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//  applicable license agreement, including, without limitation,
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//  that your use is for the sole purpose of programming logic
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//  devices manufactured by Intel and sold by Intel or its
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//  authorized distributors.  Please refer to the applicable
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//  agreement for further details.
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//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module  hps_sdram_p0_clock_pair_generator
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        (
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        datain,
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        dataout,
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        dataout_b) /* synthesis synthesis_clearbox=1 */;
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        input   [0:0]  datain;
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        output   [0:0]  dataout;
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        output   [0:0]  dataout_b;
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        wire  [0:0]   wire_obuf_ba_o;
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        wire  [0:0]   wire_obuf_ba_oe;
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        wire  [0:0]   wire_obufa_o;
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        wire  [0:0]   wire_obufa_oe;
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        wire  [0:0]   wire_pseudo_diffa_o;
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        wire  [0:0]   wire_pseudo_diffa_obar;
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        wire  [0:0]   wire_pseudo_diffa_oebout;
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        wire  [0:0]   wire_pseudo_diffa_oein;
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        wire  [0:0]   wire_pseudo_diffa_oeout;
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        wire  [0:0]  oe_w;
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        cyclonev_io_obuf   obuf_ba_0
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        (
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        .i(wire_pseudo_diffa_obar),
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        .o(wire_obuf_ba_o[0:0]),
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        .obar(),
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        .oe(wire_obuf_ba_oe[0:0])
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_off
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        `endif
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        ,
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        .dynamicterminationcontrol(1'b0),
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        .parallelterminationcontrol({16{1'b0}}),
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        .seriesterminationcontrol({16{1'b0}})
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_on
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        `endif
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        // synopsys translate_off
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        ,
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        .devoe(1'b1)
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        // synopsys translate_on
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        );
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        defparam
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                obuf_ba_0.bus_hold = "false",
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                obuf_ba_0.open_drain_output = "false",
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                obuf_ba_0.lpm_type = "cyclonev_io_obuf";
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        assign
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                wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
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        cyclonev_io_obuf   obufa_0
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        (
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        .i(wire_pseudo_diffa_o),
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        .o(wire_obufa_o[0:0]),
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        .obar(),
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        .oe(wire_obufa_oe[0:0])
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_off
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        `endif
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        ,
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        .dynamicterminationcontrol(1'b0),
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        .parallelterminationcontrol({16{1'b0}}),
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        .seriesterminationcontrol({16{1'b0}})
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_on
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        `endif
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        // synopsys translate_off
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        ,
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        .devoe(1'b1)
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        // synopsys translate_on
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        );
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        defparam
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                obufa_0.bus_hold = "false",
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                obufa_0.open_drain_output = "false",
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                obufa_0.lpm_type = "cyclonev_io_obuf";
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        assign
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                wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
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        cyclonev_pseudo_diff_out   pseudo_diffa_0
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        (
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        .dtc(),
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        .dtcbar(),
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        .i(datain),
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        .o(wire_pseudo_diffa_o[0:0]),
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        .obar(wire_pseudo_diffa_obar[0:0]),
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        .oebout(wire_pseudo_diffa_oebout[0:0]),
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        .oein(wire_pseudo_diffa_oein[0:0]),
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        .oeout(wire_pseudo_diffa_oeout[0:0])
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_off
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        `endif
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        ,
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        .dtcin(1'b0)
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_on
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        `endif
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        );
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        assign
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                wire_pseudo_diffa_oein = {(~ oe_w[0])};
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        assign
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                dataout = wire_obufa_o,
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                dataout_b = wire_obuf_ba_o,
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                oe_w = 1'b1;
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endmodule //hps_sdram_p0_clock_pair_generator
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//VALID FILE

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