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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [sequencer/] [sequencer_defines.pre.h] - Blame information for rev 40

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1 32 redbear 
/*
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Copyright (C) 2016 Intel Corporation
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All rights reserved.
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SPDX-License-Identifier:    BSD-3-Clause
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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    * Redistributions of source code must retain the above copyright
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      notice, this list of conditions and the following disclaimer.
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    * Redistributions in binary form must reproduce the above copyright
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      notice, this list of conditions and the following disclaimer in the
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      documentation and/or other materials provided with the distribution.
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    * Neither the name of Altera Corporation nor the
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      names of its contributors may be used to endorse or promote products
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      derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SEQUENCER_DEFINES_H_
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#define _SEQUENCER_DEFINES_H_
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#define AC_ROM_MR1_MIRR 0000000000000
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#define AC_ROM_MR1_OCD_ENABLE
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#define AC_ROM_MR2_MIRR 0000000010000
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#define AC_ROM_MR3_MIRR 0000000000000
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#define AC_ROM_MR0_CALIB
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#define AC_ROM_MR0_DLL_RESET_MIRR 0001011001000
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#define AC_ROM_MR0_DLL_RESET 0001100110000
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#define AC_ROM_MR0_MIRR 0001001001001
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#define AC_ROM_MR0 0001000110001
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#define AC_ROM_MR1 0000000000000
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#define AC_ROM_MR2 0000000001000
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#define AC_ROM_MR3 0000000000000
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#define AC_ROM_USER_ADD_0 0_0000_0000_0000
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#define AC_ROM_USER_ADD_1 0_0000_0000_1000
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#define AFI_CLK_FREQ 301
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#define AFI_RATE_RATIO 1
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#define AP_MODE 0
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#define ARRIAVGZ 0
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#define ARRIAV 0
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#define AVL_CLK_FREQ 61
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#define BFM_MODE 0
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#define BURST2 0
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#define CALIBRATE_BIT_SLIPS 0
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#define CALIB_LFIFO_OFFSET 8
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#define CALIB_VFIFO_OFFSET 6
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#define CYCLONEV 1
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#define DDR2 0
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#define DDR3 1
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#define DDRX 1
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#define DM_PINS_ENABLED 1
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#define ENABLE_ASSERT 0
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#define ENABLE_BRINGUP_DEBUGGING 0
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#define ENABLE_DELAY_CHAIN_WRITE 0
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#define ENABLE_DQS_IN_CENTERING 1
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#define ENABLE_DQS_OUT_CENTERING 0
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#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
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#define ENABLE_INST_ROM_WRITE 1
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#define ENABLE_MARGIN_REPORT_GEN 0
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#define ENABLE_NON_DESTRUCTIVE_CALIB 0
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#define ENABLE_NON_DES_CAL_TEST 0
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#define ENABLE_NON_DES_CAL 0
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#define ENABLE_SUPER_QUICK_CALIBRATION 0
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#define ENABLE_TCL_DEBUG 0
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#define FAKE_CAL_FAIL 0
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#define FIX_READ_LATENCY 8
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#define FULL_RATE 1
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#define GUARANTEED_READ_BRINGUP_TEST 0
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#define HALF_RATE 0
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#define HARD_PHY 1
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#define HARD_VFIFO 1
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#define HCX_COMPAT_MODE 0
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#define HHP_HPS_SIMULATION 0
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#define HHP_HPS_VERIFICATION 0
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#define HHP_HPS 1
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#define HPS_HW 1
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#define HR_DDIO_OUT_HAS_THREE_REGS 0
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#define IO_DELAY_PER_DCHAIN_TAP 25
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#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
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#define IO_DELAY_PER_OPA_TAP 416
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#define IO_DLL_CHAIN_LENGTH 8
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#define IO_DM_OUT_RESERVE 0
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#define IO_DQDQS_OUT_PHASE_MAX 0
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#define IO_DQS_EN_DELAY_MAX 31
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#define IO_DQS_EN_DELAY_OFFSET 0
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#define IO_DQS_EN_PHASE_MAX 7
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#define IO_DQS_IN_DELAY_MAX 31
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#define IO_DQS_IN_RESERVE 4
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#define IO_DQS_OUT_RESERVE 4
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#define IO_DQ_OUT_RESERVE 0
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#define IO_IO_IN_DELAY_MAX 31
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#define IO_IO_OUT1_DELAY_MAX 31
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#define IO_IO_OUT2_DELAY_MAX 0
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#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
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#define LPDDR1 0
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#define LPDDR2 0
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#define LRDIMM 0
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#define MARGIN_VARIATION_TEST 0
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#define MAX_LATENCY_COUNT_WIDTH 5
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#define MEM_ADDR_WIDTH 13
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#define MRS_MIRROR_PING_PONG_ATSO 0
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#define MULTIPLE_AFI_WLAT 0
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#define NON_DES_CAL 0
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#define NUM_SHADOW_REGS 1
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#define QDRII 0
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#define QUARTER_RATE 0
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#define RDIMM 0
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#define READ_AFTER_WRITE_CALIBRATION 1
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#define READ_VALID_FIFO_SIZE 16
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#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504ab
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#define RLDRAM3 0
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#define RLDRAMII 0
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#define RLDRAMX 0
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#define RUNTIME_CAL_REPORT 0
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#define RW_MGR_MEM_ADDRESS_MIRRORING 0
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#define RW_MGR_MEM_ADDRESS_WIDTH 13
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#define RW_MGR_MEM_BANK_WIDTH 3
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#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
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#define RW_MGR_MEM_CLK_EN_WIDTH 1
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#define RW_MGR_MEM_CONTROL_WIDTH 1
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#define RW_MGR_MEM_DATA_MASK_WIDTH 1
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#define RW_MGR_MEM_DATA_WIDTH 8
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#define RW_MGR_MEM_DQ_PER_READ_DQS 8
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#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
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#define RW_MGR_MEM_IF_READ_DQS_WIDTH 1
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#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 1
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#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
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#define RW_MGR_MEM_NUMBER_OF_RANKS 1
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#define RW_MGR_MEM_ODT_WIDTH 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
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#define RW_MGR_MR0_BL 1
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#define RW_MGR_MR0_CAS_LATENCY 3
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#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 1
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#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
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#define SET_FIX_READ_LATENCY_ENABLE 0
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#define SKEW_CALIBRATION 0
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#define SKIP_PTAP_0_DQS_EN_CAL 1
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#define STATIC_FULL_CALIBRATION 1
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#define STATIC_SIM_FILESET 0
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#define STATIC_SKIP_MEM_INIT 0
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#define STRATIXV 0
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#define TINIT_CNTR1_VAL 32
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#define TINIT_CNTR2_VAL 32
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#define TINIT_CNTR0_VAL 74
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#define TRACKING_ERROR_TEST 0
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#define TRACKING_WATCH_TEST 0
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#define TRESET_CNTR1_VAL 99
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#define TRESET_CNTR2_VAL 10
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#define TRESET_CNTR0_VAL 74
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#define USE_DQS_TRACKING 1
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#define USE_SHADOW_REGS 0
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#define USE_USER_RDIMM_VALUE 0
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#endif /* _SEQUENCER_DEFINES_H_ */

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