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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_hps_0_fpga_interfaces.sv] - Blame information for rev 40

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// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors.  Please refer to the applicable
// agreement for further details.
 
 
module ulight_fifo_hps_0_fpga_interfaces(
// h2f_reset
  output wire [1 - 1 : 0 ] h2f_rst_n
// h2f_axi_clock
 ,input wire [1 - 1 : 0 ] h2f_axi_clk
// h2f_axi_master
 ,output wire [12 - 1 : 0 ] h2f_AWID
 ,output wire [30 - 1 : 0 ] h2f_AWADDR
 ,output wire [4 - 1 : 0 ] h2f_AWLEN
 ,output wire [3 - 1 : 0 ] h2f_AWSIZE
 ,output wire [2 - 1 : 0 ] h2f_AWBURST
 ,output wire [2 - 1 : 0 ] h2f_AWLOCK
 ,output wire [4 - 1 : 0 ] h2f_AWCACHE
 ,output wire [3 - 1 : 0 ] h2f_AWPROT
 ,output wire [1 - 1 : 0 ] h2f_AWVALID
 ,input wire [1 - 1 : 0 ] h2f_AWREADY
 ,output wire [12 - 1 : 0 ] h2f_WID
 ,output wire [32 - 1 : 0 ] h2f_WDATA
 ,output wire [4 - 1 : 0 ] h2f_WSTRB
 ,output wire [1 - 1 : 0 ] h2f_WLAST
 ,output wire [1 - 1 : 0 ] h2f_WVALID
 ,input wire [1 - 1 : 0 ] h2f_WREADY
 ,input wire [12 - 1 : 0 ] h2f_BID
 ,input wire [2 - 1 : 0 ] h2f_BRESP
 ,input wire [1 - 1 : 0 ] h2f_BVALID
 ,output wire [1 - 1 : 0 ] h2f_BREADY
 ,output wire [12 - 1 : 0 ] h2f_ARID
 ,output wire [30 - 1 : 0 ] h2f_ARADDR
 ,output wire [4 - 1 : 0 ] h2f_ARLEN
 ,output wire [3 - 1 : 0 ] h2f_ARSIZE
 ,output wire [2 - 1 : 0 ] h2f_ARBURST
 ,output wire [2 - 1 : 0 ] h2f_ARLOCK
 ,output wire [4 - 1 : 0 ] h2f_ARCACHE
 ,output wire [3 - 1 : 0 ] h2f_ARPROT
 ,output wire [1 - 1 : 0 ] h2f_ARVALID
 ,input wire [1 - 1 : 0 ] h2f_ARREADY
 ,input wire [12 - 1 : 0 ] h2f_RID
 ,input wire [32 - 1 : 0 ] h2f_RDATA
 ,input wire [2 - 1 : 0 ] h2f_RRESP
 ,input wire [1 - 1 : 0 ] h2f_RLAST
 ,input wire [1 - 1 : 0 ] h2f_RVALID
 ,output wire [1 - 1 : 0 ] h2f_RREADY
);
 
 
cyclonev_hps_interface_clocks_resets clocks_resets(
 .f2h_pending_rst_ack({
    1'b1 // 0:0
  })
,.f2h_warm_rst_req_n({
    1'b1 // 0:0
  })
,.f2h_dbg_rst_req_n({
    1'b1 // 0:0
  })
,.h2f_rst_n({
    h2f_rst_n[0:0] // 0:0
  })
,.f2h_cold_rst_req_n({
    1'b1 // 0:0
  })
);
 
 
cyclonev_hps_interface_dbg_apb debug_apb(
 .DBG_APB_DISABLE({
    1'b0 // 0:0
  })
,.P_CLK_EN({
    1'b0 // 0:0
  })
);
 
 
cyclonev_hps_interface_tpiu_trace tpiu(
 .traceclk_ctl({
    1'b1 // 0:0
  })
);
 
 
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
 .boot_from_fpga_ready({
    1'b0 // 0:0
  })
,.boot_from_fpga_on_failure({
    1'b0 // 0:0
  })
,.bsel_en({
    1'b0 // 0:0
  })
,.csel_en({
    1'b0 // 0:0
  })
,.csel({
    2'b01 // 1:0
  })
,.bsel({
    3'b001 // 2:0
  })
);
 
 
cyclonev_hps_interface_fpga2hps fpga2hps(
 .port_size_config({
    2'b11 // 1:0
  })
);
 
 
cyclonev_hps_interface_hps2fpga hps2fpga(
 .port_size_config({
    2'b00 // 1:0
  })
,.arsize({
    h2f_ARSIZE[2:0] // 2:0
  })
,.wvalid({
    h2f_WVALID[0:0] // 0:0
  })
,.rlast({
    h2f_RLAST[0:0] // 0:0
  })
,.clk({
    h2f_axi_clk[0:0] // 0:0
  })
,.rresp({
    h2f_RRESP[1:0] // 1:0
  })
,.arready({
    h2f_ARREADY[0:0] // 0:0
  })
,.arprot({
    h2f_ARPROT[2:0] // 2:0
  })
,.araddr({
    h2f_ARADDR[29:0] // 29:0
  })
,.bvalid({
    h2f_BVALID[0:0] // 0:0
  })
,.arid({
    h2f_ARID[11:0] // 11:0
  })
,.bid({
    h2f_BID[11:0] // 11:0
  })
,.arburst({
    h2f_ARBURST[1:0] // 1:0
  })
,.arcache({
    h2f_ARCACHE[3:0] // 3:0
  })
,.awvalid({
    h2f_AWVALID[0:0] // 0:0
  })
,.wdata({
    h2f_WDATA[31:0] // 31:0
  })
,.rid({
    h2f_RID[11:0] // 11:0
  })
,.rvalid({
    h2f_RVALID[0:0] // 0:0
  })
,.wready({
    h2f_WREADY[0:0] // 0:0
  })
,.awlock({
    h2f_AWLOCK[1:0] // 1:0
  })
,.bresp({
    h2f_BRESP[1:0] // 1:0
  })
,.arlen({
    h2f_ARLEN[3:0] // 3:0
  })
,.awsize({
    h2f_AWSIZE[2:0] // 2:0
  })
,.awlen({
    h2f_AWLEN[3:0] // 3:0
  })
,.bready({
    h2f_BREADY[0:0] // 0:0
  })
,.awid({
    h2f_AWID[11:0] // 11:0
  })
,.rdata({
    h2f_RDATA[31:0] // 31:0
  })
,.awready({
    h2f_AWREADY[0:0] // 0:0
  })
,.arvalid({
    h2f_ARVALID[0:0] // 0:0
  })
,.wlast({
    h2f_WLAST[0:0] // 0:0
  })
,.awprot({
    h2f_AWPROT[2:0] // 2:0
  })
,.awaddr({
    h2f_AWADDR[29:0] // 29:0
  })
,.wid({
    h2f_WID[11:0] // 11:0
  })
,.awcache({
    h2f_AWCACHE[3:0] // 3:0
  })
,.arlock({
    h2f_ARLOCK[1:0] // 1:0
  })
,.awburst({
    h2f_AWBURST[1:0] // 1:0
  })
,.rready({
    h2f_RREADY[0:0] // 0:0
  })
,.wstrb({
    h2f_WSTRB[3:0] // 3:0
  })
);
 
 
cyclonev_hps_interface_fpga2sdram f2sdram(
 .cfg_cport_rfifo_map({
    18'b000000000000000000 // 17:0
  })
,.cfg_axi_mm_select({
    6'b000000 // 5:0
  })
,.cfg_wfifo_cport_map({
    16'b0000000000000000 // 15:0
  })
,.cfg_cport_type({
    12'b000000000000 // 11:0
  })
,.cfg_rfifo_cport_map({
    16'b0000000000000000 // 15:0
  })
,.cfg_port_width({
    12'b000000000000 // 11:0
  })
,.cfg_cport_wfifo_map({
    18'b000000000000000000 // 17:0
  })
);
 
endmodule
 

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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_hps_0_fpga_interfaces.sv] - Blame information for rev 40

Line No.	Rev	Author	Line
1	32	redbear	`// (C) 2001-2017 Intel Corporation. All rights reserved.`
2			`// Your use of Intel Corporation's design tools, logic functions and other`
3			`// software and tools, and its AMPP partner logic functions, and any output`
4	40	redbear	`// files from any of the foregoing (including device programming or simulation`
5	32	redbear	`// files), and any associated documentation or information are expressly subject`
6			`// to the terms and conditions of the Intel Program License Subscription`
7	40	redbear	`// Agreement, Intel FPGA IP License Agreement, or other applicable`
8	32	redbear	`// license agreement, including, without limitation, that your use is for the`
9			`// sole purpose of programming logic devices manufactured by Intel and sold by`
10			`// Intel or its authorized distributors. Please refer to the applicable`
11			`// agreement for further details.`
12
13
14			`module ulight_fifo_hps_0_fpga_interfaces(`
15			`// h2f_reset`
16			`output wire [1 - 1 : 0 ] h2f_rst_n`
17			`// h2f_axi_clock`
18			`,input wire [1 - 1 : 0 ] h2f_axi_clk`
19			`// h2f_axi_master`
20			`,output wire [12 - 1 : 0 ] h2f_AWID`
21			`,output wire [30 - 1 : 0 ] h2f_AWADDR`
22			`,output wire [4 - 1 : 0 ] h2f_AWLEN`
23			`,output wire [3 - 1 : 0 ] h2f_AWSIZE`
24			`,output wire [2 - 1 : 0 ] h2f_AWBURST`
25			`,output wire [2 - 1 : 0 ] h2f_AWLOCK`
26			`,output wire [4 - 1 : 0 ] h2f_AWCACHE`
27			`,output wire [3 - 1 : 0 ] h2f_AWPROT`
28			`,output wire [1 - 1 : 0 ] h2f_AWVALID`
29			`,input wire [1 - 1 : 0 ] h2f_AWREADY`
30			`,output wire [12 - 1 : 0 ] h2f_WID`
31			`,output wire [32 - 1 : 0 ] h2f_WDATA`
32			`,output wire [4 - 1 : 0 ] h2f_WSTRB`
33			`,output wire [1 - 1 : 0 ] h2f_WLAST`
34			`,output wire [1 - 1 : 0 ] h2f_WVALID`
35			`,input wire [1 - 1 : 0 ] h2f_WREADY`
36			`,input wire [12 - 1 : 0 ] h2f_BID`
37			`,input wire [2 - 1 : 0 ] h2f_BRESP`
38			`,input wire [1 - 1 : 0 ] h2f_BVALID`
39			`,output wire [1 - 1 : 0 ] h2f_BREADY`
40			`,output wire [12 - 1 : 0 ] h2f_ARID`
41			`,output wire [30 - 1 : 0 ] h2f_ARADDR`
42			`,output wire [4 - 1 : 0 ] h2f_ARLEN`
43			`,output wire [3 - 1 : 0 ] h2f_ARSIZE`
44			`,output wire [2 - 1 : 0 ] h2f_ARBURST`
45			`,output wire [2 - 1 : 0 ] h2f_ARLOCK`
46			`,output wire [4 - 1 : 0 ] h2f_ARCACHE`
47			`,output wire [3 - 1 : 0 ] h2f_ARPROT`
48			`,output wire [1 - 1 : 0 ] h2f_ARVALID`
49			`,input wire [1 - 1 : 0 ] h2f_ARREADY`
50			`,input wire [12 - 1 : 0 ] h2f_RID`
51			`,input wire [32 - 1 : 0 ] h2f_RDATA`
52			`,input wire [2 - 1 : 0 ] h2f_RRESP`
53			`,input wire [1 - 1 : 0 ] h2f_RLAST`
54			`,input wire [1 - 1 : 0 ] h2f_RVALID`
55			`,output wire [1 - 1 : 0 ] h2f_RREADY`
56			`);`
57
58
59			`cyclonev_hps_interface_clocks_resets clocks_resets(`
60			`.f2h_pending_rst_ack({`
61			`1'b1 // 0:0`
62			`})`
63			`,.f2h_warm_rst_req_n({`
64			`1'b1 // 0:0`
65			`})`
66			`,.f2h_dbg_rst_req_n({`
67			`1'b1 // 0:0`
68			`})`
69			`,.h2f_rst_n({`
70			`h2f_rst_n[0:0] // 0:0`
71			`})`
72			`,.f2h_cold_rst_req_n({`
73			`1'b1 // 0:0`
74			`})`
75			`);`
76
77
78			`cyclonev_hps_interface_dbg_apb debug_apb(`
79			`.DBG_APB_DISABLE({`
80			`1'b0 // 0:0`
81			`})`
82			`,.P_CLK_EN({`
83			`1'b0 // 0:0`
84			`})`
85			`);`
86
87
88			`cyclonev_hps_interface_tpiu_trace tpiu(`
89			`.traceclk_ctl({`
90			`1'b1 // 0:0`
91			`})`
92			`);`
93
94
95			`cyclonev_hps_interface_boot_from_fpga boot_from_fpga(`
96			`.boot_from_fpga_ready({`
97			`1'b0 // 0:0`
98			`})`
99			`,.boot_from_fpga_on_failure({`
100			`1'b0 // 0:0`
101			`})`
102			`,.bsel_en({`
103			`1'b0 // 0:0`
104			`})`
105			`,.csel_en({`
106			`1'b0 // 0:0`
107			`})`
108			`,.csel({`
109			`2'b01 // 1:0`
110			`})`
111			`,.bsel({`
112			`3'b001 // 2:0`
113			`})`
114			`);`
115
116
117			`cyclonev_hps_interface_fpga2hps fpga2hps(`
118			`.port_size_config({`
119			`2'b11 // 1:0`
120			`})`
121			`);`
122
123
124			`cyclonev_hps_interface_hps2fpga hps2fpga(`
125			`.port_size_config({`
126			`2'b00 // 1:0`
127			`})`
128			`,.arsize({`
129			`h2f_ARSIZE[2:0] // 2:0`
130			`})`
131			`,.wvalid({`
132			`h2f_WVALID[0:0] // 0:0`
133			`})`
134			`,.rlast({`
135			`h2f_RLAST[0:0] // 0:0`
136			`})`
137			`,.clk({`
138			`h2f_axi_clk[0:0] // 0:0`
139			`})`
140			`,.rresp({`
141			`h2f_RRESP[1:0] // 1:0`
142			`})`
143			`,.arready({`
144			`h2f_ARREADY[0:0] // 0:0`
145			`})`
146			`,.arprot({`
147			`h2f_ARPROT[2:0] // 2:0`
148			`})`
149			`,.araddr({`
150			`h2f_ARADDR[29:0] // 29:0`
151			`})`
152			`,.bvalid({`
153			`h2f_BVALID[0:0] // 0:0`
154			`})`
155			`,.arid({`
156			`h2f_ARID[11:0] // 11:0`
157			`})`
158			`,.bid({`
159			`h2f_BID[11:0] // 11:0`
160			`})`
161			`,.arburst({`
162			`h2f_ARBURST[1:0] // 1:0`
163			`})`
164			`,.arcache({`
165			`h2f_ARCACHE[3:0] // 3:0`
166			`})`
167			`,.awvalid({`
168			`h2f_AWVALID[0:0] // 0:0`
169			`})`
170			`,.wdata({`
171			`h2f_WDATA[31:0] // 31:0`
172			`})`
173			`,.rid({`
174			`h2f_RID[11:0] // 11:0`
175			`})`
176			`,.rvalid({`
177			`h2f_RVALID[0:0] // 0:0`
178			`})`
179			`,.wready({`
180			`h2f_WREADY[0:0] // 0:0`
181			`})`
182			`,.awlock({`
183			`h2f_AWLOCK[1:0] // 1:0`
184			`})`
185			`,.bresp({`
186			`h2f_BRESP[1:0] // 1:0`
187			`})`
188			`,.arlen({`
189			`h2f_ARLEN[3:0] // 3:0`
190			`})`
191			`,.awsize({`
192			`h2f_AWSIZE[2:0] // 2:0`
193			`})`
194			`,.awlen({`
195			`h2f_AWLEN[3:0] // 3:0`
196			`})`
197			`,.bready({`
198			`h2f_BREADY[0:0] // 0:0`
199			`})`
200			`,.awid({`
201			`h2f_AWID[11:0] // 11:0`
202			`})`
203			`,.rdata({`
204			`h2f_RDATA[31:0] // 31:0`
205			`})`
206			`,.awready({`
207			`h2f_AWREADY[0:0] // 0:0`
208			`})`
209			`,.arvalid({`
210			`h2f_ARVALID[0:0] // 0:0`
211			`})`
212			`,.wlast({`
213			`h2f_WLAST[0:0] // 0:0`
214			`})`
215			`,.awprot({`
216			`h2f_AWPROT[2:0] // 2:0`
217			`})`
218			`,.awaddr({`
219			`h2f_AWADDR[29:0] // 29:0`
220			`})`
221			`,.wid({`
222			`h2f_WID[11:0] // 11:0`
223			`})`
224			`,.awcache({`
225			`h2f_AWCACHE[3:0] // 3:0`
226			`})`
227			`,.arlock({`
228			`h2f_ARLOCK[1:0] // 1:0`
229			`})`
230			`,.awburst({`
231			`h2f_AWBURST[1:0] // 1:0`
232			`})`
233			`,.rready({`
234			`h2f_RREADY[0:0] // 0:0`
235			`})`
236			`,.wstrb({`
237			`h2f_WSTRB[3:0] // 3:0`
238			`})`
239			`);`
240
241
242			`cyclonev_hps_interface_fpga2sdram f2sdram(`
243			`.cfg_cport_rfifo_map({`
244			`18'b000000000000000000 // 17:0`
245			`})`
246			`,.cfg_axi_mm_select({`
247			`6'b000000 // 5:0`
248			`})`
249			`,.cfg_wfifo_cport_map({`
250			`16'b0000000000000000 // 15:0`
251			`})`
252			`,.cfg_cport_type({`
253			`12'b000000000000 // 11:0`
254			`})`
255			`,.cfg_rfifo_cport_map({`
256			`16'b0000000000000000 // 15:0`
257			`})`
258			`,.cfg_port_width({`
259			`12'b000000000000 // 11:0`
260			`})`
261			`,.cfg_cport_wfifo_map({`
262			`18'b000000000000000000 // 17:0`
263			`})`
264			`);`
265
266			`endmodule`
267