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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_hps_0_hps_io.v] - Blame information for rev 40

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1 32 redbear 
// ulight_fifo_hps_0_hps_io.v
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// This file was auto-generated from altera_hps_io_hw.tcl.  If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 17.1 593
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`timescale 1 ps / 1 ps
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module ulight_fifo_hps_0_hps_io (
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                output wire [12:0] mem_a,       // memory.mem_a
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                output wire [2:0]  mem_ba,      //       .mem_ba
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                output wire        mem_ck,      //       .mem_ck
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                output wire        mem_ck_n,    //       .mem_ck_n
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                output wire        mem_cke,     //       .mem_cke
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                output wire        mem_cs_n,    //       .mem_cs_n
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                output wire        mem_ras_n,   //       .mem_ras_n
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                output wire        mem_cas_n,   //       .mem_cas_n
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                output wire        mem_we_n,    //       .mem_we_n
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                output wire        mem_reset_n, //       .mem_reset_n
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                inout  wire [7:0]  mem_dq,      //       .mem_dq
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                inout  wire        mem_dqs,     //       .mem_dqs
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                inout  wire        mem_dqs_n,   //       .mem_dqs_n
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                output wire        mem_odt,     //       .mem_odt
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                output wire        mem_dm,      //       .mem_dm
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                input  wire        oct_rzqin    //       .oct_rzqin
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        );
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        ulight_fifo_hps_0_hps_io_border border (
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                .mem_a       (mem_a),       // memory.mem_a
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                .mem_ba      (mem_ba),      //       .mem_ba
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                .mem_ck      (mem_ck),      //       .mem_ck
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                .mem_ck_n    (mem_ck_n),    //       .mem_ck_n
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                .mem_cke     (mem_cke),     //       .mem_cke
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                .mem_cs_n    (mem_cs_n),    //       .mem_cs_n
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                .mem_ras_n   (mem_ras_n),   //       .mem_ras_n
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                .mem_cas_n   (mem_cas_n),   //       .mem_cas_n
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                .mem_we_n    (mem_we_n),    //       .mem_we_n
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                .mem_reset_n (mem_reset_n), //       .mem_reset_n
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                .mem_dq      (mem_dq),      //       .mem_dq
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                .mem_dqs     (mem_dqs),     //       .mem_dqs
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                .mem_dqs_n   (mem_dqs_n),   //       .mem_dqs_n
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                .mem_odt     (mem_odt),     //       .mem_odt
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                .mem_dm      (mem_dm),      //       .mem_dm
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                .oct_rzqin   (oct_rzqin)    //       .oct_rzqin
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        );
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endmodule

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