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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_mm_interconnect_0_router.sv] - Blame information for rev 40

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1 32 redbear
// (C) 2001-2017 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other
3
// software and tools, and its AMPP partner logic functions, and any output
4 40 redbear
// files from any of the foregoing (including device programming or simulation
5 32 redbear
// files), and any associated documentation or information are expressly subject
6
// to the terms and conditions of the Intel Program License Subscription
7 40 redbear
// Agreement, Intel FPGA IP License Agreement, or other applicable
8 32 redbear
// license agreement, including, without limitation, that your use is for the
9
// sole purpose of programming logic devices manufactured by Intel and sold by
10
// Intel or its authorized distributors.  Please refer to the applicable
11
// agreement for further details.
12
 
13
 
14
 
15
// Your use of Altera Corporation's design tools, logic functions and other
16
// software and tools, and its AMPP partner logic functions, and any output
17
// files any of the foregoing (including device programming or simulation
18
// files), and any associated documentation or information are expressly subject
19
// to the terms and conditions of the Altera Program License Subscription
20
// Agreement, Altera MegaCore Function License Agreement, or other applicable
21
// license agreement, including, without limitation, that your use is for the
22
// sole purpose of programming logic devices manufactured by Altera and sold by
23
// Altera or its authorized distributors.  Please refer to the applicable
24
// agreement for further details.
25
 
26
 
27 40 redbear
// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
28 32 redbear
// $Revision: #1 $
29 40 redbear
// $Date: 2017/07/30 $
30 32 redbear
// $Author: swbranch $
31
 
32
// -------------------------------------------------------
33
// Merlin Router
34
//
35
// Asserts the appropriate one-hot encoded channel based on
36
// either (a) the address or (b) the dest id. The DECODER_TYPE
37
// parameter controls this behaviour. 0 means address decoder,
38
// 1 means dest id decoder.
39
//
40
// In the case of (a), it also sets the destination id.
41
// -------------------------------------------------------
42
 
43
`timescale 1 ns / 1 ns
44
 
45
module ulight_fifo_mm_interconnect_0_router_default_decode
46
  #(
47
     parameter DEFAULT_CHANNEL = 0,
48
               DEFAULT_WR_CHANNEL = -1,
49
               DEFAULT_RD_CHANNEL = -1,
50
               DEFAULT_DESTID = 12
51
   )
52
  (output [104 - 100 : 0] default_destination_id,
53
   output [22-1 : 0] default_wr_channel,
54
   output [22-1 : 0] default_rd_channel,
55
   output [22-1 : 0] default_src_channel
56
  );
57
 
58
  assign default_destination_id =
59
    DEFAULT_DESTID[104 - 100 : 0];
60
 
61
  generate
62
    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
63
      assign default_src_channel = '0;
64
    end
65
    else begin : default_channel_assignment
66
      assign default_src_channel = 22'b1 << DEFAULT_CHANNEL;
67
    end
68
  endgenerate
69
 
70
  generate
71
    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
72
      assign default_wr_channel = '0;
73
      assign default_rd_channel = '0;
74
    end
75
    else begin : default_rw_channel_assignment
76
      assign default_wr_channel = 22'b1 << DEFAULT_WR_CHANNEL;
77
      assign default_rd_channel = 22'b1 << DEFAULT_RD_CHANNEL;
78
    end
79
  endgenerate
80
 
81
endmodule
82
 
83
 
84
module ulight_fifo_mm_interconnect_0_router
85
(
86
    // -------------------
87
    // Clock & Reset
88
    // -------------------
89
    input clk,
90
    input reset,
91
 
92
    // -------------------
93
    // Command Sink (Input)
94
    // -------------------
95
    input                       sink_valid,
96
    input  [129-1 : 0]    sink_data,
97
    input                       sink_startofpacket,
98
    input                       sink_endofpacket,
99
    output                      sink_ready,
100
 
101
    // -------------------
102
    // Command Source (Output)
103
    // -------------------
104
    output                          src_valid,
105
    output reg [129-1    : 0] src_data,
106
    output reg [22-1 : 0] src_channel,
107
    output                          src_startofpacket,
108
    output                          src_endofpacket,
109
    input                           src_ready
110
);
111
 
112
    // -------------------------------------------------------
113
    // Local parameters and variables
114
    // -------------------------------------------------------
115
    localparam PKT_ADDR_H = 65;
116
    localparam PKT_ADDR_L = 36;
117
    localparam PKT_DEST_ID_H = 104;
118
    localparam PKT_DEST_ID_L = 100;
119
    localparam PKT_PROTECTION_H = 119;
120
    localparam PKT_PROTECTION_L = 117;
121
    localparam ST_DATA_W = 129;
122
    localparam ST_CHANNEL_W = 22;
123
    localparam DECODER_TYPE = 0;
124
 
125
    localparam PKT_TRANS_WRITE = 68;
126
    localparam PKT_TRANS_READ  = 69;
127
 
128
    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
129
    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
130
 
131
 
132
 
133
    // -------------------------------------------------------
134
    // Figure out the number of bits to mask off for each slave span
135
    // during address decoding
136
    // -------------------------------------------------------
137
    localparam PAD0 = log2ceil(64'h10 - 64'h0);
138
    localparam PAD1 = log2ceil(64'h10010 - 64'h10000);
139
    localparam PAD2 = log2ceil(64'h1a010 - 64'h1a000);
140
    localparam PAD3 = log2ceil(64'h20010 - 64'h20000);
141
    localparam PAD4 = log2ceil(64'h2a010 - 64'h2a000);
142
    localparam PAD5 = log2ceil(64'h30010 - 64'h30000);
143
    localparam PAD6 = log2ceil(64'h3a010 - 64'h3a000);
144
    localparam PAD7 = log2ceil(64'h40010 - 64'h40000);
145
    localparam PAD8 = log2ceil(64'h4a010 - 64'h4a000);
146
    localparam PAD9 = log2ceil(64'h50010 - 64'h50000);
147
    localparam PAD10 = log2ceil(64'h5a010 - 64'h5a000);
148
    localparam PAD11 = log2ceil(64'h60010 - 64'h60000);
149
    localparam PAD12 = log2ceil(64'h6a010 - 64'h6a000);
150
    localparam PAD13 = log2ceil(64'h70010 - 64'h70000);
151
    localparam PAD14 = log2ceil(64'h80010 - 64'h80000);
152
    localparam PAD15 = log2ceil(64'h90010 - 64'h90000);
153
    localparam PAD16 = log2ceil(64'ha0010 - 64'ha0000);
154
    localparam PAD17 = log2ceil(64'hb0010 - 64'hb0000);
155
    localparam PAD18 = log2ceil(64'hc0010 - 64'hc0000);
156
    localparam PAD19 = log2ceil(64'hd0010 - 64'hd0000);
157
    localparam PAD20 = log2ceil(64'he0010 - 64'he0000);
158
    localparam PAD21 = log2ceil(64'hf0010 - 64'hf0000);
159
    // -------------------------------------------------------
160
    // Work out which address bits are significant based on the
161
    // address range of the slaves. If the required width is too
162
    // large or too small, we use the address field width instead.
163
    // -------------------------------------------------------
164
    localparam ADDR_RANGE = 64'hf0010;
165
    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
166
    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
167
                                  (RANGE_ADDR_WIDTH == 0) ?
168
                                        PKT_ADDR_H :
169
                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
170
 
171
    localparam RG = RANGE_ADDR_WIDTH-1;
172
    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
173
 
174
      reg [PKT_ADDR_W-1 : 0] address;
175
      always @* begin
176
        address = {PKT_ADDR_W{1'b0}};
177
        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
178
      end
179
 
180
    // -------------------------------------------------------
181
    // Pass almost everything through, untouched
182
    // -------------------------------------------------------
183
    assign sink_ready        = src_ready;
184
    assign src_valid         = sink_valid;
185
    assign src_startofpacket = sink_startofpacket;
186
    assign src_endofpacket   = sink_endofpacket;
187
    wire [PKT_DEST_ID_W-1:0] default_destid;
188
    wire [22-1 : 0] default_src_channel;
189
 
190
 
191
 
192
 
193
    // -------------------------------------------------------
194
    // Write and read transaction signals
195
    // -------------------------------------------------------
196
    wire read_transaction;
197
    assign read_transaction  = sink_data[PKT_TRANS_READ];
198
 
199
 
200
    ulight_fifo_mm_interconnect_0_router_default_decode the_default_decode(
201
      .default_destination_id (default_destid),
202
      .default_wr_channel   (),
203
      .default_rd_channel   (),
204
      .default_src_channel  (default_src_channel)
205
    );
206
 
207
    always @* begin
208
        src_data    = sink_data;
209
        src_channel = default_src_channel;
210
        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
211
 
212
        // --------------------------------------------------
213
        // Address Decoder
214
        // Sets the channel and destination ID based on the address
215
        // --------------------------------------------------
216
 
217
    // ( 0x0 .. 0x10 )
218
    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h0   ) begin
219
            src_channel = 22'b0000000000000000000001;
220
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12;
221
    end
222
 
223
    // ( 0x10000 .. 0x10010 )
224
    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h10000  && read_transaction  ) begin
225
            src_channel = 22'b0000000000000000000010;
226
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16;
227
    end
228
 
229
    // ( 0x1a000 .. 0x1a010 )
230
    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 20'h1a000  && read_transaction  ) begin
231
            src_channel = 22'b0000010000000000000000;
232
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 19;
233
    end
234
 
235
    // ( 0x20000 .. 0x20010 )
236
    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 20'h20000  && read_transaction  ) begin
237
            src_channel = 22'b0000000000000000000100;
238
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15;
239
    end
240
 
241
    // ( 0x2a000 .. 0x2a010 )
242
    if ( {address[RG:PAD4],{PAD4{1'b0}}} == 20'h2a000  && read_transaction  ) begin
243
            src_channel = 22'b0000100000000000000000;
244
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
245
    end
246
 
247
    // ( 0x30000 .. 0x30010 )
248
    if ( {address[RG:PAD5],{PAD5{1'b0}}} == 20'h30000  && read_transaction  ) begin
249
            src_channel = 22'b0000000000000000001000;
250
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
251
    end
252
 
253
    // ( 0x3a000 .. 0x3a010 )
254
    if ( {address[RG:PAD6],{PAD6{1'b0}}} == 20'h3a000   ) begin
255
            src_channel = 22'b0001000000000000000000;
256
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
257
    end
258
 
259
    // ( 0x40000 .. 0x40010 )
260
    if ( {address[RG:PAD7],{PAD7{1'b0}}} == 20'h40000   ) begin
261
            src_channel = 22'b0000000000000000010000;
262
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
263
    end
264
 
265
    // ( 0x4a000 .. 0x4a010 )
266
    if ( {address[RG:PAD8],{PAD8{1'b0}}} == 20'h4a000  && read_transaction  ) begin
267
            src_channel = 22'b0010000000000000000000;
268
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11;
269
    end
270
 
271
    // ( 0x50000 .. 0x50010 )
272
    if ( {address[RG:PAD9],{PAD9{1'b0}}} == 20'h50000  && read_transaction  ) begin
273
            src_channel = 22'b0000000000000000100000;
274
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9;
275
    end
276
 
277
    // ( 0x5a000 .. 0x5a010 )
278
    if ( {address[RG:PAD10],{PAD10{1'b0}}} == 20'h5a000  && read_transaction  ) begin
279
            src_channel = 22'b0100000000000000000000;
280
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
281
    end
282
 
283
    // ( 0x60000 .. 0x60010 )
284
    if ( {address[RG:PAD11],{PAD11{1'b0}}} == 20'h60000  && read_transaction  ) begin
285
            src_channel = 22'b0000000000000001000000;
286
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7;
287
    end
288
 
289
    // ( 0x6a000 .. 0x6a010 )
290
    if ( {address[RG:PAD12],{PAD12{1'b0}}} == 20'h6a000  && read_transaction  ) begin
291
            src_channel = 22'b1000000000000000000000;
292
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
293
    end
294
 
295
    // ( 0x70000 .. 0x70010 )
296
    if ( {address[RG:PAD13],{PAD13{1'b0}}} == 20'h70000   ) begin
297
            src_channel = 22'b0000000000000010000000;
298
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14;
299
    end
300
 
301
    // ( 0x80000 .. 0x80010 )
302
    if ( {address[RG:PAD14],{PAD14{1'b0}}} == 20'h80000   ) begin
303
            src_channel = 22'b0000000000000100000000;
304
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
305
    end
306
 
307
    // ( 0x90000 .. 0x90010 )
308
    if ( {address[RG:PAD15],{PAD15{1'b0}}} == 20'h90000   ) begin
309
            src_channel = 22'b0000000000001000000000;
310
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13;
311
    end
312
 
313
    // ( 0xa0000 .. 0xa0010 )
314
    if ( {address[RG:PAD16],{PAD16{1'b0}}} == 20'ha0000   ) begin
315
            src_channel = 22'b0000000000010000000000;
316
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 20;
317
    end
318
 
319
    // ( 0xb0000 .. 0xb0010 )
320
    if ( {address[RG:PAD17],{PAD17{1'b0}}} == 20'hb0000   ) begin
321
            src_channel = 22'b0000000000100000000000;
322
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 21;
323
    end
324
 
325
    // ( 0xc0000 .. 0xc0010 )
326
    if ( {address[RG:PAD18],{PAD18{1'b0}}} == 20'hc0000  && read_transaction  ) begin
327
            src_channel = 22'b0000000001000000000000;
328
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10;
329
    end
330
 
331
    // ( 0xd0000 .. 0xd0010 )
332
    if ( {address[RG:PAD19],{PAD19{1'b0}}} == 20'hd0000  && read_transaction  ) begin
333
            src_channel = 22'b0000000010000000000000;
334
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8;
335
    end
336
 
337
    // ( 0xe0000 .. 0xe0010 )
338
    if ( {address[RG:PAD20],{PAD20{1'b0}}} == 20'he0000   ) begin
339
            src_channel = 22'b0000000100000000000000;
340
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17;
341
    end
342
 
343
    // ( 0xf0000 .. 0xf0010 )
344
    if ( {address[RG:PAD21],{PAD21{1'b0}}} == 20'hf0000   ) begin
345
            src_channel = 22'b0000001000000000000000;
346
            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 18;
347
    end
348
 
349
end
350
 
351
 
352
    // --------------------------------------------------
353
    // Ceil(log2()) function
354
    // --------------------------------------------------
355
    function integer log2ceil;
356
        input reg[65:0] val;
357
        reg [65:0] i;
358
 
359
        begin
360
            i = 1;
361
            log2ceil = 0;
362
 
363
            while (i < val) begin
364
                log2ceil = log2ceil + 1;
365
                i = i << 1;
366
            end
367
        end
368
    endfunction
369
 
370
endmodule
371
 
372
 

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