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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo/] [synthesis/] [submodules/] [ulight_fifo_write_data_fifo_tx.v] - Blame information for rev 40

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1 40 redbear
//Legal Notice: (C)2018 Altera Corporation. All rights reserved.  Your
2 32 redbear
//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors.  Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings 
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// altera message_level Level1 
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// altera message_off 10034 10035 10036 10037 10230 10240 10030 
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module ulight_fifo_write_data_fifo_tx (
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                                        // inputs:
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                                         address,
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                                         chipselect,
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                                         clk,
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                                         reset_n,
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                                         write_n,
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                                         writedata,
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                                        // outputs:
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                                         out_port,
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                                         readdata
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                                      )
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;
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  output  [  8: 0] out_port;
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  output  [ 31: 0] readdata;
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  input   [  1: 0] address;
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  input            chipselect;
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  input            clk;
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  input            reset_n;
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  input            write_n;
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  input   [ 31: 0] writedata;
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wire             clk_en;
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reg     [  8: 0] data_out;
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wire    [  8: 0] out_port;
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wire    [  8: 0] read_mux_out;
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wire    [ 31: 0] readdata;
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  assign clk_en = 1;
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  //s1, which is an e_avalon_slave
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  assign read_mux_out = {9 {(address == 0)}} & data_out;
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  always @(posedge clk or negedge reset_n)
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    begin
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      if (reset_n == 0)
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          data_out <= 0;
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      else if (chipselect && ~write_n && (address == 0))
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          data_out <= writedata[8 : 0];
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    end
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  assign readdata = {32'b0 | read_mux_out};
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  assign out_port = data_out;
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endmodule
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