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redbear |
Info: Starting: Create simulation model
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| 2 |
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Info: qsys-generate /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation --family="Cyclone V" --part=5CSEMA4U23C6
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| 3 |
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Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
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| 4 |
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Progress: Reading input file
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| 5 |
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Progress: Adding auto_start [altera_avalon_pio 17.1]
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| 6 |
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Progress: Parameterizing module auto_start
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| 7 |
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Progress: Adding clk_0 [clock_source 17.1]
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| 8 |
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Progress: Parameterizing module clk_0
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| 9 |
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Progress: Adding clock_sel [altera_avalon_pio 17.1]
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| 10 |
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Progress: Parameterizing module clock_sel
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| 11 |
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Progress: Adding counter_rx_fifo [altera_avalon_pio 17.1]
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| 12 |
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Progress: Parameterizing module counter_rx_fifo
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| 13 |
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Progress: Adding counter_tx_fifo [altera_avalon_pio 17.1]
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| 14 |
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Progress: Parameterizing module counter_tx_fifo
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| 15 |
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Progress: Adding data_flag_rx [altera_avalon_pio 17.1]
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| 16 |
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Progress: Parameterizing module data_flag_rx
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| 17 |
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Progress: Adding data_info [altera_avalon_pio 17.1]
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| 18 |
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Progress: Parameterizing module data_info
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| 19 |
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Progress: Adding data_read_en_rx [altera_avalon_pio 17.1]
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| 20 |
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Progress: Parameterizing module data_read_en_rx
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| 21 |
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Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.1]
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| 22 |
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Progress: Parameterizing module fifo_empty_rx_status
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| 23 |
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Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.1]
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| 24 |
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Progress: Parameterizing module fifo_empty_tx_status
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| 25 |
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Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.1]
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| 26 |
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Progress: Parameterizing module fifo_full_rx_status
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| 27 |
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Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.1]
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| 28 |
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Progress: Parameterizing module fifo_full_tx_status
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| 29 |
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Progress: Adding fsm_info [altera_avalon_pio 17.1]
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| 30 |
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Progress: Parameterizing module fsm_info
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| 31 |
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Progress: Adding hps_0 [altera_hps 17.1]
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| 32 |
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Progress: Parameterizing module hps_0
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| 33 |
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Progress: Adding led_pio_test [altera_avalon_pio 17.1]
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| 34 |
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Progress: Parameterizing module led_pio_test
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| 35 |
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Progress: Adding link_disable [altera_avalon_pio 17.1]
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| 36 |
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Progress: Parameterizing module link_disable
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| 37 |
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Progress: Adding link_start [altera_avalon_pio 17.1]
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| 38 |
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Progress: Parameterizing module link_start
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| 39 |
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Progress: Adding pll_0 [altera_pll 17.1]
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| 40 |
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Progress: Parameterizing module pll_0
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| 41 |
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Progress: Adding timecode_ready_rx [altera_avalon_pio 17.1]
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| 42 |
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Progress: Parameterizing module timecode_ready_rx
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| 43 |
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Progress: Adding timecode_rx [altera_avalon_pio 17.1]
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| 44 |
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Progress: Parameterizing module timecode_rx
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| 45 |
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Progress: Adding timecode_tx_data [altera_avalon_pio 17.1]
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| 46 |
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Progress: Parameterizing module timecode_tx_data
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| 47 |
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Progress: Adding timecode_tx_enable [altera_avalon_pio 17.1]
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| 48 |
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Progress: Parameterizing module timecode_tx_enable
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| 49 |
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Progress: Adding timecode_tx_ready [altera_avalon_pio 17.1]
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| 50 |
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Progress: Parameterizing module timecode_tx_ready
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| 51 |
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Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.1]
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| 52 |
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Progress: Parameterizing module write_data_fifo_tx
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| 53 |
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Progress: Adding write_en_tx [altera_avalon_pio 17.1]
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| 54 |
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Progress: Parameterizing module write_en_tx
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| 55 |
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Progress: Building connections
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| 56 |
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Progress: Parameterizing connections
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| 57 |
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Progress: Validating
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| 58 |
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Progress: Done reading input file
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| 59 |
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Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 60 |
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Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 61 |
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Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 62 |
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Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 63 |
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Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 64 |
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Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 65 |
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Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 66 |
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Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 67 |
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Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 68 |
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Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36
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| 69 |
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Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
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| 70 |
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Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
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| 71 |
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Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
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| 72 |
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Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
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| 73 |
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Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
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| 74 |
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Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
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| 75 |
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Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
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| 76 |
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Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
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| 77 |
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Info: ulight_fifo.pll_0: Able to implement PLL with user settings
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| 78 |
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Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
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| 79 |
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Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 80 |
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Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 81 |
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Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| 82 |
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Info: ulight_fifo: Generating ulight_fifo "ulight_fifo" for SIM_VERILOG
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| 83 |
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Warning: ulight_fifo: "No matching role found for clk_0:clk:clk_out (clk)"
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| 84 |
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Warning: ulight_fifo: "No matching role found for pll_0:refclk1:refclk1 (refclk1)"
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| 85 |
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Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'
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| 86 |
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Info: auto_start: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ ]
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| 87 |
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Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'
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| 88 |
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Info: auto_start: "ulight_fifo" instantiated altera_avalon_pio "auto_start"
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| 89 |
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Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'
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| 90 |
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Info: clock_sel: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ ]
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| 91 |
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Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'
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| 92 |
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Info: clock_sel: "ulight_fifo" instantiated altera_avalon_pio "clock_sel"
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| 93 |
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Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'
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| 94 |
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Info: counter_rx_fifo: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ ]
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| 95 |
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Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'
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| 96 |
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Info: counter_rx_fifo: "ulight_fifo" instantiated altera_avalon_pio "counter_rx_fifo"
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| 97 |
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Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'
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| 98 |
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Info: data_flag_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ ]
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| 99 |
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Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'
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| 100 |
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Info: data_flag_rx: "ulight_fifo" instantiated altera_avalon_pio "data_flag_rx"
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| 101 |
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Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'
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| 102 |
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Info: data_info: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ ]
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| 103 |
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Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'
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| 104 |
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Info: data_info: "ulight_fifo" instantiated altera_avalon_pio "data_info"
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| 105 |
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Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
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| 106 |
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Info: fifo_empty_rx_status: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ ]
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| 107 |
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Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
|
| 108 |
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Info: fifo_empty_rx_status: "ulight_fifo" instantiated altera_avalon_pio "fifo_empty_rx_status"
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| 109 |
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Info: hps_0: "Running for module: hps_0"
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| 110 |
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Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36
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| 111 |
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Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
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| 112 |
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Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
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| 113 |
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Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
|
| 114 |
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Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
|
| 115 |
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Warning: hps_0: set_interface_assignment: Interface "hps_io" does not exist
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| 116 |
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Info: hps_0: "ulight_fifo" instantiated altera_hps "hps_0"
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| 117 |
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Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'
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| 118 |
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Info: led_pio_test: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ ]
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| 119 |
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Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'
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| 120 |
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Info: led_pio_test: "ulight_fifo" instantiated altera_avalon_pio "led_pio_test"
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| 121 |
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Info: pll_0: Generating simgen model
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| 122 |
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Info: pll_0: Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Jan 23 17:29:46 2018 Info: Command: quartus_sh -t run_simgen_cmd.tcl Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Jan 23 17:29:50 2018 Info: Command: quartus_map ulight_fifo_pll_0.qpf --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_parameter=CBX_HDL_LANGUAGE=VERILOG Info (20034): Auto device selection is not supported for Cyclone V device family. The default device, 5CGXFC7C7F23C8, is set. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo_pll_0.v Info (12023): Found entity 1: ulight_fifo_pll_0 File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 2 Info (12127): Elaborating entity "ulight_fifo_pll_0" for the top level hierarchy Info (12128): Elaborating entity "altera_pll" for hierarchy "altera_pll:altera_pll_i" File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 241 Warning (10034): Output port "lvds_clk" at altera_pll.v(319) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 319 Warning (10034): Output port "loaden" at altera_pll.v(320) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 320 Warning (10034): Output port "extclk_out" at altera_pll.v(321) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 321 Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus Info (12130): Elaborated megafunction instantiation "altera_pll:altera_pll_i" File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 241 Info (12133): Instantiated megafunction "altera_pll:altera_pll_i" with the following parameter: File: /tmp/alt7554_7831099621877055177.dir/0009_pll_0_gen/ulight_fifo_pll_0.v Line: 241 Info (12134): Parameter "fractional_vco_multiplier" = "false" Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" Info (12134): Parameter "pll_fractional_cout" = "32" Info (12134): Parameter "pll_dsm_out_sel" = "1st_order" Info (12134): Parameter "operation_mode" = "normal" Info (12134): Parameter "number_of_clocks" = "1" Info (12134): Parameter "output_clock_frequency0" = "400.000000 MHz" Info (12134): Parameter "phase_shift0" = "0 ps" Info (12134): Parameter "duty_cycle0" = "50" Info (12134): Parameter "output_clock_frequency1" = "0 MHz" Info (12134): Parameter "phase_shift1" = "0 ps" Info (12134): Parameter "duty_cycle1" = "50" Info (12134): Parameter "output_clock_frequency2" = "0 MHz" Info (12134): Parameter "phase_shift2" = "0 ps" Info (12134): Parameter "duty_cycle2" = "50" Info (12134): Parameter "output_clock_frequency3" = "0 MHz" Info (12134): Parameter "phase_shift3" = "0 ps" Info (12134): Parameter "duty_cycle3" = "50" Info (12134): Parameter "output_clock_frequency4" = "0 MHz" Info (12134): Parameter "phase_shift4" = "0 ps" Info (12134): Parameter "duty_cycle4" = "50" Info (12134): Parameter "output_clock_frequency5" = "0 MHz" Info (12134): Parameter "phase_shift5" = "0 ps" Info (12134): Parameter "duty_cycle5" = "50" Info (12134): Parameter "output_clock_frequency6" = "0 MHz" Info (12134): Parameter "phase_shift6" = "0 ps" Info (12134): Parameter "duty_cycle6" = "50" Info (12134): Parameter "output_clock_frequency7" = "0 MHz" Info (12134): Parameter "phase_shift7" = "0 ps" Info (12134): Parameter "duty_cycle7" = "50" Info (12134): Parameter "output_clock_frequency8" = "0 MHz" Info (12134): Parameter "phase_shift8" = "0 ps" Info (12134): Parameter "duty_cycle8" = "50" Info (12134): Parameter "output_clock_frequency9" = "0 MHz" Info (12134): Parameter "phase_shift9" = "0 ps" Info (12134): Parameter "duty_cycle9" = "50" Info (12134): Parameter "output_clock_frequency10" = "0 MHz" Info (12134): Parameter "phase_shift10" = "0 ps" Info (12134): Parameter "duty_cycle10" = "50" Info (12134): Parameter "output_clock_frequency11" = "0 MHz" Info (12134): Parameter "phase_shift11" = "0 ps" Info (12134): Parameter "duty_cycle11" = "50" Info (12134): Parameter "output_clock_frequency12" = "0 MHz" Info (12134): Parameter "phase_shift12" = "0 ps" Info (12134): Parameter "duty_cycle12" = "50" Info (12134): Parameter "output_clock_frequency13" = "0 MHz" Info (12134): Parameter "phase_shift13" = "0 ps" Info (12134): Parameter "duty_cycle13" = "50" Info (12134): Parameter "output_clock_frequency14" = "0 MHz" Info (12134): Parameter "phase_shift14" = "0 ps" Info (12134): Parameter "duty_cycle14" = "50" Info (12134): Parameter "output_clock_frequency15" = "0 MHz" Info (12134): Parameter "phase_shift15" = "0 ps" Info (12134): Parameter "duty_cycle15" = "50" Info (12134): Parameter "output_clock_frequency16" = "0 MHz" Info (12134): Parameter "phase_shift16" = "0 ps" Info (12134): Parameter "duty_cycle16" = "50" Info (12134): Parameter "output_clock_frequency17" = "0 MHz" Info (12134): Parameter "phase_shift17" = "0 ps" Info (12134): Parameter "duty_cycle17" = "50" Info (12134): Parameter "pll_type" = "Cyclone V" Info (12134): Parameter "pll_subtype" = "General" Info (12134): Parameter "m_cnt_hi_div" = "4" Info (12134): Parameter "m_cnt_lo_div" = "4" Info (12134): Parameter "n_cnt_hi_div" = "256" Info (12134): Parameter "n_cnt_lo_div" = "256" Info (12134): Parameter "m_cnt_bypass_en" = "false" Info (12134): Parameter "n_cnt_bypass_en" = "true" Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false" Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false" Info (12134): Parameter "c_cnt_hi_div0" = "256" Info (12134): Parameter "c_cnt_lo_div0" = "256" Info (12134): Parameter "c_cnt_prst0" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0" Info (12134): Parameter "c_cnt_in_src0" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en0" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false" Info (12134): Parameter "c_cnt_hi_div1" = "1" Info (12134): Parameter "c_cnt_lo_div1" = "1" Info (12134): Parameter "c_cnt_prst1" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0" Info (12134): Parameter "c_cnt_in_src1" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en1" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false" Info (12134): Parameter "c_cnt_hi_div2" = "1" Info (12134): Parameter "c_cnt_lo_div2" = "1" Info (12134): Parameter "c_cnt_prst2" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0" Info (12134): Parameter "c_cnt_in_src2" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en2" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false" Info (12134): Parameter "c_cnt_hi_div3" = "1" Info (12134): Parameter "c_cnt_lo_div3" = "1" Info (12134): Parameter "c_cnt_prst3" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0" Info (12134): Parameter "c_cnt_in_src3" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en3" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false" Info (12134): Parameter "c_cnt_hi_div4" = "1" Info (12134): Parameter "c_cnt_lo_div4" = "1" Info (12134): Parameter "c_cnt_prst4" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0" Info (12134): Parameter "c_cnt_in_src4" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en4" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false" Info (12134): Parameter "c_cnt_hi_div5" = "1" Info (12134): Parameter "c_cnt_lo_div5" = "1" Info (12134): Parameter "c_cnt_prst5" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0" Info (12134): Parameter "c_cnt_in_src5" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en5" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false" Info (12134): Parameter "c_cnt_hi_div6" = "1" Info (12134): Parameter "c_cnt_lo_div6" = "1" Info (12134): Parameter "c_cnt_prst6" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0" Info (12134): Parameter "c_cnt_in_src6" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en6" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false" Info (12134): Parameter "c_cnt_hi_div7" = "1" Info (12134): Parameter "c_cnt_lo_div7" = "1" Info (12134): Parameter "c_cnt_prst7" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0" Info (12134): Parameter "c_cnt_in_src7" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en7" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false" Info (12134): Parameter "c_cnt_hi_div8" = "1" Info (12134): Parameter "c_cnt_lo_div8" = "1" Info (12134): Parameter "c_cnt_prst8" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0" Info (12134): Parameter "c_cnt_in_src8" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en8" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false" Info (12134): Parameter "c_cnt_hi_div9" = "1" Info (12134): Parameter "c_cnt_lo_div9" = "1" Info (12134): Parameter "c_cnt_prst9" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0" Info (12134): Parameter "c_cnt_in_src9" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en9" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false" Info (12134): Parameter "c_cnt_hi_div10" = "1" Info (12134): Parameter "c_cnt_lo_div10" = "1" Info (12134): Parameter "c_cnt_prst10" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0" Info (12134): Parameter "c_cnt_in_src10" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en10" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false" Info (12134): Parameter "c_cnt_hi_div11" = "1" Info (12134): Parameter "c_cnt_lo_div11" = "1" Info (12134): Parameter "c_cnt_prst11" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0" Info (12134): Parameter "c_cnt_in_src11" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en11" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false" Info (12134): Parameter "c_cnt_hi_div12" = "1" Info (12134): Parameter "c_cnt_lo_div12" = "1" Info (12134): Parameter "c_cnt_prst12" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0" Info (12134): Parameter "c_cnt_in_src12" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en12" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false" Info (12134): Parameter "c_cnt_hi_div13" = "1" Info (12134): Parameter "c_cnt_lo_div13" = "1" Info (12134): Parameter "c_cnt_prst13" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0" Info (12134): Parameter "c_cnt_in_src13" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en13" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false" Info (12134): Parameter "c_cnt_hi_div14" = "1" Info (12134): Parameter "c_cnt_lo_div14" = "1" Info (12134): Parameter "c_cnt_prst14" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0" Info (12134): Parameter "c_cnt_in_src14" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en14" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false" Info (12134): Parameter "c_cnt_hi_div15" = "1" Info (12134): Parameter "c_cnt_lo_div15" = "1" Info (12134): Parameter "c_cnt_prst15" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0" Info (12134): Parameter "c_cnt_in_src15" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en15" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false" Info (12134): Parameter "c_cnt_hi_div16" = "1" Info (12134): Parameter "c_cnt_lo_div16" = "1" Info (12134): Parameter "c_cnt_prst16" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0" Info (12134): Parameter "c_cnt_in_src16" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en16" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false" Info (12134): Parameter "c_cnt_hi_div17" = "1" Info (12134): Parameter "c_cnt_lo_div17" = "1" Info (12134): Parameter "c_cnt_prst17" = "1" Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0" Info (12134): Parameter "c_cnt_in_src17" = "ph_mux_clk" Info (12134): Parameter "c_cnt_bypass_en17" = "true" Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false" Info (12134): Parameter "pll_vco_div" = "2" Info (12134): Parameter "pll_cp_current" = "20" Info (12134): Parameter "pll_bwctrl" = "4000" Info (12134): Parameter "pll_output_clk_frequency" = "400.0 MHz" Info (12134): Parameter "pll_fractional_division" = "1" Info (12134): Parameter "mimic_fbclk_type" = "gclk" Info (12134): Parameter "pll_fbclk_mux_1" = "glb" Info (12134): Parameter "pll_fbclk_mux_2" = "fb_1" Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk" Info (12134): Parameter "pll_slf_rst" = "false" Info (12134): Parameter "refclk1_frequency" = "100.0 MHz" Info (12134): Parameter "pll_clk_loss_sw_en" = "true" Info (12134): Parameter "pll_manu_clk_sw_en" = "false" Info (12134): Parameter "pll_auto_clk_sw_en" = "true" Info (12134): Parameter "pll_clkin_1_src" = "clk_1" Info (12134): Parameter "pll_clk_sw_dly" = "0" Info (281010): Generating sgate simulator netlist using Simgen SIMGEN_PROGRESS Start of Model generation -- 0% complete SIMGEN_PROGRESS Phase 1 : Internal Objects created -- 25% complete SIMGEN_PROGRESS Phase 2 : Connections between internal objects made -- 60% complete SIMGEN_PROGRESS Phase 3 : Netlist generated -- 100% complete Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings Info: Peak virtual memory: 941 megabytes Info: Processing ended: Tue Jan 23 17:30:09 2018 Info: Elapsed time: 00:00:19 Info: Total CPU time (on all processors): 00:00:40 Info (23030): Evaluation of Tcl script run_simgen_cmd.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 753 megabytes Info: Processing ended: Tue Jan 23 17:30:10 2018 Info: Elapsed time: 00:00:24 Info: Total CPU time (on all processors): 00:00:41
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Info: pll_0: Simgen was successful
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Info: pll_0: "ulight_fifo" instantiated altera_pll "pll_0"
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Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'
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Info: timecode_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ ]
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Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'
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Info: timecode_rx: "ulight_fifo" instantiated altera_avalon_pio "timecode_rx"
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Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'
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Info: timecode_tx_data: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ ]
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Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'
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Info: timecode_tx_data: "ulight_fifo" instantiated altera_avalon_pio "timecode_tx_data"
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Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'
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Info: write_data_fifo_tx: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ ]
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Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'
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Info: write_data_fifo_tx: "ulight_fifo" instantiated altera_avalon_pio "write_data_fifo_tx"
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
|
| 153 |
|
|
Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
|
| 154 |
|
|
Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
|
| 155 |
|
|
Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
|
| 156 |
|
|
Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
|
| 157 |
|
|
Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
|
| 158 |
|
|
Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
|
| 159 |
|
|
Info: mm_interconnect_0: "ulight_fifo" instantiated altera_mm_interconnect "mm_interconnect_0"
|
| 160 |
|
|
Info: rst_controller: "ulight_fifo" instantiated altera_reset_controller "rst_controller"
|
| 161 |
|
|
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
|
| 162 |
|
|
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
|
| 163 |
|
|
Info: led_pio_test_s1_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "led_pio_test_s1_translator"
|
| 164 |
|
|
Info: hps_0_h2f_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
|
| 165 |
|
|
Info: led_pio_test_s1_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "led_pio_test_s1_agent"
|
| 166 |
|
|
Info: led_pio_test_s1_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "led_pio_test_s1_agent_rsp_fifo"
|
| 167 |
|
|
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
|
| 168 |
|
|
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
|
| 169 |
|
|
Info: hps_0_h2f_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_0_h2f_axi_master_wr_limiter"
|
| 170 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_sc_fifo.v
|
| 171 |
|
|
Info: led_pio_test_s1_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "led_pio_test_s1_burst_adapter"
|
| 172 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_merlin_address_alignment.sv
|
| 173 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_st_pipeline_base.v
|
| 174 |
|
|
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
|
| 175 |
|
|
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
|
| 176 |
|
|
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
|
| 177 |
|
|
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
|
| 178 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_merlin_arbitrator.sv
|
| 179 |
|
|
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
|
| 180 |
|
|
Info: border: "hps_io" instantiated altera_interface_generator "border"
|
| 181 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/verbosity_pkg.sv
|
| 182 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/avalon_utilities_pkg.sv
|
| 183 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/avalon_mm_pkg.sv
|
| 184 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_mm_slave_bfm.sv
|
| 185 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_interrupt_sink.sv
|
| 186 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_clock_source.sv
|
| 187 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules/altera_avalon_reset_source.sv
|
| 188 |
|
|
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
|
| 189 |
|
|
Info: ulight_fifo: Done "ulight_fifo" with 32 modules, 58 files
|
| 190 |
|
|
Info: qsys-generate succeeded.
|
| 191 |
|
|
Info: Finished: Create simulation model
|
| 192 |
|
|
Info: Starting: Create Modelsim Project.
|
| 193 |
|
|
Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ --use-relative-paths=true
|
| 194 |
|
|
Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ --use-relative-paths=true
|
| 195 |
|
|
Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
|
| 196 |
|
|
Info: mentor/msim_setup.tcl
|
| 197 |
|
|
Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
|
| 198 |
|
|
Info: synopsys/vcs/vcs_setup.sh
|
| 199 |
|
|
Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
|
| 200 |
|
|
Info: synopsys/vcsmx/synopsys_sim.setup
|
| 201 |
|
|
Info: synopsys/vcsmx/vcsmx_setup.sh
|
| 202 |
|
|
Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
|
| 203 |
|
|
Info: cadence/cds.lib
|
| 204 |
|
|
Info: cadence/hdl.var
|
| 205 |
|
|
Info: cadence/ncsim_setup.sh
|
| 206 |
|
|
Info: 32 .cds.lib files in cadence/cds_libs/ directory
|
| 207 |
|
|
Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/ directory:
|
| 208 |
|
|
Info: aldec/rivierapro_setup.tcl
|
| 209 |
|
|
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/.
|
| 210 |
|
|
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
|
| 211 |
|
|
Info: Finished: Create Modelsim Project.
|
| 212 |
32 |
redbear |
Info: Starting: Create block symbol file (.bsf)
|
| 213 |
40 |
redbear |
Info: qsys-generate /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo.qsys --block-symbol-file --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo --family="Cyclone V" --part=5CSEMA4U23C6
|
| 214 |
32 |
redbear |
Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
|
| 215 |
|
|
Progress: Reading input file
|
| 216 |
40 |
redbear |
Progress: Adding auto_start [altera_avalon_pio 17.1]
|
| 217 |
32 |
redbear |
Progress: Parameterizing module auto_start
|
| 218 |
40 |
redbear |
Progress: Adding clk_0 [clock_source 17.1]
|
| 219 |
32 |
redbear |
Progress: Parameterizing module clk_0
|
| 220 |
40 |
redbear |
Progress: Adding clock_sel [altera_avalon_pio 17.1]
|
| 221 |
32 |
redbear |
Progress: Parameterizing module clock_sel
|
| 222 |
40 |
redbear |
Progress: Adding counter_rx_fifo [altera_avalon_pio 17.1]
|
| 223 |
32 |
redbear |
Progress: Parameterizing module counter_rx_fifo
|
| 224 |
40 |
redbear |
Progress: Adding counter_tx_fifo [altera_avalon_pio 17.1]
|
| 225 |
32 |
redbear |
Progress: Parameterizing module counter_tx_fifo
|
| 226 |
40 |
redbear |
Progress: Adding data_flag_rx [altera_avalon_pio 17.1]
|
| 227 |
32 |
redbear |
Progress: Parameterizing module data_flag_rx
|
| 228 |
40 |
redbear |
Progress: Adding data_info [altera_avalon_pio 17.1]
|
| 229 |
32 |
redbear |
Progress: Parameterizing module data_info
|
| 230 |
40 |
redbear |
Progress: Adding data_read_en_rx [altera_avalon_pio 17.1]
|
| 231 |
32 |
redbear |
Progress: Parameterizing module data_read_en_rx
|
| 232 |
40 |
redbear |
Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.1]
|
| 233 |
32 |
redbear |
Progress: Parameterizing module fifo_empty_rx_status
|
| 234 |
40 |
redbear |
Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.1]
|
| 235 |
32 |
redbear |
Progress: Parameterizing module fifo_empty_tx_status
|
| 236 |
40 |
redbear |
Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.1]
|
| 237 |
32 |
redbear |
Progress: Parameterizing module fifo_full_rx_status
|
| 238 |
40 |
redbear |
Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.1]
|
| 239 |
32 |
redbear |
Progress: Parameterizing module fifo_full_tx_status
|
| 240 |
40 |
redbear |
Progress: Adding fsm_info [altera_avalon_pio 17.1]
|
| 241 |
32 |
redbear |
Progress: Parameterizing module fsm_info
|
| 242 |
40 |
redbear |
Progress: Adding hps_0 [altera_hps 17.1]
|
| 243 |
32 |
redbear |
Progress: Parameterizing module hps_0
|
| 244 |
40 |
redbear |
Progress: Adding led_pio_test [altera_avalon_pio 17.1]
|
| 245 |
32 |
redbear |
Progress: Parameterizing module led_pio_test
|
| 246 |
40 |
redbear |
Progress: Adding link_disable [altera_avalon_pio 17.1]
|
| 247 |
32 |
redbear |
Progress: Parameterizing module link_disable
|
| 248 |
40 |
redbear |
Progress: Adding link_start [altera_avalon_pio 17.1]
|
| 249 |
32 |
redbear |
Progress: Parameterizing module link_start
|
| 250 |
40 |
redbear |
Progress: Adding pll_0 [altera_pll 17.1]
|
| 251 |
32 |
redbear |
Progress: Parameterizing module pll_0
|
| 252 |
40 |
redbear |
Progress: Adding timecode_ready_rx [altera_avalon_pio 17.1]
|
| 253 |
32 |
redbear |
Progress: Parameterizing module timecode_ready_rx
|
| 254 |
40 |
redbear |
Progress: Adding timecode_rx [altera_avalon_pio 17.1]
|
| 255 |
32 |
redbear |
Progress: Parameterizing module timecode_rx
|
| 256 |
40 |
redbear |
Progress: Adding timecode_tx_data [altera_avalon_pio 17.1]
|
| 257 |
32 |
redbear |
Progress: Parameterizing module timecode_tx_data
|
| 258 |
40 |
redbear |
Progress: Adding timecode_tx_enable [altera_avalon_pio 17.1]
|
| 259 |
32 |
redbear |
Progress: Parameterizing module timecode_tx_enable
|
| 260 |
40 |
redbear |
Progress: Adding timecode_tx_ready [altera_avalon_pio 17.1]
|
| 261 |
32 |
redbear |
Progress: Parameterizing module timecode_tx_ready
|
| 262 |
40 |
redbear |
Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.1]
|
| 263 |
32 |
redbear |
Progress: Parameterizing module write_data_fifo_tx
|
| 264 |
40 |
redbear |
Progress: Adding write_en_tx [altera_avalon_pio 17.1]
|
| 265 |
32 |
redbear |
Progress: Parameterizing module write_en_tx
|
| 266 |
|
|
Progress: Building connections
|
| 267 |
|
|
Progress: Parameterizing connections
|
| 268 |
|
|
Progress: Validating
|
| 269 |
|
|
Progress: Done reading input file
|
| 270 |
|
|
Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 271 |
|
|
Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 272 |
|
|
Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 273 |
|
|
Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 274 |
|
|
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 275 |
|
|
Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 276 |
|
|
Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 277 |
|
|
Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 278 |
|
|
Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 279 |
40 |
redbear |
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36
|
| 280 |
|
|
Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
|
| 281 |
32 |
redbear |
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
|
| 282 |
|
|
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
|
| 283 |
|
|
Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
|
| 284 |
|
|
Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
|
| 285 |
|
|
Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
|
| 286 |
40 |
redbear |
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
|
| 287 |
|
|
Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
|
| 288 |
32 |
redbear |
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
|
| 289 |
|
|
Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
|
| 290 |
|
|
Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 291 |
|
|
Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 292 |
|
|
Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 293 |
|
|
Info: qsys-generate succeeded.
|
| 294 |
|
|
Info: Finished: Create block symbol file (.bsf)
|
| 295 |
|
|
Info:
|
| 296 |
|
|
Info: Starting: Create HDL design files for synthesis
|
| 297 |
40 |
redbear |
Info: qsys-generate /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo.qsys --synthesis=VERILOG --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis --family="Cyclone V" --part=5CSEMA4U23C6
|
| 298 |
32 |
redbear |
Progress: Loading spw_fifo_ulight/ulight_fifo.qsys
|
| 299 |
|
|
Progress: Reading input file
|
| 300 |
40 |
redbear |
Progress: Adding auto_start [altera_avalon_pio 17.1]
|
| 301 |
32 |
redbear |
Progress: Parameterizing module auto_start
|
| 302 |
40 |
redbear |
Progress: Adding clk_0 [clock_source 17.1]
|
| 303 |
32 |
redbear |
Progress: Parameterizing module clk_0
|
| 304 |
40 |
redbear |
Progress: Adding clock_sel [altera_avalon_pio 17.1]
|
| 305 |
32 |
redbear |
Progress: Parameterizing module clock_sel
|
| 306 |
40 |
redbear |
Progress: Adding counter_rx_fifo [altera_avalon_pio 17.1]
|
| 307 |
32 |
redbear |
Progress: Parameterizing module counter_rx_fifo
|
| 308 |
40 |
redbear |
Progress: Adding counter_tx_fifo [altera_avalon_pio 17.1]
|
| 309 |
32 |
redbear |
Progress: Parameterizing module counter_tx_fifo
|
| 310 |
40 |
redbear |
Progress: Adding data_flag_rx [altera_avalon_pio 17.1]
|
| 311 |
32 |
redbear |
Progress: Parameterizing module data_flag_rx
|
| 312 |
40 |
redbear |
Progress: Adding data_info [altera_avalon_pio 17.1]
|
| 313 |
32 |
redbear |
Progress: Parameterizing module data_info
|
| 314 |
40 |
redbear |
Progress: Adding data_read_en_rx [altera_avalon_pio 17.1]
|
| 315 |
32 |
redbear |
Progress: Parameterizing module data_read_en_rx
|
| 316 |
40 |
redbear |
Progress: Adding fifo_empty_rx_status [altera_avalon_pio 17.1]
|
| 317 |
32 |
redbear |
Progress: Parameterizing module fifo_empty_rx_status
|
| 318 |
40 |
redbear |
Progress: Adding fifo_empty_tx_status [altera_avalon_pio 17.1]
|
| 319 |
32 |
redbear |
Progress: Parameterizing module fifo_empty_tx_status
|
| 320 |
40 |
redbear |
Progress: Adding fifo_full_rx_status [altera_avalon_pio 17.1]
|
| 321 |
32 |
redbear |
Progress: Parameterizing module fifo_full_rx_status
|
| 322 |
40 |
redbear |
Progress: Adding fifo_full_tx_status [altera_avalon_pio 17.1]
|
| 323 |
32 |
redbear |
Progress: Parameterizing module fifo_full_tx_status
|
| 324 |
40 |
redbear |
Progress: Adding fsm_info [altera_avalon_pio 17.1]
|
| 325 |
32 |
redbear |
Progress: Parameterizing module fsm_info
|
| 326 |
40 |
redbear |
Progress: Adding hps_0 [altera_hps 17.1]
|
| 327 |
32 |
redbear |
Progress: Parameterizing module hps_0
|
| 328 |
40 |
redbear |
Progress: Adding led_pio_test [altera_avalon_pio 17.1]
|
| 329 |
32 |
redbear |
Progress: Parameterizing module led_pio_test
|
| 330 |
40 |
redbear |
Progress: Adding link_disable [altera_avalon_pio 17.1]
|
| 331 |
32 |
redbear |
Progress: Parameterizing module link_disable
|
| 332 |
40 |
redbear |
Progress: Adding link_start [altera_avalon_pio 17.1]
|
| 333 |
32 |
redbear |
Progress: Parameterizing module link_start
|
| 334 |
40 |
redbear |
Progress: Adding pll_0 [altera_pll 17.1]
|
| 335 |
32 |
redbear |
Progress: Parameterizing module pll_0
|
| 336 |
40 |
redbear |
Progress: Adding timecode_ready_rx [altera_avalon_pio 17.1]
|
| 337 |
32 |
redbear |
Progress: Parameterizing module timecode_ready_rx
|
| 338 |
40 |
redbear |
Progress: Adding timecode_rx [altera_avalon_pio 17.1]
|
| 339 |
32 |
redbear |
Progress: Parameterizing module timecode_rx
|
| 340 |
40 |
redbear |
Progress: Adding timecode_tx_data [altera_avalon_pio 17.1]
|
| 341 |
32 |
redbear |
Progress: Parameterizing module timecode_tx_data
|
| 342 |
40 |
redbear |
Progress: Adding timecode_tx_enable [altera_avalon_pio 17.1]
|
| 343 |
32 |
redbear |
Progress: Parameterizing module timecode_tx_enable
|
| 344 |
40 |
redbear |
Progress: Adding timecode_tx_ready [altera_avalon_pio 17.1]
|
| 345 |
32 |
redbear |
Progress: Parameterizing module timecode_tx_ready
|
| 346 |
40 |
redbear |
Progress: Adding write_data_fifo_tx [altera_avalon_pio 17.1]
|
| 347 |
32 |
redbear |
Progress: Parameterizing module write_data_fifo_tx
|
| 348 |
40 |
redbear |
Progress: Adding write_en_tx [altera_avalon_pio 17.1]
|
| 349 |
32 |
redbear |
Progress: Parameterizing module write_en_tx
|
| 350 |
|
|
Progress: Building connections
|
| 351 |
|
|
Progress: Parameterizing connections
|
| 352 |
|
|
Progress: Validating
|
| 353 |
|
|
Progress: Done reading input file
|
| 354 |
|
|
Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 355 |
|
|
Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 356 |
|
|
Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 357 |
|
|
Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 358 |
|
|
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 359 |
|
|
Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 360 |
|
|
Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 361 |
|
|
Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 362 |
|
|
Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 363 |
40 |
redbear |
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36
|
| 364 |
|
|
Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
|
| 365 |
32 |
redbear |
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
|
| 366 |
|
|
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
|
| 367 |
|
|
Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
|
| 368 |
|
|
Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
|
| 369 |
|
|
Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
|
| 370 |
40 |
redbear |
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
|
| 371 |
|
|
Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
|
| 372 |
32 |
redbear |
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
|
| 373 |
|
|
Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
|
| 374 |
|
|
Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 375 |
|
|
Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 376 |
|
|
Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
| 377 |
|
|
Info: ulight_fifo: Generating ulight_fifo "ulight_fifo" for QUARTUS_SYNTH
|
| 378 |
|
|
Warning: ulight_fifo: "No matching role found for clk_0:clk:clk_out (clk)"
|
| 379 |
|
|
Warning: ulight_fifo: "No matching role found for pll_0:refclk1:refclk1 (refclk1)"
|
| 380 |
|
|
Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'
|
| 381 |
40 |
redbear |
Info: auto_start: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=0 ]
|
| 382 |
32 |
redbear |
Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'
|
| 383 |
|
|
Info: auto_start: "ulight_fifo" instantiated altera_avalon_pio "auto_start"
|
| 384 |
|
|
Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'
|
| 385 |
40 |
redbear |
Info: clock_sel: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=0 ]
|
| 386 |
32 |
redbear |
Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'
|
| 387 |
|
|
Info: clock_sel: "ulight_fifo" instantiated altera_avalon_pio "clock_sel"
|
| 388 |
|
|
Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'
|
| 389 |
40 |
redbear |
Info: counter_rx_fifo: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=0 ]
|
| 390 |
32 |
redbear |
Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'
|
| 391 |
|
|
Info: counter_rx_fifo: "ulight_fifo" instantiated altera_avalon_pio "counter_rx_fifo"
|
| 392 |
|
|
Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'
|
| 393 |
40 |
redbear |
Info: data_flag_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=0 ]
|
| 394 |
32 |
redbear |
Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'
|
| 395 |
|
|
Info: data_flag_rx: "ulight_fifo" instantiated altera_avalon_pio "data_flag_rx"
|
| 396 |
|
|
Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'
|
| 397 |
40 |
redbear |
Info: data_info: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=0 ]
|
| 398 |
32 |
redbear |
Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'
|
| 399 |
|
|
Info: data_info: "ulight_fifo" instantiated altera_avalon_pio "data_info"
|
| 400 |
|
|
Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
|
| 401 |
40 |
redbear |
Info: fifo_empty_rx_status: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=0 ]
|
| 402 |
32 |
redbear |
Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
|
| 403 |
|
|
Info: fifo_empty_rx_status: "ulight_fifo" instantiated altera_avalon_pio "fifo_empty_rx_status"
|
| 404 |
|
|
Info: hps_0: "Running for module: hps_0"
|
| 405 |
40 |
redbear |
Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36
|
| 406 |
|
|
Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
|
| 407 |
32 |
redbear |
Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
|
| 408 |
|
|
Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
|
| 409 |
|
|
Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
|
| 410 |
|
|
Warning: hps_0: set_interface_assignment: Interface "hps_io" does not exist
|
| 411 |
|
|
Info: hps_0: "ulight_fifo" instantiated altera_hps "hps_0"
|
| 412 |
|
|
Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'
|
| 413 |
40 |
redbear |
Info: led_pio_test: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=0 ]
|
| 414 |
32 |
redbear |
Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'
|
| 415 |
|
|
Info: led_pio_test: "ulight_fifo" instantiated altera_avalon_pio "led_pio_test"
|
| 416 |
|
|
Info: pll_0: "ulight_fifo" instantiated altera_pll "pll_0"
|
| 417 |
|
|
Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'
|
| 418 |
40 |
redbear |
Info: timecode_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=0 ]
|
| 419 |
32 |
redbear |
Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'
|
| 420 |
|
|
Info: timecode_rx: "ulight_fifo" instantiated altera_avalon_pio "timecode_rx"
|
| 421 |
|
|
Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'
|
| 422 |
40 |
redbear |
Info: timecode_tx_data: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=0 ]
|
| 423 |
32 |
redbear |
Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'
|
| 424 |
|
|
Info: timecode_tx_data: "ulight_fifo" instantiated altera_avalon_pio "timecode_tx_data"
|
| 425 |
|
|
Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'
|
| 426 |
40 |
redbear |
Info: write_data_fifo_tx: Generation command is [exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=0 ]
|
| 427 |
32 |
redbear |
Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'
|
| 428 |
|
|
Info: write_data_fifo_tx: "ulight_fifo" instantiated altera_avalon_pio "write_data_fifo_tx"
|
| 429 |
|
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
|
| 430 |
|
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Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
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| 431 |
|
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Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
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| 432 |
|
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Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
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| 433 |
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Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
|
| 434 |
|
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Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
|
| 435 |
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Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
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| 436 |
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Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
|
| 437 |
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Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
|
| 438 |
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Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
|
| 439 |
|
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Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
|
| 440 |
|
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Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
|
| 441 |
|
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Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
|
| 442 |
|
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Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
|
| 443 |
|
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Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
|
| 444 |
|
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Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0
|
| 445 |
|
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Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0
|
| 446 |
|
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Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0
|
| 447 |
|
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Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0
|
| 448 |
|
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Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0
|
| 449 |
|
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Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0
|
| 450 |
|
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Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0
|
| 451 |
|
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Info: mm_interconnect_0: "ulight_fifo" instantiated altera_mm_interconnect "mm_interconnect_0"
|
| 452 |
|
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Info: rst_controller: "ulight_fifo" instantiated altera_reset_controller "rst_controller"
|
| 453 |
|
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Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
|
| 454 |
|
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Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
|
| 455 |
|
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Info: led_pio_test_s1_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "led_pio_test_s1_translator"
|
| 456 |
|
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Info: hps_0_h2f_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
|
| 457 |
|
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Info: led_pio_test_s1_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "led_pio_test_s1_agent"
|
| 458 |
|
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Info: led_pio_test_s1_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "led_pio_test_s1_agent_rsp_fifo"
|
| 459 |
|
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Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
|
| 460 |
|
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Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
|
| 461 |
|
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Info: hps_0_h2f_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_0_h2f_axi_master_wr_limiter"
|
| 462 |
40 |
redbear |
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v
|
| 463 |
32 |
redbear |
Info: led_pio_test_s1_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "led_pio_test_s1_burst_adapter"
|
| 464 |
40 |
redbear |
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv
|
| 465 |
|
|
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v
|
| 466 |
32 |
redbear |
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
|
| 467 |
|
|
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
|
| 468 |
|
|
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
|
| 469 |
|
|
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
|
| 470 |
40 |
redbear |
Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv
|
| 471 |
32 |
redbear |
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
|
| 472 |
|
|
Info: border: "hps_io" instantiated altera_interface_generator "border"
|
| 473 |
|
|
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
|
| 474 |
|
|
Info: ulight_fifo: Done "ulight_fifo" with 32 modules, 89 files
|
| 475 |
|
|
Info: qsys-generate succeeded.
|
| 476 |
|
|
Info: Finished: Create HDL design files for synthesis
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