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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [clock_reduce.v] - Blame information for rev 40

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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
module clock_reduce(
                        input clk,
                        input reset_n,
                        input [2:0] clock_sel,
 
                        output  clk_reduced,
                        output  clk_100_reduced
 
                   );
 
 
reg [10:0] counter;
reg [10:0] counter_100;
 
assign clk_reduced     = clk_reduced_p | clk_reduced_n;
assign clk_100_reduced = clk_100_reduced_p | clk_100_reduced_n;
 
 
reg clk_reduced_i;
reg clk_100_reduced_i;
 
 
reg clk_reduced_p;
reg clk_100_reduced_p;
 
reg clk_reduced_n;
reg clk_100_reduced_n;
 
always@(*)
begin
 
        clk_reduced_p = 1'b0;
 
        if(clk_reduced_i)
        begin
                clk_reduced_p = 1'b1;
        end
 
end
 
 
always@(*)
begin
 
        clk_reduced_n = 1'b1;
 
        if(!clk_reduced_i)
        begin
                clk_reduced_n = 1'b0;
        end
 
end
 
always@(*)
begin
 
        clk_100_reduced_p = 1'b0;
 
        if(clk_100_reduced_i)
        begin
                clk_100_reduced_p = 1'b1;
        end
 
end
 
 
always@(*)
begin
 
        clk_100_reduced_n = 1'b1;
 
        if(!clk_100_reduced_i)
        begin
                clk_100_reduced_n = 1'b0;
        end
 
end
 
always@(posedge clk)
begin
 
        if(!reset_n)
        begin
 
                counter <= 11'd0;
                counter_100 <= 11'd0;
                clk_reduced_i <= 1'b0;
                clk_100_reduced_i <= 1'b0;
        end
        else
        begin
 
 
                case(clock_sel)
                3'd0://2mhz - 500 ns
                begin
                        if(counter >=11'd0 && counter <=11'd99 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter >=11'd100 && counter <=11'd199 )
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                3'd1://5mhz
                begin
 
                        if(counter >=11'd0 && counter <=11'd39 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter >=11'd40 && counter <=11'd79 )
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                3'd2://10mhz
                begin
                        if(counter >=11'd0 && counter <=11'd19 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter >=11'd20 && counter <=11'd39 )
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                3'd3://50mhz
                begin
                        if(counter >=11'd0 && counter <=11'd3 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter >=11'd4 && counter <=11'd7)
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                3'd4://100mhz
                begin
                        if(counter >=11'd0 && counter <=11'd1 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter >=11'd2 && counter <=11'd4)
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                3'd5://150mhz
                begin
                        if(counter >=11'd0 && counter <=11'd1 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter >=11'd2 && counter <=11'd3)
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                3'd6://200mhz
                begin
                        if(counter >=11'd0 && counter <=11'd1 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter == 11'd2)
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                3'd7://300mhz
                begin
                        if(counter ==11'd0 )
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= counter + 11'd1;
                        end
                        else if(counter ==11'd1)
                        begin
                                clk_reduced_i <= 1'b0;
                                counter <= counter + 11'd1;
                        end
                        else
                        begin
                                clk_reduced_i <= 1'b1;
                                counter <= 11'd0;
                        end
                end
                endcase
 
                if(counter_100 >=11'd0 && counter_100 <=11'd1 )
                begin
                        clk_100_reduced_i <= 1'b1;
                        counter_100 <= counter_100 + 11'd1;
                end
                else if(counter_100 >=11'd2 && counter_100 <=11'd4)
                begin
                        clk_100_reduced_i <= 1'b0;
                        counter_100 <= counter_100 + 11'd1;
                end
                else
                begin
                        clk_100_reduced_i <= 1'b1;
                        counter_100 <= 11'd0;
                end
 
        end
 
end
 
endmodule

Line No.	Rev	Author	Line
1	23	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`module clock_reduce(`
35			`input clk,`
36			`input reset_n,`
37	40	redbear	`input [2:0] clock_sel,`
38	23	redbear
39	40	redbear	`output clk_reduced,`
40			`output clk_100_reduced`
41
42	23	redbear	`);`
43
44
45			`reg [10:0] counter;`
46	40	redbear	`reg [10:0] counter_100;`
47	23	redbear
48	40	redbear	`assign clk_reduced = clk_reduced_p \| clk_reduced_n;`
49			`assign clk_100_reduced = clk_100_reduced_p \| clk_100_reduced_n;`
50
51
52			`reg clk_reduced_i;`
53			`reg clk_100_reduced_i;`
54
55
56			`reg clk_reduced_p;`
57			`reg clk_100_reduced_p;`
58
59			`reg clk_reduced_n;`
60			`reg clk_100_reduced_n;`
61
62			`always@(*)`
63			`begin`
64
65			`clk_reduced_p = 1'b0;`
66
67			`if(clk_reduced_i)`
68			`begin`
69			`clk_reduced_p = 1'b1;`
70			`end`
71
72			`end`
73
74
75			`always@(*)`
76			`begin`
77
78			`clk_reduced_n = 1'b1;`
79
80			`if(!clk_reduced_i)`
81			`begin`
82			`clk_reduced_n = 1'b0;`
83			`end`
84
85			`end`
86
87			`always@(*)`
88			`begin`
89
90			`clk_100_reduced_p = 1'b0;`
91
92			`if(clk_100_reduced_i)`
93			`begin`
94			`clk_100_reduced_p = 1'b1;`
95			`end`
96
97			`end`
98
99
100			`always@(*)`
101			`begin`
102
103			`clk_100_reduced_n = 1'b1;`
104
105			`if(!clk_100_reduced_i)`
106			`begin`
107			`clk_100_reduced_n = 1'b0;`
108			`end`
109
110			`end`
111
112	23	redbear	`always@(posedge clk)`
113			`begin`
114
115			`if(!reset_n)`
116			`begin`
117	40	redbear
118	23	redbear	`counter <= 11'd0;`
119	40	redbear	`counter_100 <= 11'd0;`
120			`clk_reduced_i <= 1'b0;`
121			`clk_100_reduced_i <= 1'b0;`
122	23	redbear	`end`
123			`else`
124			`begin`
125	40	redbear
126
127			`case(clock_sel)`
128			`3'd0://2mhz - 500 ns`
129	23	redbear	`begin`
130	40	redbear	`if(counter >=11'd0 && counter <=11'd99 )`
131			`begin`
132			`clk_reduced_i <= 1'b1;`
133			`counter <= counter + 11'd1;`
134			`end`
135			`else if(counter >=11'd100 && counter <=11'd199 )`
136			`begin`
137			`clk_reduced_i <= 1'b0;`
138			`counter <= counter + 11'd1;`
139			`end`
140			`else`
141			`begin`
142			`clk_reduced_i <= 1'b1;`
143			`counter <= 11'd0;`
144			`end`
145	23	redbear	`end`
146	40	redbear	`3'd1://5mhz`
147	23	redbear	`begin`
148	40	redbear
149			`if(counter >=11'd0 && counter <=11'd39 )`
150			`begin`
151			`clk_reduced_i <= 1'b1;`
152			`counter <= counter + 11'd1;`
153			`end`
154			`else if(counter >=11'd40 && counter <=11'd79 )`
155			`begin`
156			`clk_reduced_i <= 1'b0;`
157			`counter <= counter + 11'd1;`
158			`end`
159			`else`
160			`begin`
161			`clk_reduced_i <= 1'b1;`
162			`counter <= 11'd0;`
163			`end`
164	23	redbear	`end`
165	40	redbear	`3'd2://10mhz`
166			`begin`
167			`if(counter >=11'd0 && counter <=11'd19 )`
168			`begin`
169			`clk_reduced_i <= 1'b1;`
170			`counter <= counter + 11'd1;`
171			`end`
172			`else if(counter >=11'd20 && counter <=11'd39 )`
173			`begin`
174			`clk_reduced_i <= 1'b0;`
175			`counter <= counter + 11'd1;`
176			`end`
177			`else`
178			`begin`
179			`clk_reduced_i <= 1'b1;`
180			`counter <= 11'd0;`
181			`end`
182			`end`
183			`3'd3://50mhz`
184			`begin`
185			`if(counter >=11'd0 && counter <=11'd3 )`
186			`begin`
187			`clk_reduced_i <= 1'b1;`
188			`counter <= counter + 11'd1;`
189			`end`
190			`else if(counter >=11'd4 && counter <=11'd7)`
191			`begin`
192			`clk_reduced_i <= 1'b0;`
193			`counter <= counter + 11'd1;`
194			`end`
195			`else`
196			`begin`
197			`clk_reduced_i <= 1'b1;`
198			`counter <= 11'd0;`
199			`end`
200			`end`
201			`3'd4://100mhz`
202			`begin`
203			`if(counter >=11'd0 && counter <=11'd1 )`
204			`begin`
205			`clk_reduced_i <= 1'b1;`
206			`counter <= counter + 11'd1;`
207			`end`
208			`else if(counter >=11'd2 && counter <=11'd4)`
209			`begin`
210			`clk_reduced_i <= 1'b0;`
211			`counter <= counter + 11'd1;`
212			`end`
213			`else`
214			`begin`
215			`clk_reduced_i <= 1'b1;`
216			`counter <= 11'd0;`
217			`end`
218			`end`
219			`3'd5://150mhz`
220			`begin`
221			`if(counter >=11'd0 && counter <=11'd1 )`
222			`begin`
223			`clk_reduced_i <= 1'b1;`
224			`counter <= counter + 11'd1;`
225			`end`
226			`else if(counter >=11'd2 && counter <=11'd3)`
227			`begin`
228			`clk_reduced_i <= 1'b0;`
229			`counter <= counter + 11'd1;`
230			`end`
231			`else`
232			`begin`
233			`clk_reduced_i <= 1'b1;`
234			`counter <= 11'd0;`
235			`end`
236			`end`
237			`3'd6://200mhz`
238			`begin`
239			`if(counter >=11'd0 && counter <=11'd1 )`
240			`begin`
241			`clk_reduced_i <= 1'b1;`
242			`counter <= counter + 11'd1;`
243			`end`
244			`else if(counter == 11'd2)`
245			`begin`
246			`clk_reduced_i <= 1'b0;`
247			`counter <= counter + 11'd1;`
248			`end`
249			`else`
250			`begin`
251			`clk_reduced_i <= 1'b1;`
252			`counter <= 11'd0;`
253			`end`
254			`end`
255			`3'd7://300mhz`
256			`begin`
257			`if(counter ==11'd0 )`
258			`begin`
259			`clk_reduced_i <= 1'b1;`
260			`counter <= counter + 11'd1;`
261			`end`
262			`else if(counter ==11'd1)`
263			`begin`
264			`clk_reduced_i <= 1'b0;`
265			`counter <= counter + 11'd1;`
266			`end`
267			`else`
268			`begin`
269			`clk_reduced_i <= 1'b1;`
270			`counter <= 11'd0;`
271			`end`
272			`end`
273			`endcase`
274
275			`if(counter_100 >=11'd0 && counter_100 <=11'd1 )`
276			`begin`
277			`clk_100_reduced_i <= 1'b1;`
278			`counter_100 <= counter_100 + 11'd1;`
279			`end`
280			`else if(counter_100 >=11'd2 && counter_100 <=11'd4)`
281			`begin`
282			`clk_100_reduced_i <= 1'b0;`
283			`counter_100 <= counter_100 + 11'd1;`
284			`end`
285	23	redbear	`else`
286			`begin`
287	40	redbear	`clk_100_reduced_i <= 1'b1;`
288			`counter_100 <= 11'd0;`
289	23	redbear	`end`
290	40	redbear
291	23	redbear	`end`
292
293			`end`
294
295			`endmodule`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [clock_reduce.v] - Blame information for rev 40