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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [debounce.v] - Blame information for rev 40

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1 23 redbear 
//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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module debounce_db(
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                    input CLK,
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                    input PB,
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                    output reg PB_state,
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                    output reg PB_down
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                  );
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41 40 redbear 
                  reg aux_pb;
42 23 redbear 
                  reg [15:0] counter;
43 40 redbear 
                  //assign PB_state = (counter >= 400)?PB_state:1'b1;
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always@(*)
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begin
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        PB_state = 1'b1;
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        if(CLK)
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        begin
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                if(aux_pb)
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                        PB_state = 1'b0;
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        end
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        else if(!CLK)
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        begin
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                if(aux_pb)
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                        PB_state = 1'b0;
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        end
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end
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61 23 redbear 
always@(posedge CLK)
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begin
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        if(PB)
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        begin
66 40 redbear 
                aux_pb  <= 1'b0;
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                counter <= 16'd0;
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                PB_down <= 1'b0;
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        end
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        else
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        begin
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                if(counter >= 400)
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                begin
75 40 redbear 
                        aux_pb  <= 1'b1;
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                        PB_down <= 1'b1;
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                end
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                else
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                        counter <= counter + 16'd1;
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        end
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end
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endmodule

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