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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [detector_tokens.v] - Blame information for rev 40

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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
module detector_tokens(
                                                                input  rx_din,
                                                                input  rx_sin,
                                                                input  rx_resetn,
                                                                //input clock_sys,
                                                                //output reg rx_buffer_write,
                                                                output reg [13:0] info
                                                         );
 
        wire rx_error;
        reg rx_got_bit;
        reg rx_got_null;
        reg rx_got_nchar;
        reg rx_got_time_code;
        reg rx_got_fct;
 
        wire  [5:0] counter_neg;
 
        reg  [1:0] state_data_process;
        reg  [1:0] next_state_data_process;
        reg control_bit_found;
 
        wire posedge_clk;
        wire negedge_clk;
 
        wire bit_c_0;//N
        wire bit_c_1;//P
        wire bit_c_2;//N
        wire bit_c_3;//P
        wire bit_c_ex;//P
 
        wire bit_d_0;//N
        wire bit_d_1;//P
        wire bit_d_2;//N
        wire bit_d_3;//P
        wire bit_d_4;//N
        wire bit_d_5;//P
        wire bit_d_6;//N
        wire bit_d_7;//P
        wire bit_d_8;//N
        wire bit_d_9;//P
 
        wire is_control;
        reg is_data;
 
        reg last_is_control;
        reg last_is_data;
        //reg last_is_timec;
 
        reg last_was_control;
        reg last_was_data;
        reg last_was_timec;
 
        reg [3:0] control;
        reg [3:0] control_r;
        reg [3:0] control_p_r;
        reg [9:0] data;
        reg [9:0] timecode;
 
        reg [9:0] dta_timec;
        reg [9:0] dta_timec_p;
 
        reg [3:0] control_l_r;
        reg [9:0] data_l_r;
 
        reg parity_rec_c;
        reg parity_rec_d;
 
        reg rx_error_c;
        reg rx_error_d;
 
        reg ready_control;
        reg ready_data;
 
        reg parity_rec_c_gen;
        reg parity_rec_d_gen;
 
        reg ready_control_p;
        reg ready_data_p;
 
        reg ready_control_p_r;
        reg ready_data_p_r;
 
        wire posedge_p;
 
        reg f_time;
 
        //CLOCK RECOVERY
        assign posedge_clk      = posedge_p;
        assign negedge_clk      = (f_time)?!posedge_p:1'b0;
 
        assign rx_error         = rx_error_c | rx_error_d;
 
        buf (posedge_p,rx_din ^ rx_sin);
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                f_time          <= 1'b0;
        end
        else
        begin
                f_time          <= 1'b1;
        end
end
 
always@(*)
begin
 
        rx_got_bit = 1'b0;
 
        if(rx_din | rx_sin)
        begin
                rx_got_bit = 1'b1;
        end
end
 
always@(*)
begin
 
        ready_control = 1'b0;
        ready_data    = 1'b0;
 
        if(is_control && counter_neg[5:0] == 6'd4 && !posedge_p)
        begin
                ready_control = 1'b1;
                ready_data    = 1'b0;
        end
        else if(is_control && counter_neg[5:0] == 6'd32 && !posedge_p)
        begin
                ready_control = 1'b0;
                ready_data    = 1'b1;
        end
end
 
bit_capture_data capture_d(
                        .negedge_clk(negedge_clk),
                        .posedge_clk(posedge_clk),
                        .rx_resetn(rx_resetn),
 
                        .rx_din(rx_din),
 
                        .bit_d_0(bit_d_0),//N
                        .bit_d_1(bit_d_1),//P
                        .bit_d_2(bit_d_2),//N
                        .bit_d_3(bit_d_3),//P
                        .bit_d_4(bit_d_4),//N
                        .bit_d_5(bit_d_5),//P
                        .bit_d_6(bit_d_6),//N
                        .bit_d_7(bit_d_7),//P
                        .bit_d_8(bit_d_8),//N
                        .bit_d_9(bit_d_9)//P
                  );
 
bit_capture_control capture_c(
                        .negedge_clk(negedge_clk),
                        .posedge_clk(posedge_clk),
                        .rx_resetn(rx_resetn),
 
                        .rx_din(rx_din),
 
                        .bit_c_0(bit_c_0),
                        .bit_c_1(bit_c_1),
                        .bit_c_2(bit_c_2),
                        .bit_c_3(bit_c_3)
                  );
 
counter_neg cnt_neg(
                        .negedge_clk(negedge_clk),
                        .rx_resetn(rx_resetn),
                        .rx_din(rx_din),
                        .is_control(is_control),
                        .counter_neg(counter_neg)
                  );
 
always@(*)
begin
 
        next_state_data_process = state_data_process;
 
        case(state_data_process)
        2'd0:
        begin
                if(ready_control_p_r || ready_data_p_r)
                begin
                        next_state_data_process = 2'd1;
                end
                else
                begin
                        next_state_data_process = 2'd0;
                end
        end
        2'd1:
        begin
                next_state_data_process = 2'd0;
        end
        default:
        begin
                next_state_data_process = 2'd0;
        end
        endcase
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                rx_got_null       <= 1'b0;
                rx_got_nchar      <= 1'b0;
                rx_got_time_code  <= 1'b0;
                rx_got_fct        <= 1'b0;
        end
        else
        begin
                if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)
                begin
                        rx_got_fct        <= 1'b1;
                        rx_got_null       <= 1'b0;
                        rx_got_nchar      <= 1'b0;
                        rx_got_time_code  <= 1'b0;
                end
                else if(control[2:0] != 3'd7 && last_is_data)
                begin
                        rx_got_nchar      <= 1'b1;
                        rx_got_null       <= 1'b0;
                        rx_got_time_code  <= 1'b0;
                        rx_got_fct        <= 1'b0;
                end
                else if(control[2:0] == 3'd7 && last_is_data)
                begin
                        rx_got_time_code  <= 1'b1;
                        rx_got_null       <= 1'b0;
                        rx_got_nchar      <= 1'b0;
                        rx_got_fct        <= 1'b0;
                end
                else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)
                begin
                        rx_got_null       <= 1'b1;
                        rx_got_nchar      <= 1'b0;
                        rx_got_time_code  <= 1'b0;
                        rx_got_fct        <= 1'b0;
                end
                else
                begin
                        rx_got_null       <= rx_got_null;
                        rx_got_nchar      <= rx_got_nchar;
                        rx_got_time_code  <= rx_got_time_code;
                        rx_got_fct        <= rx_got_fct;
                end
        end
end
 
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
        if(!rx_resetn)
        begin
                ready_control_p_r <= 1'b0;
                ready_data_p_r  <=  1'b0;
        end
        else
        begin
 
                if(counter_neg[5:0] == 6'd4 && is_control)
                begin
                        ready_control_p_r <= 1'b1;
                end
                else if(counter_neg[5:0] == 6'd32)
                begin
                        ready_data_p_r <= 1'b1;
                end
                else
                begin
                        ready_control_p_r <= 1'b0;
                        ready_data_p_r <= 1'b0;
                end
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                control_r               <= 4'd0;
                parity_rec_c            <= 1'b0;
                parity_rec_c_gen        <= 1'b0;
        end
        else
        begin
                control_r         <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
                parity_rec_c      <= bit_c_3;
 
                if(last_is_control)
                begin
                        parity_rec_c_gen <= !(bit_c_2^control[0]^control[1]);
                end
                else if(last_is_data)
                begin
                        parity_rec_c_gen <= !(bit_c_2^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
                end
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn )
begin
        if(!rx_resetn)
        begin
                dta_timec               <= 10'd0;
                parity_rec_d            <= 1'b0;
                parity_rec_d_gen        <= 1'b0;
        end
        else
        begin
                dta_timec         <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
                parity_rec_d      <= bit_d_9;
 
                if(last_is_control)
                begin
                        parity_rec_d_gen <= !(bit_d_8^control[0]^control[1]);
                end
                else if(last_is_data)
                begin
                        parity_rec_d_gen <= !(bit_d_8^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
                end
        end
end
 
always@(posedge posedge_clk or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
                control_l_r      <= 4'd0;
                control          <= 4'd0;
                data             <=  10'd0;
 
                last_is_control  <=  1'b0;
                last_is_data     <=  1'b0;
                //last_is_timec          <=  1'b0;
 
                state_data_process <= 2'd0;
                info <= 14'd0;
 
                rx_error_c <= 1'b0;
                rx_error_d <= 1'b0;
        end
        else
        begin
 
                state_data_process <= next_state_data_process;
 
                case(state_data_process)
                2'd0:
                begin
 
                        if(ready_control_p_r)
                        begin
                                control          <= control_p_r;
                                control_l_r      <= control;
 
                                last_is_control          <= 1'b1;
                                last_is_data             <= 1'b0;
                                //last_is_timec          <= 1'b0;
 
                        end
                        else if(ready_data_p_r)
                        begin
                                if(control[2:0] != 3'd7)
                                begin
                                        data            <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
 
                                        last_is_control         <=1'b0;
                                        last_is_data            <=1'b1;
                                        //last_is_timec         <=1'b0;
                                end
                                else if(control[2:0] == 3'd7)
                                begin
 
                                        last_is_control         <= 1'b0;
                                        last_is_data            <= 1'b0;
                                        //last_is_timec         <= 1'b1;
                                end
                        end
                        else
                        begin
 
                        end
 
                end
                2'd1:
                begin
                                if(ready_control_p_r)
                                begin
 
                                        if(parity_rec_c_gen != parity_rec_c)
                                        begin
                                                rx_error_c <= 1'b1;
                                        end
                                        else
                                                rx_error_c <= rx_error_c;
 
                                end
                                else if(ready_data_p_r)
                                begin
 
                                        if(parity_rec_d_gen != parity_rec_d)
                                        begin
                                                rx_error_d <= 1'b1;
                                        end
                                        else
                                                rx_error_d <= rx_error_d;
 
 
                                end
                                info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
                end
                default:
                begin
 
                end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	23	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33			`module detector_tokens(`
34			`input rx_din,`
35			`input rx_sin,`
36			`input rx_resetn,`
37	26	redbear	`//input clock_sys,`
38	40	redbear	`//output reg rx_buffer_write,`
39	26	redbear	`output reg [13:0] info`
40	23	redbear	`);`
41
42	40	redbear	`wire rx_error;`
43			`reg rx_got_bit;`
44	26	redbear	`reg rx_got_null;`
45			`reg rx_got_nchar;`
46			`reg rx_got_time_code;`
47	23	redbear	`reg rx_got_fct;`
48
49	40	redbear	`wire [5:0] counter_neg;`
50
51			`reg [1:0] state_data_process;`
52			`reg [1:0] next_state_data_process;`
53	26	redbear	`reg control_bit_found;`
54	23	redbear
55			`wire posedge_clk;`
56			`wire negedge_clk;`
57
58	40	redbear	`wire bit_c_0;//N`
59			`wire bit_c_1;//P`
60			`wire bit_c_2;//N`
61			`wire bit_c_3;//P`
62			`wire bit_c_ex;//P`
63	23	redbear
64	40	redbear	`wire bit_d_0;//N`
65			`wire bit_d_1;//P`
66			`wire bit_d_2;//N`
67			`wire bit_d_3;//P`
68			`wire bit_d_4;//N`
69			`wire bit_d_5;//P`
70			`wire bit_d_6;//N`
71			`wire bit_d_7;//P`
72			`wire bit_d_8;//N`
73			`wire bit_d_9;//P`
74	23	redbear
75	40	redbear	`wire is_control;`
76	23	redbear	`reg is_data;`
77
78			`reg last_is_control;`
79			`reg last_is_data;`
80	40	redbear	`//reg last_is_timec;`
81	23	redbear
82			`reg last_was_control;`
83			`reg last_was_data;`
84			`reg last_was_timec;`
85
86			`reg [3:0] control;`
87			`reg [3:0] control_r;`
88	40	redbear	`reg [3:0] control_p_r;`
89	23	redbear	`reg [9:0] data;`
90			`reg [9:0] timecode;`
91
92			`reg [9:0] dta_timec;`
93	40	redbear	`reg [9:0] dta_timec_p;`
94	23	redbear
95			`reg [3:0] control_l_r;`
96			`reg [9:0] data_l_r;`
97
98	40	redbear	`reg parity_rec_c;`
99			`reg parity_rec_d;`
100	23	redbear
101	40	redbear	`reg rx_error_c;`
102			`reg rx_error_d;`
103	23	redbear
104	40	redbear	`reg ready_control;`
105			`reg ready_data;`
106	23	redbear
107	40	redbear	`reg parity_rec_c_gen;`
108			`reg parity_rec_d_gen;`
109	23	redbear
110	40	redbear	`reg ready_control_p;`
111			`reg ready_data_p;`
112	23	redbear
113	40	redbear	`reg ready_control_p_r;`
114			`reg ready_data_p_r;`
115	23	redbear
116	40	redbear	`wire posedge_p;`
117	23	redbear
118	40	redbear	`reg f_time;`
119
120			`//CLOCK RECOVERY`
121			`assign posedge_clk = posedge_p;`
122			`assign negedge_clk = (f_time)?!posedge_p:1'b0;`
123	23	redbear
124	40	redbear	`assign rx_error = rx_error_c \| rx_error_d;`
125	23	redbear
126	40	redbear	`buf (posedge_p,rx_din ^ rx_sin);`
127	23	redbear
128	26	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
129			`begin`
130
131			`if(!rx_resetn)`
132			`begin`
133	40	redbear	`f_time <= 1'b0;`
134	26	redbear	`end`
135			`else`
136			`begin`
137	40	redbear	`f_time <= 1'b1;`
138	26	redbear	`end`
139			`end`
140
141	40	redbear	`always@(*)`
142	23	redbear	`begin`
143
144	40	redbear	`rx_got_bit = 1'b0;`
145
146			`if(rx_din \| rx_sin)`
147	23	redbear	`begin`
148	40	redbear	`rx_got_bit = 1'b1;`
149	23	redbear	`end`
150			`end`
151
152	40	redbear	`always@(*)`
153	23	redbear	`begin`
154
155	40	redbear	`ready_control = 1'b0;`
156			`ready_data = 1'b0;`
157
158			`if(is_control && counter_neg[5:0] == 6'd4 && !posedge_p)`
159	23	redbear	`begin`
160	40	redbear	`ready_control = 1'b1;`
161			`ready_data = 1'b0;`
162	23	redbear	`end`
163	40	redbear	`else if(is_control && counter_neg[5:0] == 6'd32 && !posedge_p)`
164	23	redbear	`begin`
165	40	redbear	`ready_control = 1'b0;`
166			`ready_data = 1'b1;`
167	23	redbear	`end`
168			`end`
169
170	40	redbear	`bit_capture_data capture_d(`
171			`.negedge_clk(negedge_clk),`
172			`.posedge_clk(posedge_clk),`
173			`.rx_resetn(rx_resetn),`
174
175			`.rx_din(rx_din),`
176
177			`.bit_d_0(bit_d_0),//N`
178			`.bit_d_1(bit_d_1),//P`
179			`.bit_d_2(bit_d_2),//N`
180			`.bit_d_3(bit_d_3),//P`
181			`.bit_d_4(bit_d_4),//N`
182			`.bit_d_5(bit_d_5),//P`
183			`.bit_d_6(bit_d_6),//N`
184			`.bit_d_7(bit_d_7),//P`
185			`.bit_d_8(bit_d_8),//N`
186			`.bit_d_9(bit_d_9)//P`
187			`);`
188
189			`bit_capture_control capture_c(`
190			`.negedge_clk(negedge_clk),`
191			`.posedge_clk(posedge_clk),`
192			`.rx_resetn(rx_resetn),`
193
194			`.rx_din(rx_din),`
195
196			`.bit_c_0(bit_c_0),`
197			`.bit_c_1(bit_c_1),`
198			`.bit_c_2(bit_c_2),`
199			`.bit_c_3(bit_c_3)`
200			`);`
201
202			`counter_neg cnt_neg(`
203			`.negedge_clk(negedge_clk),`
204			`.rx_resetn(rx_resetn),`
205			`.rx_din(rx_din),`
206			`.is_control(is_control),`
207			`.counter_neg(counter_neg)`
208			`);`
209
210			`always@(*)`
211	23	redbear	`begin`
212
213	40	redbear	`next_state_data_process = state_data_process;`
214
215			`case(state_data_process)`
216			`2'd0:`
217	23	redbear	`begin`
218	40	redbear	`if(ready_control_p_r \|\| ready_data_p_r)`
219	23	redbear	`begin`
220	40	redbear	`next_state_data_process = 2'd1;`
221	23	redbear	`end`
222	40	redbear	`else`
223	26	redbear	`begin`
224	40	redbear	`next_state_data_process = 2'd0;`
225	26	redbear	`end`
226	23	redbear	`end`
227	40	redbear	`2'd1:`
228	23	redbear	`begin`
229	40	redbear	`next_state_data_process = 2'd0;`
230			`end`
231			`default:`
232	26	redbear	`begin`
233	40	redbear	`next_state_data_process = 2'd0;`
234			`end`
235			`endcase`
236	26	redbear	`end`
237
238			`always@(posedge negedge_clk or negedge rx_resetn)`
239			`begin`
240			`if(!rx_resetn)`
241			`begin`
242			`rx_got_null <= 1'b0;`
243			`rx_got_nchar <= 1'b0;`
244			`rx_got_time_code <= 1'b0;`
245			`rx_got_fct <= 1'b0;`
246	23	redbear	`end`
247	26	redbear	`else`
248	23	redbear	`begin`
249	26	redbear	`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)`
250	23	redbear	`begin`
251	26	redbear	`rx_got_fct <= 1'b1;`
252			`rx_got_null <= 1'b0;`
253			`rx_got_nchar <= 1'b0;`
254			`rx_got_time_code <= 1'b0;`
255	23	redbear	`end`
256	26	redbear	`else if(control[2:0] != 3'd7 && last_is_data)`
257	23	redbear	`begin`
258	26	redbear	`rx_got_nchar <= 1'b1;`
259			`rx_got_null <= 1'b0;`
260			`rx_got_time_code <= 1'b0;`
261			`rx_got_fct <= 1'b0;`
262	23	redbear	`end`
263	26	redbear	`else if(control[2:0] == 3'd7 && last_is_data)`
264	23	redbear	`begin`
265	26	redbear	`rx_got_time_code <= 1'b1;`
266			`rx_got_null <= 1'b0;`
267			`rx_got_nchar <= 1'b0;`
268			`rx_got_fct <= 1'b0;`
269	23	redbear	`end`
270	26	redbear	`else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)`
271			`begin`
272			`rx_got_null <= 1'b1;`
273			`rx_got_nchar <= 1'b0;`
274			`rx_got_time_code <= 1'b0;`
275			`rx_got_fct <= 1'b0;`
276			`end`
277			`else`
278			`begin`
279			`rx_got_null <= rx_got_null;`
280			`rx_got_nchar <= rx_got_nchar;`
281			`rx_got_time_code <= rx_got_time_code;`
282			`rx_got_fct <= rx_got_fct;`
283			`end`
284	23	redbear	`end`
285			`end`
286
287	26	redbear
288			`always@(posedge negedge_clk or negedge rx_resetn)`
289	23	redbear	`begin`
290	26	redbear	`if(!rx_resetn)`
291			`begin`
292	40	redbear	`ready_control_p_r <= 1'b0;`
293			`ready_data_p_r <= 1'b0;`
294	26	redbear	`end`
295			`else`
296			`begin`
297	40	redbear
298			`if(counter_neg[5:0] == 6'd4 && is_control)`
299			`begin`
300			`ready_control_p_r <= 1'b1;`
301			`end`
302			`else if(counter_neg[5:0] == 6'd32)`
303			`begin`
304			`ready_data_p_r <= 1'b1;`
305			`end`
306			`else`
307			`begin`
308			`ready_control_p_r <= 1'b0;`
309			`ready_data_p_r <= 1'b0;`
310			`end`
311	26	redbear	`end`
312			`end`
313	23	redbear
314	40	redbear	`always@(posedge posedge_clk or negedge rx_resetn )`
315	26	redbear	`begin`
316	23	redbear	`if(!rx_resetn)`
317			`begin`
318	26	redbear	`control_r <= 4'd0;`
319	40	redbear	`parity_rec_c <= 1'b0;`
320			`parity_rec_c_gen <= 1'b0;`
321	26	redbear	`end`
322			`else`
323			`begin`
324	40	redbear	`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
325			`parity_rec_c <= bit_c_3;`
326
327			`if(last_is_control)`
328			`begin`
329			`parity_rec_c_gen <= !(bit_c_2^control[0]^control[1]);`
330			`end`
331			`else if(last_is_data)`
332			`begin`
333			`parity_rec_c_gen <= !(bit_c_2^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);`
334			`end`
335	26	redbear	`end`
336			`end`
337
338	40	redbear	`always@(posedge posedge_clk or negedge rx_resetn )`
339	26	redbear	`begin`
340			`if(!rx_resetn)`
341			`begin`
342			`dta_timec <= 10'd0;`
343	40	redbear	`parity_rec_d <= 1'b0;`
344			`parity_rec_d_gen <= 1'b0;`
345	26	redbear	`end`
346			`else`
347			`begin`
348	40	redbear	`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
349			`parity_rec_d <= bit_d_9;`
350
351			`if(last_is_control)`
352			`begin`
353			`parity_rec_d_gen <= !(bit_d_8^control[0]^control[1]);`
354			`end`
355			`else if(last_is_data)`
356			`begin`
357			`parity_rec_d_gen <= !(bit_d_8^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);`
358			`end`
359	26	redbear	`end`
360			`end`
361
362			`always@(posedge posedge_clk or negedge rx_resetn )`
363			`begin`
364
365			`if(!rx_resetn)`
366			`begin`
367	40	redbear	`control_l_r <= 4'd0;`
368			`control <= 4'd0;`
369			`data <= 10'd0;`
370	23	redbear
371	40	redbear	`last_is_control <= 1'b0;`
372			`last_is_data <= 1'b0;`
373			`//last_is_timec <= 1'b0;`
374	23	redbear
375	40	redbear	`state_data_process <= 2'd0;`
376			`info <= 14'd0;`
377	23	redbear
378	40	redbear	`rx_error_c <= 1'b0;`
379			`rx_error_d <= 1'b0;`
380	23	redbear	`end`
381			`else`
382			`begin`
383
384	40	redbear	`state_data_process <= next_state_data_process;`
385	23	redbear
386	40	redbear	`case(state_data_process)`
387			`2'd0:`
388	23	redbear	`begin`
389
390	40	redbear	`if(ready_control_p_r)`
391			`begin`
392			`control <= control_p_r;`
393			`control_l_r <= control;`
394	26	redbear
395	40	redbear	`last_is_control <= 1'b1;`
396			`last_is_data <= 1'b0;`
397			`//last_is_timec <= 1'b0;`
398	26	redbear
399	40	redbear	`end`
400			`else if(ready_data_p_r)`
401	26	redbear	`begin`
402	40	redbear	`if(control[2:0] != 3'd7)`
403			`begin`
404			`data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};`
405
406			`last_is_control <=1'b0;`
407			`last_is_data <=1'b1;`
408			`//last_is_timec <=1'b0;`
409			`end`
410			`else if(control[2:0] == 3'd7)`
411			`begin`
412
413			`last_is_control <= 1'b0;`
414			`last_is_data <= 1'b0;`
415			`//last_is_timec <= 1'b1;`
416			`end`
417	26	redbear	`end`
418	40	redbear	`else`
419	26	redbear	`begin`
420	40	redbear
421	26	redbear	`end`
422	40	redbear
423	26	redbear	`end`
424	40	redbear	`2'd1:`
425	26	redbear	`begin`
426	40	redbear	`if(ready_control_p_r)`
427			`begin`
428	26	redbear
429	40	redbear	`if(parity_rec_c_gen != parity_rec_c)`
430			`begin`
431			`rx_error_c <= 1'b1;`
432			`end`
433			`else`
434			`rx_error_c <= rx_error_c;`
435	26	redbear
436	40	redbear	`end`
437			`else if(ready_data_p_r)`
438			`begin`
439	23	redbear
440	40	redbear	`if(parity_rec_d_gen != parity_rec_d)`
441			`begin`
442			`rx_error_d <= 1'b1;`
443			`end`
444			`else`
445			`rx_error_d <= rx_error_d;`
446	26	redbear
447	40	redbear
448			`end`
449			`info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};`
450	23	redbear	`end`
451	40	redbear	`default:`
452	23	redbear	`begin`
453	40	redbear
454	23	redbear	`end`
455	40	redbear	`endcase`
456	23	redbear	`end`
457	40	redbear	`end`
458	23	redbear
459			`endmodule`

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