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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [detector_tokens.v] - Blame information for rev 23

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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
module detector_tokens(
                                                                input  rx_din,
                                                                input  rx_sin,
                                                                input  rx_resetn,
                                                                output [13:0] info
                                                         );
 
        wire rx_error;
        wire rx_got_bit;
        wire rx_got_null;
        wire rx_got_nchar;
        wire rx_got_time_code;
        reg rx_got_fct;
 
        reg  [4:0] counter_neg;
 
        wire posedge_clk;
        wire negedge_clk;
 
        reg bit_c_0;//N
        reg bit_c_1;//P
        reg bit_c_2;//N
        reg bit_c_3;//P
 
        reg bit_d_0;//N
        reg bit_d_1;//P
        reg bit_d_2;//N
        reg bit_d_3;//P
        reg bit_d_4;//N
        reg bit_d_5;//P
        reg bit_d_6;//N
        reg bit_d_7;//P
        reg bit_d_8;//N
        reg bit_d_9;//P
 
        reg is_control;
        reg is_data;
 
        reg last_is_control;
        reg last_is_data;
        reg last_is_timec;
 
        reg last_was_control;
        reg last_was_data;
        reg last_was_timec;
 
        reg [3:0] control;
        reg [3:0] control_r;
        reg [9:0] data;
        reg [9:0] timecode;
 
        reg [9:0] dta_timec;
 
        reg [3:0] control_l_r;
        reg [9:0] data_l_r;
 
        reg parity_error;
        wire check_c_d;
 
        reg rx_data_take;
 
        reg first_time;
 
        //CLOCK RECOVERY
        assign posedge_clk      = (rx_din ^ rx_sin)?1'b1:1'b0;
        assign negedge_clk      = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
 
        assign check_c_d        = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
 
        assign rx_got_null      = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
        //assign rx_got_fct       = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
 
        assign rx_got_bit       = (posedge_clk)?1'b1:1'b0;
 
        assign rx_error         =  parity_error;
 
        assign rx_got_nchar     = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
        assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
 
        assign info = {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_1 <= 1'b0;
                bit_c_3 <= 1'b0;
 
                bit_d_1 <= 1'b0;
                bit_d_3 <= 1'b0;
                bit_d_5 <= 1'b0;
                bit_d_7 <= 1'b0;
                bit_d_9 <= 1'b0;
                first_time <= 1'b0;
        end
        else
        begin
                bit_c_1 <= rx_din;
                bit_c_3 <= bit_c_1;
 
                bit_d_1 <= rx_din;
                bit_d_3 <= bit_d_1;
                bit_d_5 <= bit_d_3;
                bit_d_7 <= bit_d_5;
                bit_d_9 <= bit_d_7;
                first_time <= 1'b1;
 
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_0 <= 1'b0;
                bit_c_2 <= 1'b0;
 
                bit_d_0 <= 1'b0;
                bit_d_2 <= 1'b0;
                bit_d_4 <= 1'b0;
                bit_d_6 <= 1'b0;
                bit_d_8 <= 1'b0;
        end
        else
        begin
 
                bit_c_0 <= rx_din;
                bit_c_2 <= bit_c_0;
 
                bit_d_0 <= rx_din;
                bit_d_2 <= bit_d_0;
                bit_d_4 <= bit_d_2;
                bit_d_6 <= bit_d_4;
                bit_d_8 <= bit_d_6;
        end
end
 
 
always@(*)
begin
        rx_got_fct = 1'b0;
 
        if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && check_c_d)
        begin
                rx_got_fct = 1'b1;
        end
end
 
always@(*)
begin
        dta_timec  = 10'd0;
        control_r          = 4'd0;
 
        if(counter_neg == 5'd2)
        begin
                control_r     = {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
        end
        else if(counter_neg == 5'd5)
        begin
                dta_timec   = {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
        end
end
 
 
always@(posedge negedge_clk)
begin
 
        if(!rx_resetn)
        begin
                is_control <= 1'b0;
                is_data    <= 1'b0;
 
                counter_neg <= 5'd0;
        end
        else
        begin
 
                if(counter_neg == 5'd1)
                begin
                        if(bit_c_0)
                        begin
                                is_control <= 1'b1;
                                is_data    <= 1'b0;
                        end
                        else
                        begin
                                is_control <= 1'b0;
                                is_data    <= 1'b1;
                        end
 
                        counter_neg <= counter_neg + 5'd1;
 
                end
                else
                begin
                        if(is_control)
                        begin
                                if(counter_neg == 5'd2)
                                begin
                                        counter_neg <= 5'd1;
                                        is_control  <= 1'b0;
                                end
                                else
                                        counter_neg <= counter_neg + 5'd1;
                        end
                        else if(is_data)
                        begin
                                if(counter_neg == 5'd5)
                                begin
                                        counter_neg <= 5'd1;
                                        is_data     <= 1'b0;
                                end
                                else
                                        counter_neg <= counter_neg + 5'd1;
                        end
                        else
                        begin
                                counter_neg <= counter_neg + 5'd1;
                        end
                end
        end
end
 
always@(*)
begin
 
        parity_error = 1'b0;
 
        if(last_is_control)
        begin
                if(last_was_control)
                begin
                        if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_timec)
                begin
                        if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_data)
                begin
                        if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
        end
        else if(last_is_data)
        begin
                if(last_was_control)
                begin
                        if(!(data[8]^control[1]^control[0]) != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_timec)
                begin
                        if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_data)
                begin
                        if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
        end
 
end
 
always@(posedge check_c_d or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
                control     <= 4'd0;
                control_l_r <= 4'd0;
 
                data            <= 10'd0;
                data_l_r        <= 10'd0;
                //rx_data_flag    <= 9'd0; 
                //rx_buffer_write <= 1'b0;
                //rx_data_take    <= 1'b0;
 
                timecode    <= 10'd0;
        //      rx_time_out <= 8'd0;
        //      rx_tick_out <= 1'b0;
 
                last_is_control <=1'b0;
                last_is_data    <=1'b0;
                last_is_timec   <=1'b0;
 
                last_was_control <=1'b0;
                last_was_data    <=1'b0;
                last_was_timec   <=1'b0;
 
        end
        else
        begin
 
                //rx_buffer_write <= rx_data_take;
                //rx_data_flag <= data[8:0];
 
                //rx_time_out <= timecode[7:0];
 
                if((control[2:0] != 3'd7 & is_data) == 1'b1)
                begin
 
                        data                    <= dta_timec;
                        data_l_r                <= data;
 
                        //rx_data_take <= 1'b1;
                        //rx_tick_out  <= 1'b0;
 
                        last_is_control         <=1'b0;
                        last_is_data            <=1'b1;
                        last_is_timec           <=1'b0;
                        last_was_control        <= last_is_control;
                        last_was_data           <= last_is_data ;
                        last_was_timec          <= last_is_timec;
                end
                else if((control[2:0] == 3'd7 & is_data) == 1'b1)
                begin
 
                        timecode                 <= dta_timec;
                        //rx_tick_out  <= 1'b1;
                        //rx_data_take <= 1'b0;
 
                        last_is_control         <= 1'b0;
                        last_is_data            <= 1'b0;
                        last_is_timec           <= 1'b1;
                        last_was_control        <= last_is_control;
                        last_was_data           <= last_is_data ;
                        last_was_timec          <= last_is_timec;
                end
                else if(control_r == 4'd6 || control_r == 4'd13 || control_r == 4'd5 || control_r == 4'd15 || control_r == 4'd7 || control_r == 4'd4 || control_r == 4'd12)
                begin
 
                        control          <= control_r;
                        control_l_r      <= control[3:0];
 
                        if((control[2:0] == 3'd6 & is_control) == 1'b1 )
                        begin
                                data <= 10'b0100000001;
                                //rx_data_take <= 1'b1;
                        end
                        else if(  (control[2:0] == 3'd5 & is_control) == 1'b1 )
                        begin
                                data <= 10'b0100000000;
                        //      rx_data_take <= 1'b1;
                        end
                        else
                        begin
                        //      rx_data_take    <= 1'b0;
                        end
 
                        //rx_tick_out  <= 1'b0;
 
                        last_is_control          <= 1'b1;
                        last_is_data             <= 1'b0;
                        last_is_timec            <= 1'b0;
                        last_was_control         <= last_is_control;
                        last_was_data            <= last_is_data ;
                        last_was_timec           <= last_is_timec;
                end
        end
end
 
endmodule

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[/] [spacewiresystemc/] [trunk/] [rtl/] [DEBUG_VERILOG/] [detector_tokens.v] - Blame information for rev 23

Line No.	Rev	Author	Line
1	23	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33			`module detector_tokens(`
34			`input rx_din,`
35			`input rx_sin,`
36			`input rx_resetn,`
37			`output [13:0] info`
38			`);`
39
40			`wire rx_error;`
41			`wire rx_got_bit;`
42			`wire rx_got_null;`
43			`wire rx_got_nchar;`
44			`wire rx_got_time_code;`
45			`reg rx_got_fct;`
46
47			`reg [4:0] counter_neg;`
48
49			`wire posedge_clk;`
50			`wire negedge_clk;`
51
52			`reg bit_c_0;//N`
53			`reg bit_c_1;//P`
54			`reg bit_c_2;//N`
55			`reg bit_c_3;//P`
56
57			`reg bit_d_0;//N`
58			`reg bit_d_1;//P`
59			`reg bit_d_2;//N`
60			`reg bit_d_3;//P`
61			`reg bit_d_4;//N`
62			`reg bit_d_5;//P`
63			`reg bit_d_6;//N`
64			`reg bit_d_7;//P`
65			`reg bit_d_8;//N`
66			`reg bit_d_9;//P`
67
68			`reg is_control;`
69			`reg is_data;`
70
71			`reg last_is_control;`
72			`reg last_is_data;`
73			`reg last_is_timec;`
74
75			`reg last_was_control;`
76			`reg last_was_data;`
77			`reg last_was_timec;`
78
79			`reg [3:0] control;`
80			`reg [3:0] control_r;`
81			`reg [9:0] data;`
82			`reg [9:0] timecode;`
83
84			`reg [9:0] dta_timec;`
85
86			`reg [3:0] control_l_r;`
87			`reg [9:0] data_l_r;`
88
89			`reg parity_error;`
90			`wire check_c_d;`
91
92			`reg rx_data_take;`
93
94			`reg first_time;`
95
96			`//CLOCK RECOVERY`
97			`assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;`
98			`assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;`
99
100			`assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 \| (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 \| (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;`
101
102			`assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;`
103			`//assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;`
104
105			`assign rx_got_bit = (posedge_clk)?1'b1:1'b0;`
106
107			`assign rx_error = parity_error;`
108
109			`assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;`
110			`assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;`
111
112			`assign info = {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};`
113
114			`always@(posedge posedge_clk or negedge rx_resetn)`
115			`begin`
116
117			`if(!rx_resetn)`
118			`begin`
119			`bit_c_1 <= 1'b0;`
120			`bit_c_3 <= 1'b0;`
121
122			`bit_d_1 <= 1'b0;`
123			`bit_d_3 <= 1'b0;`
124			`bit_d_5 <= 1'b0;`
125			`bit_d_7 <= 1'b0;`
126			`bit_d_9 <= 1'b0;`
127			`first_time <= 1'b0;`
128			`end`
129			`else`
130			`begin`
131			`bit_c_1 <= rx_din;`
132			`bit_c_3 <= bit_c_1;`
133
134			`bit_d_1 <= rx_din;`
135			`bit_d_3 <= bit_d_1;`
136			`bit_d_5 <= bit_d_3;`
137			`bit_d_7 <= bit_d_5;`
138			`bit_d_9 <= bit_d_7;`
139			`first_time <= 1'b1;`
140
141			`end`
142
143			`end`
144
145			`always@(posedge negedge_clk or negedge rx_resetn)`
146			`begin`
147
148			`if(!rx_resetn)`
149			`begin`
150			`bit_c_0 <= 1'b0;`
151			`bit_c_2 <= 1'b0;`
152
153			`bit_d_0 <= 1'b0;`
154			`bit_d_2 <= 1'b0;`
155			`bit_d_4 <= 1'b0;`
156			`bit_d_6 <= 1'b0;`
157			`bit_d_8 <= 1'b0;`
158			`end`
159			`else`
160			`begin`
161
162			`bit_c_0 <= rx_din;`
163			`bit_c_2 <= bit_c_0;`
164
165			`bit_d_0 <= rx_din;`
166			`bit_d_2 <= bit_d_0;`
167			`bit_d_4 <= bit_d_2;`
168			`bit_d_6 <= bit_d_4;`
169			`bit_d_8 <= bit_d_6;`
170			`end`
171			`end`
172
173
174			`always@(*)`
175			`begin`
176			`rx_got_fct = 1'b0;`
177
178			`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && check_c_d)`
179			`begin`
180			`rx_got_fct = 1'b1;`
181			`end`
182			`end`
183
184			`always@(*)`
185			`begin`
186			`dta_timec = 10'd0;`
187			`control_r = 4'd0;`
188
189			`if(counter_neg == 5'd2)`
190			`begin`
191			`control_r = {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
192			`end`
193			`else if(counter_neg == 5'd5)`
194			`begin`
195			`dta_timec = {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
196			`end`
197			`end`
198
199
200			`always@(posedge negedge_clk)`
201			`begin`
202
203			`if(!rx_resetn)`
204			`begin`
205			`is_control <= 1'b0;`
206			`is_data <= 1'b0;`
207
208			`counter_neg <= 5'd0;`
209			`end`
210			`else`
211			`begin`
212
213			`if(counter_neg == 5'd1)`
214			`begin`
215			`if(bit_c_0)`
216			`begin`
217			`is_control <= 1'b1;`
218			`is_data <= 1'b0;`
219			`end`
220			`else`
221			`begin`
222			`is_control <= 1'b0;`
223			`is_data <= 1'b1;`
224			`end`
225
226			`counter_neg <= counter_neg + 5'd1;`
227
228			`end`
229			`else`
230			`begin`
231			`if(is_control)`
232			`begin`
233			`if(counter_neg == 5'd2)`
234			`begin`
235			`counter_neg <= 5'd1;`
236			`is_control <= 1'b0;`
237			`end`
238			`else`
239			`counter_neg <= counter_neg + 5'd1;`
240			`end`
241			`else if(is_data)`
242			`begin`
243			`if(counter_neg == 5'd5)`
244			`begin`
245			`counter_neg <= 5'd1;`
246			`is_data <= 1'b0;`
247			`end`
248			`else`
249			`counter_neg <= counter_neg + 5'd1;`
250			`end`
251			`else`
252			`begin`
253			`counter_neg <= counter_neg + 5'd1;`
254			`end`
255			`end`
256			`end`
257			`end`
258
259			`always@(*)`
260			`begin`
261
262			`parity_error = 1'b0;`
263
264			`if(last_is_control)`
265			`begin`
266			`if(last_was_control)`
267			`begin`
268			`if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])`
269			`begin`
270			`parity_error = 1'b1;`
271			`end`
272			`end`
273			`else if(last_was_timec)`
274			`begin`
275			`if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])`
276			`begin`
277			`parity_error = 1'b1;`
278			`end`
279			`end`
280			`else if(last_was_data)`
281			`begin`
282			`if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])`
283			`begin`
284			`parity_error = 1'b1;`
285			`end`
286			`end`
287			`end`
288			`else if(last_is_data)`
289			`begin`
290			`if(last_was_control)`
291			`begin`
292			`if(!(data[8]^control[1]^control[0]) != data[9])`
293			`begin`
294			`parity_error = 1'b1;`
295			`end`
296			`end`
297			`else if(last_was_timec)`
298			`begin`
299			`if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])`
300			`begin`
301			`parity_error = 1'b1;`
302			`end`
303			`end`
304			`else if(last_was_data)`
305			`begin`
306			`if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])`
307			`begin`
308			`parity_error = 1'b1;`
309			`end`
310			`end`
311			`end`
312
313			`end`
314
315			`always@(posedge check_c_d or negedge rx_resetn )`
316			`begin`
317
318			`if(!rx_resetn)`
319			`begin`
320			`control <= 4'd0;`
321			`control_l_r <= 4'd0;`
322
323			`data <= 10'd0;`
324			`data_l_r <= 10'd0;`
325			`//rx_data_flag <= 9'd0;`
326			`//rx_buffer_write <= 1'b0;`
327			`//rx_data_take <= 1'b0;`
328
329			`timecode <= 10'd0;`
330			`// rx_time_out <= 8'd0;`
331			`// rx_tick_out <= 1'b0;`
332
333			`last_is_control <=1'b0;`
334			`last_is_data <=1'b0;`
335			`last_is_timec <=1'b0;`
336
337			`last_was_control <=1'b0;`
338			`last_was_data <=1'b0;`
339			`last_was_timec <=1'b0;`
340
341			`end`
342			`else`
343			`begin`
344
345			`//rx_buffer_write <= rx_data_take;`
346			`//rx_data_flag <= data[8:0];`
347
348			`//rx_time_out <= timecode[7:0];`
349
350			`if((control[2:0] != 3'd7 & is_data) == 1'b1)`
351			`begin`
352
353			`data <= dta_timec;`
354			`data_l_r <= data;`
355
356			`//rx_data_take <= 1'b1;`
357			`//rx_tick_out <= 1'b0;`
358
359			`last_is_control <=1'b0;`
360			`last_is_data <=1'b1;`
361			`last_is_timec <=1'b0;`
362			`last_was_control <= last_is_control;`
363			`last_was_data <= last_is_data ;`
364			`last_was_timec <= last_is_timec;`
365			`end`
366			`else if((control[2:0] == 3'd7 & is_data) == 1'b1)`
367			`begin`
368
369			`timecode <= dta_timec;`
370			`//rx_tick_out <= 1'b1;`
371			`//rx_data_take <= 1'b0;`
372
373			`last_is_control <= 1'b0;`
374			`last_is_data <= 1'b0;`
375			`last_is_timec <= 1'b1;`
376			`last_was_control <= last_is_control;`
377			`last_was_data <= last_is_data ;`
378			`last_was_timec <= last_is_timec;`
379			`end`
380			`else if(control_r == 4'd6 \|\| control_r == 4'd13 \|\| control_r == 4'd5 \|\| control_r == 4'd15 \|\| control_r == 4'd7 \|\| control_r == 4'd4 \|\| control_r == 4'd12)`
381			`begin`
382
383			`control <= control_r;`
384			`control_l_r <= control[3:0];`
385
386			`if((control[2:0] == 3'd6 & is_control) == 1'b1 )`
387			`begin`
388			`data <= 10'b0100000001;`
389			`//rx_data_take <= 1'b1;`
390			`end`
391			`else if( (control[2:0] == 3'd5 & is_control) == 1'b1 )`
392			`begin`
393			`data <= 10'b0100000000;`
394			`// rx_data_take <= 1'b1;`
395			`end`
396			`else`
397			`begin`
398			`// rx_data_take <= 1'b0;`
399			`end`
400
401			`//rx_tick_out <= 1'b0;`
402
403			`last_is_control <= 1'b1;`
404			`last_is_data <= 1'b0;`
405			`last_is_timec <= 1'b0;`
406			`last_was_control <= last_is_control;`
407			`last_was_data <= last_is_data ;`
408			`last_was_timec <= last_is_timec;`
409			`end`
410			`end`
411			`end`
412
413			`endmodule`