URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Blame information for rev 33

Go to most recent revision | Details | Compare with Previous | View Log


//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
module fifo_rx
#(
        parameter integer DWIDTH = 9,
        parameter integer AWIDTH = 6
)
 
(
        input clock, reset, wr_en, rd_en,
        input [DWIDTH-1:0] data_in,
        output reg f_full,f_empty,
        output reg open_slot_fct,
        output reg overflow_credit_error,
        output reg [DWIDTH-1:0] data_out,
        output reg [AWIDTH-1:0] counter
);
 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
        reg [AWIDTH-1:0] wr_ptr;
        reg [AWIDTH-1:0] rd_ptr;
 
        reg block_read;
        reg block_write;
 
        wire [AWIDTH-1:0] wr;
        wire [AWIDTH-1:0] rd;
 
        reg [AWIDTH-1:0] credit_counter;
 
//Write pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        wr_ptr <= {(AWIDTH){1'b0}};
                        block_write <= 1'b0;
                        overflow_credit_error<=1'b0;
                end
                else
                begin
                        if(block_write)
                        begin
                                if(!wr_en)
                                        block_write <= 1'b0;
                        end
                        else if (wr_en && !f_full)
                        begin
                                block_write <= 1'b1;
                                mem[wr_ptr]<=data_in;
                                wr_ptr <= wr;
                        end
 
                        if(wr_en && credit_counter > 6'd55)
                        begin
 
                                overflow_credit_error<=1'b1;
                        end
                end
        end
 
//FULL - EMPTY COUNTER
 
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        f_full  <= 1'b0;
                        f_empty <= 1'b1;
                        counter <= {(AWIDTH){1'b0}};
                        credit_counter <= 6'd55;
                end
                else
                begin
 
                        if (wr_en && !f_full && !block_write)
                        begin
                                if(rd_en && !f_empty && !block_read)
                                begin
                                        counter <= counter;
                                end
                                else
                                begin
                                        counter <= counter + 6'd1;
                                end
 
                                credit_counter <= credit_counter - 6'd1;
 
                        end
                        else if(rd_en && !f_empty && !block_read)
                        begin
                                if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
                                        credit_counter <= credit_counter + 6'd8;
 
                                counter <= counter - 6'd1;
                        end
 
 
 
 
                        if(counter == 6'd63)
                        begin
                                f_full <= 1'b1;
                        end
                        else
                        begin
                                f_full <= 1'b0;
                        end
 
                        if(counter == 6'd0)
                        begin
                                f_empty <= 1'b1;
                        end
                        else
                        begin
                                f_empty <= 1'b0;
                        end
 
                end
        end
 
//Read pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        rd_ptr <= {(AWIDTH){1'b0}};
                        data_out <= 9'd0;
                        open_slot_fct<= 1'b0;
                        block_read <= 1'b0;
                end
                else
                begin
 
                        if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
                        begin
                                open_slot_fct<= 1'b1;
                        end
                        else
                        begin
                                open_slot_fct<= 1'b0;
                        end
 
                        if(block_read == 1)
                        begin
                                if(!rd_en)
                                        block_read<= 1'b0;
 
                                data_out  <= mem[rd_ptr];
                        end
                        else
                        if(rd_en && !f_empty)
                        begin
                                rd_ptr <= rd;
                                block_read<= 1'b1;
                        end
                        else
                        begin
                                data_out  <= mem[rd_ptr];
                        end
                end
        end
 
        //assign f_empty   = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
        assign wr        = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
        assign rd        = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
 
endmodule

Line No.	Rev	Author	Line
1	33	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33			`module fifo_rx`
34			`#(`
35			`parameter integer DWIDTH = 9,`
36			`parameter integer AWIDTH = 6`
37			`)`
38
39			`(`
40			`input clock, reset, wr_en, rd_en,`
41			`input [DWIDTH-1:0] data_in,`
42			`output reg f_full,f_empty,`
43			`output reg open_slot_fct,`
44			`output reg overflow_credit_error,`
45			`output reg [DWIDTH-1:0] data_out,`
46			`output reg [AWIDTH-1:0] counter`
47			`);`
48
49			`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`
50
51			`reg [AWIDTH-1:0] wr_ptr;`
52			`reg [AWIDTH-1:0] rd_ptr;`
53
54			`reg block_read;`
55			`reg block_write;`
56
57			`wire [AWIDTH-1:0] wr;`
58			`wire [AWIDTH-1:0] rd;`
59
60			`reg [AWIDTH-1:0] credit_counter;`
61
62			`//Write pointer`
63			`always@(posedge clock or negedge reset)`
64			`begin`
65			`if (!reset)`
66			`begin`
67			`wr_ptr <= {(AWIDTH){1'b0}};`
68			`block_write <= 1'b0;`
69			`overflow_credit_error<=1'b0;`
70			`end`
71			`else`
72			`begin`
73			`if(block_write)`
74			`begin`
75			`if(!wr_en)`
76			`block_write <= 1'b0;`
77			`end`
78			`else if (wr_en && !f_full)`
79			`begin`
80			`block_write <= 1'b1;`
81			`mem[wr_ptr]<=data_in;`
82			`wr_ptr <= wr;`
83			`end`
84
85			`if(wr_en && credit_counter > 6'd55)`
86			`begin`
87
88			`overflow_credit_error<=1'b1;`
89			`end`
90			`end`
91			`end`
92
93			`//FULL - EMPTY COUNTER`
94
95			`always@(posedge clock or negedge reset)`
96			`begin`
97			`if (!reset)`
98			`begin`
99			`f_full <= 1'b0;`
100			`f_empty <= 1'b1;`
101			`counter <= {(AWIDTH){1'b0}};`
102			`credit_counter <= 6'd55;`
103			`end`
104			`else`
105			`begin`
106
107			`if (wr_en && !f_full && !block_write)`
108			`begin`
109			`if(rd_en && !f_empty && !block_read)`
110			`begin`
111			`counter <= counter;`
112			`end`
113			`else`
114			`begin`
115			`counter <= counter + 6'd1;`
116			`end`
117
118			`credit_counter <= credit_counter - 6'd1;`
119
120			`end`
121			`else if(rd_en && !f_empty && !block_read)`
122			`begin`
123			`if(rd_ptr == 6'd8 \|\| rd_ptr == 6'd16 \|\| rd_ptr == 6'd24 \|\| rd_ptr == 6'd32 \|\| rd_ptr == 6'd40 \|\| rd_ptr == 6'd48 \|\| rd_ptr == 6'd56 \|\| rd_ptr == 6'd63)`
124			`credit_counter <= credit_counter + 6'd8;`
125
126			`counter <= counter - 6'd1;`
127			`end`
128
129
130
131
132			`if(counter == 6'd63)`
133			`begin`
134			`f_full <= 1'b1;`
135			`end`
136			`else`
137			`begin`
138			`f_full <= 1'b0;`
139			`end`
140
141			`if(counter == 6'd0)`
142			`begin`
143			`f_empty <= 1'b1;`
144			`end`
145			`else`
146			`begin`
147			`f_empty <= 1'b0;`
148			`end`
149
150			`end`
151			`end`
152
153			`//Read pointer`
154			`always@(posedge clock or negedge reset)`
155			`begin`
156			`if (!reset)`
157			`begin`
158			`rd_ptr <= {(AWIDTH){1'b0}};`
159			`data_out <= 9'd0;`
160			`open_slot_fct<= 1'b0;`
161			`block_read <= 1'b0;`
162			`end`
163			`else`
164			`begin`
165
166			`if(rd_ptr == 6'd8 \|\| rd_ptr == 6'd16 \|\| rd_ptr == 6'd24 \|\| rd_ptr == 6'd32 \|\| rd_ptr == 6'd40 \|\| rd_ptr == 6'd48 \|\| rd_ptr == 6'd56 \|\| rd_ptr == 6'd63)`
167			`begin`
168			`open_slot_fct<= 1'b1;`
169			`end`
170			`else`
171			`begin`
172			`open_slot_fct<= 1'b0;`
173			`end`
174
175			`if(block_read == 1)`
176			`begin`
177			`if(!rd_en)`
178			`block_read<= 1'b0;`
179
180			`data_out <= mem[rd_ptr];`
181			`end`
182			`else`
183			`if(rd_en && !f_empty)`
184			`begin`
185			`rd_ptr <= rd;`
186			`block_read<= 1'b1;`
187			`end`
188			`else`
189			`begin`
190			`data_out <= mem[rd_ptr];`
191			`end`
192			`end`
193			`end`
194
195			`//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;`
196			`assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;`
197			`assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;`
198
199			`endmodule`

Browse

Tools

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_rx.v] - Blame information for rev 33