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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
module fifo_rx
#(
        parameter integer DWIDTH = 9,
        parameter integer AWIDTH = 6
)
 
(
        input clock, reset, wr_en, rd_en,
        input [DWIDTH-1:0] data_in,
        output reg f_full,f_empty,
        output reg open_slot_fct,
        output reg overflow_credit_error,
        output reg [DWIDTH-1:0] data_out,
        output reg [AWIDTH-1:0] counter
);
 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
        reg [AWIDTH-1:0] wr_ptr;
        reg [AWIDTH-1:0] rd_ptr;
 
        reg [AWIDTH-1:0] credit_counter;
 
        reg  [1:0] state_data_write;
        reg  [1:0] next_state_data_write;
 
        reg  [1:0] state_data_read;
        reg  [1:0] next_state_data_read;
 
 
/****************************************/
 
always@(*)
begin
        next_state_data_write = state_data_write;
 
        case(state_data_write)
        2'd0:
        begin
                if(wr_en && !f_full)
                begin
                        next_state_data_write = 2'd1;
                end
                else
                begin
                        next_state_data_write = 2'd0;
                end
        end
        2'd1:
        begin
                if(wr_en)
                begin
                        next_state_data_write = 2'd1;
                end
                else
                begin
                        next_state_data_write = 2'd2;
                end
        end
        2'd2:
        begin
                next_state_data_write = 2'd0;
        end
        default:
        begin
                next_state_data_write = 2'd0;
        end
        endcase
end
 
/****************************************/
 
always@(*)
begin
        next_state_data_read = state_data_read;
 
        case(state_data_read)
        2'd0:
        begin
                if(rd_en && !f_empty)
                begin
                        next_state_data_read = 2'd1;
                end
                else
                begin
                        next_state_data_read = 2'd0;
                end
        end
        2'd1:
        begin
                if(rd_en)
                begin
                        next_state_data_read = 2'd1;
                end
                else
                begin
                        next_state_data_read = 2'd2;
                end
        end
        2'd2:
        begin
                next_state_data_read = 2'd0;
        end
        default:
        begin
                next_state_data_read = 2'd0;
        end
        endcase
end
 
 
//Write pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        wr_ptr <= {(AWIDTH){1'b0}};
                        mem[0] <= {(DWIDTH){1'b0}};
                        mem[1] <= {(DWIDTH){1'b0}};
                        mem[2] <= {(DWIDTH){1'b0}};
                        mem[3] <= {(DWIDTH){1'b0}};
                        mem[4] <= {(DWIDTH){1'b0}};
                        mem[5] <= {(DWIDTH){1'b0}};
                        mem[6] <= {(DWIDTH){1'b0}};
                        mem[7] <= {(DWIDTH){1'b0}};
                        mem[8] <= {(DWIDTH){1'b0}};
                        mem[9] <= {(DWIDTH){1'b0}};
                        mem[10] <= {(DWIDTH){1'b0}};
 
                        mem[11] <= {(DWIDTH){1'b0}};
                        mem[12] <= {(DWIDTH){1'b0}};
                        mem[13] <= {(DWIDTH){1'b0}};
                        mem[14] <= {(DWIDTH){1'b0}};
                        mem[15] <= {(DWIDTH){1'b0}};
                        mem[16] <= {(DWIDTH){1'b0}};
                        mem[17] <= {(DWIDTH){1'b0}};
                        mem[18] <= {(DWIDTH){1'b0}};
                        mem[19] <= {(DWIDTH){1'b0}};
                        mem[20] <= {(DWIDTH){1'b0}};
                        mem[21] <= {(DWIDTH){1'b0}};
 
                        mem[22] <= {(DWIDTH){1'b0}};
                        mem[23] <= {(DWIDTH){1'b0}};
                        mem[24] <= {(DWIDTH){1'b0}};
                        mem[25] <= {(DWIDTH){1'b0}};
                        mem[26] <= {(DWIDTH){1'b0}};
                        mem[27] <= {(DWIDTH){1'b0}};
                        mem[28] <= {(DWIDTH){1'b0}};
                        mem[29] <= {(DWIDTH){1'b0}};
                        mem[30] <= {(DWIDTH){1'b0}};
                        mem[31] <= {(DWIDTH){1'b0}};
                        mem[32] <= {(DWIDTH){1'b0}};
 
 
                        mem[33] <= {(DWIDTH){1'b0}};
                        mem[34] <= {(DWIDTH){1'b0}};
                        mem[35] <= {(DWIDTH){1'b0}};
                        mem[36] <= {(DWIDTH){1'b0}};
                        mem[37] <= {(DWIDTH){1'b0}};
                        mem[38] <= {(DWIDTH){1'b0}};
                        mem[39] <= {(DWIDTH){1'b0}};
                        mem[40] <= {(DWIDTH){1'b0}};
                        mem[41] <= {(DWIDTH){1'b0}};
                        mem[42] <= {(DWIDTH){1'b0}};
                        mem[43] <= {(DWIDTH){1'b0}};
 
                        mem[44] <= {(DWIDTH){1'b0}};
                        mem[45] <= {(DWIDTH){1'b0}};
                        mem[46] <= {(DWIDTH){1'b0}};
                        mem[47] <= {(DWIDTH){1'b0}};
                        mem[48] <= {(DWIDTH){1'b0}};
                        mem[49] <= {(DWIDTH){1'b0}};
                        mem[50] <= {(DWIDTH){1'b0}};
                        mem[51] <= {(DWIDTH){1'b0}};
                        mem[52] <= {(DWIDTH){1'b0}};
                        mem[53] <= {(DWIDTH){1'b0}};
                        mem[54] <= {(DWIDTH){1'b0}};
 
                        mem[55] <= {(DWIDTH){1'b0}};
                        mem[56] <= {(DWIDTH){1'b0}};
                        mem[57] <= {(DWIDTH){1'b0}};
                        mem[58] <= {(DWIDTH){1'b0}};
                        mem[59] <= {(DWIDTH){1'b0}};
                        mem[60] <= {(DWIDTH){1'b0}};
                        mem[61] <= {(DWIDTH){1'b0}};
                        mem[62] <= {(DWIDTH){1'b0}};
                        mem[63] <= {(DWIDTH){1'b0}};
 
                        overflow_credit_error<=1'b0;
                        state_data_write <= 2'd0;
                end
                else
                begin
 
                        state_data_write <= next_state_data_write;
 
                        case(state_data_write)
                        2'd0:
                        begin
                                if(credit_counter > 6'd55)
                                begin
                                        overflow_credit_error <= 1'b1;
                                end
                                else
                                        overflow_credit_error <= 1'b0;
 
                                mem[wr_ptr]<=data_in;
                        end
                        2'd1:
                        begin
                                if(wr_en)
                                        mem[wr_ptr]<=data_in;
                                else
                                        mem[wr_ptr]<=mem[wr_ptr];
                        end
                        2'd2:
                        begin
                                wr_ptr <= wr_ptr + 6'd1;
                        end
                        default:
                        begin
                                mem[wr_ptr]<=mem[wr_ptr];
                                wr_ptr <= wr_ptr;
                        end
                        endcase
 
                end
        end
 
//FULL - EMPTY COUNTER
 
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        f_full  <= 1'b0;
                        f_empty <= 1'b1;
                        counter <= {(AWIDTH){1'b0}};
                        credit_counter <= 6'd55;
                end
                else
                begin
 
                        if (state_data_write == 2'd2)
                        begin
                                credit_counter   <= credit_counter - 6'd1;
                        end
                        else if(state_data_read == 2'd2)
                        begin
                                if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
                                begin
                                        if(credit_counter < 6'd48)
                                                credit_counter <= credit_counter + 6'd8;
                                        else
                                                credit_counter <= credit_counter + 6'd7;
                                end
                        end
                        else
                                credit_counter <= credit_counter;
 
                        if (state_data_write == 2'd2)
                        begin
                                if(counter == 6'd63)
                                        counter <= counter;
                                else
                                        counter <= counter + 6'd1;
                        end
                        else if(state_data_read == 2'd2)
                        begin
                                if(counter == 6'd0)
                                        counter <= counter;
                                else
                                        counter <= counter - 6'd1;
                        end
                        else
                        begin
                                counter <= counter;
                        end
 
                        if(counter == 6'd63)
                        begin
                                f_full <= 1'b1;
                        end
                        else
                        begin
                                f_full <= 1'b0;
                        end
 
                        if(counter == 6'd0)
                        begin
                                f_empty <= 1'b1;
                        end
                        else
                        begin
                                f_empty <= 1'b0;
                        end
                end
        end
 
//Read pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        rd_ptr <= {(AWIDTH){1'b0}};
                        data_out <= 9'd0;
                        open_slot_fct<= 1'b0;
                        state_data_read <= 2'd0;
                end
                else
                begin
 
                        state_data_read <= next_state_data_read;
 
                        case(state_data_read)
                        2'd0:
                        begin
                                if(rd_en)
                                begin
                                        data_out   <= data_out;
                                        open_slot_fct<= open_slot_fct;
                                        rd_ptr     <= rd_ptr+ 6'd1;
                                end
                                else
                                begin
                                        open_slot_fct<= open_slot_fct;
                                        data_out   <= mem[rd_ptr];
                                end
                        end
                        2'd1:
                        begin
                                if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
                                begin
                                        open_slot_fct<= 1'b1;
                                end
                                else
                                begin
                                        open_slot_fct<= 1'b0;
                                end
 
                                if(rd_en)
                                begin
                                        data_out   <= mem[rd_ptr];
                                end
                                else
                                begin
                                        data_out   <= data_out;
                                end
 
                        end
                        2'd2:
                        begin
                                open_slot_fct<= open_slot_fct;
                                data_out   <= data_out;
                        end
                        default:
                        begin
                                rd_ptr     <= rd_ptr;
                                data_out   <= data_out;
                        end
                        endcase
 
 
                end
        end
 
endmodule

Line No.	Rev	Author	Line
1	33	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33			`module fifo_rx`
34			`#(`
35			`parameter integer DWIDTH = 9,`
36			`parameter integer AWIDTH = 6`
37			`)`
38
39			`(`
40			`input clock, reset, wr_en, rd_en,`
41			`input [DWIDTH-1:0] data_in,`
42			`output reg f_full,f_empty,`
43			`output reg open_slot_fct,`
44			`output reg overflow_credit_error,`
45			`output reg [DWIDTH-1:0] data_out,`
46			`output reg [AWIDTH-1:0] counter`
47			`);`
48
49			`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`
50
51			`reg [AWIDTH-1:0] wr_ptr;`
52			`reg [AWIDTH-1:0] rd_ptr;`
53
54			`reg [AWIDTH-1:0] credit_counter;`
55
56	37	redbear	`reg [1:0] state_data_write;`
57			`reg [1:0] next_state_data_write;`
58
59			`reg [1:0] state_data_read;`
60			`reg [1:0] next_state_data_read;`
61
62
63			`/****************************************/`
64
65			`always@(*)`
66			`begin`
67			`next_state_data_write = state_data_write;`
68
69			`case(state_data_write)`
70			`2'd0:`
71			`begin`
72			`if(wr_en && !f_full)`
73			`begin`
74			`next_state_data_write = 2'd1;`
75			`end`
76			`else`
77			`begin`
78			`next_state_data_write = 2'd0;`
79			`end`
80			`end`
81			`2'd1:`
82			`begin`
83			`if(wr_en)`
84			`begin`
85			`next_state_data_write = 2'd1;`
86			`end`
87			`else`
88			`begin`
89			`next_state_data_write = 2'd2;`
90			`end`
91			`end`
92			`2'd2:`
93			`begin`
94			`next_state_data_write = 2'd0;`
95			`end`
96			`default:`
97			`begin`
98			`next_state_data_write = 2'd0;`
99			`end`
100			`endcase`
101			`end`
102
103			`/****************************************/`
104
105			`always@(*)`
106			`begin`
107			`next_state_data_read = state_data_read;`
108
109			`case(state_data_read)`
110			`2'd0:`
111			`begin`
112			`if(rd_en && !f_empty)`
113			`begin`
114			`next_state_data_read = 2'd1;`
115			`end`
116			`else`
117			`begin`
118			`next_state_data_read = 2'd0;`
119			`end`
120			`end`
121			`2'd1:`
122			`begin`
123			`if(rd_en)`
124			`begin`
125			`next_state_data_read = 2'd1;`
126			`end`
127			`else`
128			`begin`
129			`next_state_data_read = 2'd2;`
130			`end`
131			`end`
132			`2'd2:`
133			`begin`
134			`next_state_data_read = 2'd0;`
135			`end`
136			`default:`
137			`begin`
138			`next_state_data_read = 2'd0;`
139			`end`
140			`endcase`
141			`end`
142
143
144	33	redbear	`//Write pointer`
145			`always@(posedge clock or negedge reset)`
146			`begin`
147			`if (!reset)`
148			`begin`
149			`wr_ptr <= {(AWIDTH){1'b0}};`
150	34	redbear	`mem[0] <= {(DWIDTH){1'b0}};`
151			`mem[1] <= {(DWIDTH){1'b0}};`
152			`mem[2] <= {(DWIDTH){1'b0}};`
153			`mem[3] <= {(DWIDTH){1'b0}};`
154			`mem[4] <= {(DWIDTH){1'b0}};`
155			`mem[5] <= {(DWIDTH){1'b0}};`
156			`mem[6] <= {(DWIDTH){1'b0}};`
157			`mem[7] <= {(DWIDTH){1'b0}};`
158			`mem[8] <= {(DWIDTH){1'b0}};`
159			`mem[9] <= {(DWIDTH){1'b0}};`
160			`mem[10] <= {(DWIDTH){1'b0}};`
161
162			`mem[11] <= {(DWIDTH){1'b0}};`
163			`mem[12] <= {(DWIDTH){1'b0}};`
164			`mem[13] <= {(DWIDTH){1'b0}};`
165			`mem[14] <= {(DWIDTH){1'b0}};`
166			`mem[15] <= {(DWIDTH){1'b0}};`
167			`mem[16] <= {(DWIDTH){1'b0}};`
168			`mem[17] <= {(DWIDTH){1'b0}};`
169			`mem[18] <= {(DWIDTH){1'b0}};`
170			`mem[19] <= {(DWIDTH){1'b0}};`
171			`mem[20] <= {(DWIDTH){1'b0}};`
172			`mem[21] <= {(DWIDTH){1'b0}};`
173
174			`mem[22] <= {(DWIDTH){1'b0}};`
175			`mem[23] <= {(DWIDTH){1'b0}};`
176			`mem[24] <= {(DWIDTH){1'b0}};`
177			`mem[25] <= {(DWIDTH){1'b0}};`
178			`mem[26] <= {(DWIDTH){1'b0}};`
179			`mem[27] <= {(DWIDTH){1'b0}};`
180			`mem[28] <= {(DWIDTH){1'b0}};`
181			`mem[29] <= {(DWIDTH){1'b0}};`
182			`mem[30] <= {(DWIDTH){1'b0}};`
183			`mem[31] <= {(DWIDTH){1'b0}};`
184			`mem[32] <= {(DWIDTH){1'b0}};`
185
186
187			`mem[33] <= {(DWIDTH){1'b0}};`
188			`mem[34] <= {(DWIDTH){1'b0}};`
189			`mem[35] <= {(DWIDTH){1'b0}};`
190			`mem[36] <= {(DWIDTH){1'b0}};`
191			`mem[37] <= {(DWIDTH){1'b0}};`
192			`mem[38] <= {(DWIDTH){1'b0}};`
193			`mem[39] <= {(DWIDTH){1'b0}};`
194			`mem[40] <= {(DWIDTH){1'b0}};`
195			`mem[41] <= {(DWIDTH){1'b0}};`
196			`mem[42] <= {(DWIDTH){1'b0}};`
197			`mem[43] <= {(DWIDTH){1'b0}};`
198
199			`mem[44] <= {(DWIDTH){1'b0}};`
200			`mem[45] <= {(DWIDTH){1'b0}};`
201			`mem[46] <= {(DWIDTH){1'b0}};`
202			`mem[47] <= {(DWIDTH){1'b0}};`
203			`mem[48] <= {(DWIDTH){1'b0}};`
204			`mem[49] <= {(DWIDTH){1'b0}};`
205			`mem[50] <= {(DWIDTH){1'b0}};`
206			`mem[51] <= {(DWIDTH){1'b0}};`
207			`mem[52] <= {(DWIDTH){1'b0}};`
208			`mem[53] <= {(DWIDTH){1'b0}};`
209			`mem[54] <= {(DWIDTH){1'b0}};`
210
211			`mem[55] <= {(DWIDTH){1'b0}};`
212			`mem[56] <= {(DWIDTH){1'b0}};`
213			`mem[57] <= {(DWIDTH){1'b0}};`
214			`mem[58] <= {(DWIDTH){1'b0}};`
215			`mem[59] <= {(DWIDTH){1'b0}};`
216			`mem[60] <= {(DWIDTH){1'b0}};`
217			`mem[61] <= {(DWIDTH){1'b0}};`
218			`mem[62] <= {(DWIDTH){1'b0}};`
219			`mem[63] <= {(DWIDTH){1'b0}};`
220	37	redbear
221	33	redbear	`overflow_credit_error<=1'b0;`
222	37	redbear	`state_data_write <= 2'd0;`
223	33	redbear	`end`
224			`else`
225			`begin`
226	37	redbear
227			`state_data_write <= next_state_data_write;`
228
229			`case(state_data_write)`
230			`2'd0:`
231	33	redbear	`begin`
232	38	redbear	`if(credit_counter > 6'd55)`
233			`begin`
234			`overflow_credit_error <= 1'b1;`
235			`end`
236			`else`
237			`overflow_credit_error <= 1'b0;`
238
239	37	redbear	`mem[wr_ptr]<=data_in;`
240	33	redbear	`end`
241	37	redbear	`2'd1:`
242	33	redbear	`begin`
243	38	redbear	`if(wr_en)`
244			`mem[wr_ptr]<=data_in;`
245			`else`
246			`mem[wr_ptr]<=mem[wr_ptr];`
247	33	redbear	`end`
248	37	redbear	`2'd2:`
249			`begin`
250			`wr_ptr <= wr_ptr + 6'd1;`
251			`end`
252			`default:`
253			`begin`
254			`mem[wr_ptr]<=mem[wr_ptr];`
255			`wr_ptr <= wr_ptr;`
256			`end`
257			`endcase`
258	38	redbear
259	33	redbear	`end`
260			`end`
261
262			`//FULL - EMPTY COUNTER`
263
264			`always@(posedge clock or negedge reset)`
265			`begin`
266			`if (!reset)`
267			`begin`
268			`f_full <= 1'b0;`
269			`f_empty <= 1'b1;`
270			`counter <= {(AWIDTH){1'b0}};`
271			`credit_counter <= 6'd55;`
272			`end`
273			`else`
274			`begin`
275
276	37	redbear	`if (state_data_write == 2'd2)`
277	33	redbear	`begin`
278	34	redbear	`credit_counter <= credit_counter - 6'd1;`
279			`end`
280	37	redbear	`else if(state_data_read == 2'd2)`
281	33	redbear	`begin`
282	36	redbear	`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`
283	37	redbear	`begin`
284			`if(credit_counter < 6'd48)`
285			`credit_counter <= credit_counter + 6'd8;`
286			`else`
287			`credit_counter <= credit_counter + 6'd7;`
288	34	redbear	`end`
289			`end`
290			`else`
291			`credit_counter <= credit_counter;`
292	33	redbear
293	37	redbear	`if (state_data_write == 2'd2)`
294	34	redbear	`begin`
295	37	redbear	`if(counter == 6'd63)`
296			`counter <= counter;`
297			`else`
298			`counter <= counter + 6'd1;`
299	34	redbear	`end`
300	37	redbear	`else if(state_data_read == 2'd2)`
301	34	redbear	`begin`
302	37	redbear	`if(counter == 6'd0)`
303			`counter <= counter;`
304			`else`
305			`counter <= counter - 6'd1;`
306	34	redbear	`end`
307			`else`
308			`begin`
309			`counter <= counter;`
310			`end`
311	33	redbear
312			`if(counter == 6'd63)`
313			`begin`
314			`f_full <= 1'b1;`
315			`end`
316			`else`
317			`begin`
318			`f_full <= 1'b0;`
319			`end`
320
321			`if(counter == 6'd0)`
322			`begin`
323			`f_empty <= 1'b1;`
324			`end`
325			`else`
326			`begin`
327			`f_empty <= 1'b0;`
328			`end`
329			`end`
330			`end`
331
332			`//Read pointer`
333			`always@(posedge clock or negedge reset)`
334			`begin`
335			`if (!reset)`
336			`begin`
337			`rd_ptr <= {(AWIDTH){1'b0}};`
338			`data_out <= 9'd0;`
339			`open_slot_fct<= 1'b0;`
340	37	redbear	`state_data_read <= 2'd0;`
341	33	redbear	`end`
342			`else`
343			`begin`
344	37	redbear
345			`state_data_read <= next_state_data_read;`
346	33	redbear
347	37	redbear	`case(state_data_read)`
348			`2'd0:`
349	33	redbear	`begin`
350	37	redbear	`if(rd_en)`
351			`begin`
352			`data_out <= data_out;`
353			`open_slot_fct<= open_slot_fct;`
354			`rd_ptr <= rd_ptr+ 6'd1;`
355			`end`
356			`else`
357			`begin`
358			`open_slot_fct<= open_slot_fct;`
359			`data_out <= mem[rd_ptr];`
360			`end`
361	33	redbear	`end`
362	37	redbear	`2'd1:`
363	33	redbear	`begin`
364	37	redbear	`if(rd_ptr == 6'd7 \|\| rd_ptr == 6'd15 \|\| rd_ptr == 6'd23 \|\| rd_ptr == 6'd31 \|\| rd_ptr == 6'd39 \|\| rd_ptr == 6'd47 \|\| rd_ptr == 6'd55 \|\| rd_ptr == 6'd63)`
365	34	redbear	`begin`
366	37	redbear	`open_slot_fct<= 1'b1;`
367	34	redbear	`end`
368	37	redbear	`else`
369			`begin`
370			`open_slot_fct<= 1'b0;`
371			`end`
372
373	38	redbear	`if(rd_en)`
374			`begin`
375			`data_out <= mem[rd_ptr];`
376			`end`
377			`else`
378			`begin`
379			`data_out <= data_out;`
380			`end`
381
382	37	redbear	`end`
383			`2'd2:`
384	33	redbear	`begin`
385	37	redbear	`open_slot_fct<= open_slot_fct;`
386			`data_out <= data_out;`
387	33	redbear	`end`
388	37	redbear	`default:`
389			`begin`
390			`rd_ptr <= rd_ptr;`
391			`data_out <= data_out;`
392			`end`
393			`endcase`
394	34	redbear
395	37	redbear
396	33	redbear	`end`
397			`end`
398
399			`endmodule`

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