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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fifo_tx.v] - Blame information for rev 36

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1 33 redbear 
//+FHDR------------------------------------------------------------------------
2 
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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module fifo_tx
34 
#(
35 
        parameter integer DWIDTH = 9,
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        parameter integer AWIDTH = 6
37 
)
38 
 
39 
(
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        input clock, reset, wr_en, rd_en,
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        input [DWIDTH-1:0] data_in,
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        output reg f_full,write_tx,f_empty,
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        output reg [DWIDTH-1:0] data_out,
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        output reg [AWIDTH-1:0] counter
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);
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47 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
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49 
        reg [AWIDTH-1:0] wr_ptr;
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        reg [AWIDTH-1:0] rd_ptr;
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52 
        reg block_read;
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        reg block_write;
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55 
//Write pointer
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        always@(posedge clock or negedge reset)
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        begin
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                if (!reset)
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                begin
60 34 redbear 
                        mem[0]  <= {(DWIDTH){1'b0}};
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                        mem[1]  <= {(DWIDTH){1'b0}};
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                        mem[2]  <= {(DWIDTH){1'b0}};
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                        mem[3]  <= {(DWIDTH){1'b0}};
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                        mem[4]  <= {(DWIDTH){1'b0}};
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                        mem[5]  <= {(DWIDTH){1'b0}};
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                        mem[6]  <= {(DWIDTH){1'b0}};
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                        mem[7]  <= {(DWIDTH){1'b0}};
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                        mem[8]  <= {(DWIDTH){1'b0}};
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                        mem[9]  <= {(DWIDTH){1'b0}};
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                        mem[10] <= {(DWIDTH){1'b0}};
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                        mem[11] <= {(DWIDTH){1'b0}};
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                        mem[12] <= {(DWIDTH){1'b0}};
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                        mem[13] <= {(DWIDTH){1'b0}};
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                        mem[14] <= {(DWIDTH){1'b0}};
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                        mem[15] <= {(DWIDTH){1'b0}};
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                        mem[16] <= {(DWIDTH){1'b0}};
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                        mem[17] <= {(DWIDTH){1'b0}};
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                        mem[18] <= {(DWIDTH){1'b0}};
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                        mem[19] <= {(DWIDTH){1'b0}};
81 
                        mem[20] <= {(DWIDTH){1'b0}};
82 
                        mem[21] <= {(DWIDTH){1'b0}};
83 
 
84 
                        mem[22] <= {(DWIDTH){1'b0}};
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                        mem[23] <= {(DWIDTH){1'b0}};
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                        mem[24] <= {(DWIDTH){1'b0}};
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                        mem[25] <= {(DWIDTH){1'b0}};
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                        mem[26] <= {(DWIDTH){1'b0}};
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                        mem[27] <= {(DWIDTH){1'b0}};
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                        mem[28] <= {(DWIDTH){1'b0}};
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                        mem[29] <= {(DWIDTH){1'b0}};
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                        mem[30] <= {(DWIDTH){1'b0}};
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                        mem[31] <= {(DWIDTH){1'b0}};
94 
                        mem[32] <= {(DWIDTH){1'b0}};
95 
 
96 
 
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                        mem[33] <= {(DWIDTH){1'b0}};
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                        mem[34] <= {(DWIDTH){1'b0}};
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                        mem[35] <= {(DWIDTH){1'b0}};
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                        mem[36] <= {(DWIDTH){1'b0}};
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                        mem[37] <= {(DWIDTH){1'b0}};
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                        mem[38] <= {(DWIDTH){1'b0}};
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                        mem[39] <= {(DWIDTH){1'b0}};
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                        mem[40] <= {(DWIDTH){1'b0}};
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                        mem[41] <= {(DWIDTH){1'b0}};
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                        mem[42] <= {(DWIDTH){1'b0}};
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                        mem[43] <= {(DWIDTH){1'b0}};
108 
 
109 
                        mem[44] <= {(DWIDTH){1'b0}};
110 
                        mem[45] <= {(DWIDTH){1'b0}};
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                        mem[46] <= {(DWIDTH){1'b0}};
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                        mem[47] <= {(DWIDTH){1'b0}};
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                        mem[48] <= {(DWIDTH){1'b0}};
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                        mem[49] <= {(DWIDTH){1'b0}};
115 
                        mem[50] <= {(DWIDTH){1'b0}};
116 
                        mem[51] <= {(DWIDTH){1'b0}};
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                        mem[52] <= {(DWIDTH){1'b0}};
118 
                        mem[53] <= {(DWIDTH){1'b0}};
119 
                        mem[54] <= {(DWIDTH){1'b0}};
120 
 
121 
                        mem[55] <= {(DWIDTH){1'b0}};
122 
                        mem[56] <= {(DWIDTH){1'b0}};
123 
                        mem[57] <= {(DWIDTH){1'b0}};
124 
                        mem[58] <= {(DWIDTH){1'b0}};
125 
                        mem[59] <= {(DWIDTH){1'b0}};
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                        mem[60] <= {(DWIDTH){1'b0}};
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                        mem[61] <= {(DWIDTH){1'b0}};
128 
                        mem[62] <= {(DWIDTH){1'b0}};
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                        mem[63] <= {(DWIDTH){1'b0}};
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131 
                        wr_ptr      <= {(AWIDTH){1'b0}};
132 33 redbear 
                        block_write <= 1'b0;
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                end
134 34 redbear 
                else
135 33 redbear 
                begin
136 34 redbear 
 
137 
                        if(block_write)
138 
                        begin
139 
                                if(!wr_en)
140 
                                begin
141 
                                        block_write <= 1'b0;
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                                        wr_ptr <= wr_ptr + 6'd1;
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                                end
144 
                        end
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                        else if (wr_en && !f_full)
146 
                        begin
147 
                                block_write <= 1'b1;
148 
                                mem[wr_ptr]<=data_in;
149 
                        end
150 33 redbear 
                end
151 
        end
152 
 
153 
//FULL - EMPTY COUNTER
154 
 
155 
        always@(posedge clock or negedge reset)
156 
        begin
157 
                if (!reset)
158 
                begin
159 34 redbear 
                        f_full  <= 1'b0;
160 
                        f_empty <= 1'b1;
161 33 redbear 
                        counter <= {(AWIDTH){1'b0}};
162 
                end
163 
                else
164 
                begin
165 
 
166 34 redbear 
                        if((wr_en && !f_full && !block_write) && (rd_en && !f_empty && !block_read))
167 33 redbear 
                        begin
168 34 redbear 
                                counter <= counter;
169 33 redbear 
                        end
170 34 redbear 
                        else if (wr_en && !f_full && !block_write)
171 
                        begin
172 
                                counter <= counter + 6'd1;
173 
                        end
174 33 redbear 
                        else if(rd_en && !f_empty && !block_read)
175 
                        begin
176 
                                counter <= counter - 6'd1;
177 
                        end
178 34 redbear 
                        else
179 
                        begin
180 
                                counter <= counter;
181 
                        end
182 33 redbear 
 
183 
                        if(counter == 6'd63)
184 
                        begin
185 
                                f_full <= 1'b1;
186 
                        end
187 
                        else
188 
                        begin
189 
                                f_full <= 1'b0;
190 
                        end
191 
 
192 
                        if(counter == 6'd0)
193 
                        begin
194 
                                f_empty <= 1'b1;
195 
                        end
196 
                        else
197 
                        begin
198 
                                f_empty <= 1'b0;
199 
                        end
200 
 
201 
                end
202 
        end
203 
 
204 
//Read pointer
205 
        always@(posedge clock or negedge reset)
206 
        begin
207 
                if (!reset)
208 
                begin
209 34 redbear 
                        rd_ptr     <= {(AWIDTH){1'b0}};
210 
                        data_out   <= 9'd0;
211 
                        write_tx   <= 1'b0;
212 33 redbear 
                        block_read <= 1'b0;
213 
                end
214 
                else
215 
                begin
216 
 
217 34 redbear 
                        if(block_read)
218 33 redbear 
                        begin
219 
                                if(!rd_en)
220 34 redbear 
                                begin
221 33 redbear 
                                        block_read<= 1'b0;
222 34 redbear 
                                end
223 33 redbear 
                        end
224 
                        else if(rd_en && !f_empty)
225 
                        begin
226 
                                block_read<= 1'b1;
227 36 redbear 
                                rd_ptr <= rd_ptr+ 6'd1;
228 33 redbear 
                        end
229 
 
230 34 redbear 
                        data_out  <= mem[rd_ptr];
231 
 
232 
                        if(rd_en)
233 33 redbear 
                        begin
234 
                                write_tx<= 1'b0;
235 
                        end
236 
                        else if(counter > 6'd0)
237 
                        begin
238 
                                write_tx<= 1'b1;
239 
                        end
240 
                        else
241 
                                write_tx<= write_tx;
242 
 
243 
                end
244 
        end
245 
 
246 
endmodule

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