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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module FSM_SPW (
                input  pclk,
                input  resetn,
 
                //fsm status control
                input  auto_start,
                input  link_start,
                input  link_disable,
 
                //rx status input control
                input  rx_error,
                input  rx_credit_error,
                input  rx_got_bit,
                input  rx_got_null,
                input  rx_got_nchar,
                input  rx_got_time_code,
                input  rx_got_fct,
                output reg rx_resetn,
 
                //tx status control
                output reg enable_tx,
                output reg send_null_tx,
                output reg send_fct_tx,
 
                output [5:0] fsm_state
 
              );
 
localparam [5:0]  error_reset   = 6'b00_0000,
                  error_wait    = 6'b00_0001,
                  ready         = 6'b00_0010,
                  started       = 6'b00_0100,
                  connecting    = 6'b00_1000,
                  run           = 6'b01_0000;
 
        reg [5:0] state_fsm;
        reg [5:0] next_state_fsm;
 
        reg [11:0] after128us;
        reg [11:0] after64us;
        reg [11:0] after850ns;
 
        reg got_bit_internal;
 
        reg get_rx_got_fct_a, get_rx_got_fct_b;
        reg get_rx_error_a, get_rx_error_b;
        reg get_rx_got_null_a, get_rx_got_null_b;
 
        reg get_rx_got_nchar_a, get_rx_got_nchar_b;
        reg get_rx_got_time_code_a, get_rx_got_time_code_b;
        reg get_rx_credit_error_a, get_rx_credit_error_b;
 
//
assign fsm_state    = state_fsm;
 
always@(*)
begin
 
        next_state_fsm = state_fsm;
 
        case(state_fsm)
        error_reset:
        begin
 
                if(after64us == 12'd639)
                begin
                        next_state_fsm = error_wait;
                end
                else
                begin
                        next_state_fsm = error_reset;
                end
 
        end
        error_wait:
        begin
 
                if(after128us == 12'd1279)
                begin
                        next_state_fsm = ready;
                end
                else if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | rx_got_time_code)
                begin
                        next_state_fsm = error_reset;
                end
 
        end
        ready:
        begin
 
                if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | get_rx_got_time_code_a)
                begin
                        next_state_fsm = error_reset;
                end
                else if(((!link_disable) & (link_start |(auto_start & get_rx_got_null_a)))==1'b1)
                begin
                        next_state_fsm = started;
                end
 
        end
        started:
        begin
 
                if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | get_rx_got_time_code_a | after128us == 12'd1279)
                begin
                        next_state_fsm = error_reset;
                end
                else if((get_rx_got_null_a & rx_got_bit)== 1'b1)
                begin
                        next_state_fsm = connecting;
                end
 
        end
        connecting:
        begin
 
                if(get_rx_error_a | get_rx_got_nchar_a | get_rx_got_time_code_a | after128us == 12'd1279)
                begin
                        next_state_fsm = error_reset;
                end
                else if(get_rx_got_fct_a)
                begin
                        next_state_fsm = run;
                end
 
        end
        run:
        begin
 
                if(get_rx_error_a | get_rx_credit_error_a | link_disable  | after850ns == 12'd85)
                begin
                        next_state_fsm = error_reset;
                end
                else
                begin
                        next_state_fsm = run;
                end
 
        end
        endcase
end
 
always@(posedge pclk or negedge resetn)
begin
        if(!resetn)
        begin
                state_fsm <= error_reset;
 
                rx_resetn <= 1'b0;
 
                enable_tx    <= 1'b0;
                send_null_tx <= 1'b0;
                send_fct_tx  <= 1'b0;
 
                get_rx_got_fct_a  <= 1'b0;
                get_rx_got_fct_b  <= 1'b0;
                get_rx_error_a    <= 1'b0;
                get_rx_error_b    <= 1'b0;
                get_rx_got_null_a <= 1'b0;
                get_rx_got_null_b <= 1'b0;
 
 
                get_rx_got_nchar_a     <= 1'b0;
                get_rx_got_nchar_b     <= 1'b0;
                get_rx_got_time_code_a <= 1'b0;
                get_rx_got_time_code_b <= 1'b0;
                get_rx_credit_error_a  <= 1'b0;
                get_rx_credit_error_b  <= 1'b0;
 
        end
        else
        begin
 
                get_rx_got_fct_b <= rx_got_fct;
                get_rx_got_fct_a <= get_rx_got_fct_b;
 
                get_rx_error_b <= rx_error;
                get_rx_error_a <= get_rx_error_b;
 
                get_rx_got_null_b <= rx_got_null;
                get_rx_got_null_a <= get_rx_got_null_b;
 
                get_rx_got_nchar_b <= rx_got_nchar;
                get_rx_got_nchar_a <= get_rx_got_nchar_b;
 
                get_rx_got_time_code_b <= rx_got_time_code;
                get_rx_got_time_code_a <= get_rx_got_time_code_b;
 
                get_rx_credit_error_b <= rx_credit_error;
                get_rx_credit_error_a <= get_rx_credit_error_b;
 
                state_fsm <= next_state_fsm;
 
                case(state_fsm)
                error_reset:
                begin
                        enable_tx<= 1'b0;
                        send_null_tx<= 1'b0;
                        send_fct_tx<= 1'b0;
 
                        if(after64us == 12'd639)
                                rx_resetn <= 1'b1;
                        else
                                rx_resetn <= 1'b0;
                end
                error_wait:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b0;
                        send_null_tx<= 1'b0;
                        send_fct_tx<= 1'b0;
                end
                ready:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b0;
                        send_fct_tx<= 1'b0;
                end
                started:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b1;
                        send_fct_tx<= 1'b0;
                end
                connecting:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b1;
                        send_fct_tx<= 1'b1;
                end
                run:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b1;
                        send_fct_tx<= 1'b1;
                end
                endcase
 
        end
end
 
always@(posedge pclk)
begin
 
        if(!resetn || state_fsm == error_reset)
        begin
                after128us <= 12'd0;
        end
        else
        begin
 
                if(next_state_fsm == connecting && state_fsm == started)
                begin
                        after128us <= 12'd0;
                end
                else if(state_fsm == error_wait || state_fsm == started || state_fsm == connecting)
                begin
                        if(after128us < 12'd1279)
                                after128us <= after128us + 12'd1;
                        else
                                after128us <= 12'd0;
                end
                else
                begin
                                after128us <= 12'd0;
                end
        end
 
end
 
always@(posedge pclk)
begin
 
        if(!resetn)
        begin
                after64us <= 12'd0;
        end
        else
        begin
                if(state_fsm == error_reset && (auto_start | link_start))
                begin
                        if(after64us < 12'd639)
                                after64us <= after64us + 12'd1;
                        else
                                after64us <= 12'd0;
                end
                else
                begin
                        after64us <= 12'd0;
                end
        end
 
end
 
always@(posedge pclk)
begin
        if(!resetn)
        begin
                got_bit_internal <= 1'b0;
        end
        else
        begin
                if(rx_got_bit)
                        got_bit_internal <= 1'b1;
                else
                        got_bit_internal <= 1'b0;
        end
end
 
always@(posedge pclk)
begin
 
        if(!resetn | got_bit_internal)
        begin
                after850ns <= 12'd0;
        end
        else
        begin
                if(state_fsm != run)
                begin
                        after850ns <= 12'd0;
                end
                else
                begin
                        if(after850ns < 12'd85 && state_fsm == run)
                                after850ns <= after850ns + 12'd1;
                        else
                                after850ns <= after850ns;
 
                end
        end
 
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module FSM_SPW (`
37			`input pclk,`
38			`input resetn,`
39
40			`//fsm status control`
41			`input auto_start,`
42			`input link_start,`
43			`input link_disable,`
44
45			`//rx status input control`
46			`input rx_error,`
47			`input rx_credit_error,`
48			`input rx_got_bit,`
49			`input rx_got_null,`
50			`input rx_got_nchar,`
51			`input rx_got_time_code,`
52			`input rx_got_fct,`
53	33	redbear	`output reg rx_resetn,`
54	5	redbear
55			`//tx status control`
56	33	redbear	`output reg enable_tx,`
57			`output reg send_null_tx,`
58			`output reg send_fct_tx,`
59	5	redbear
60			`output [5:0] fsm_state`
61
62			`);`
63
64			`localparam [5:0] error_reset = 6'b00_0000,`
65			`error_wait = 6'b00_0001,`
66			`ready = 6'b00_0010,`
67			`started = 6'b00_0100,`
68			`connecting = 6'b00_1000,`
69			`run = 6'b01_0000;`
70
71			`reg [5:0] state_fsm;`
72			`reg [5:0] next_state_fsm;`
73
74			`reg [11:0] after128us;`
75			`reg [11:0] after64us;`
76			`reg [11:0] after850ns;`
77
78	33	redbear	`reg got_bit_internal;`
79	5	redbear
80	40	redbear	`reg get_rx_got_fct_a, get_rx_got_fct_b;`
81			`reg get_rx_error_a, get_rx_error_b;`
82			`reg get_rx_got_null_a, get_rx_got_null_b;`
83
84			`reg get_rx_got_nchar_a, get_rx_got_nchar_b;`
85			`reg get_rx_got_time_code_a, get_rx_got_time_code_b;`
86			`reg get_rx_credit_error_a, get_rx_credit_error_b;`
87
88	5	redbear	`//`
89			`assign fsm_state = state_fsm;`
90
91			`always@(*)`
92			`begin`
93
94			`next_state_fsm = state_fsm;`
95
96			`case(state_fsm)`
97			`error_reset:`
98			`begin`
99
100			`if(after64us == 12'd639)`
101			`begin`
102			`next_state_fsm = error_wait;`
103			`end`
104			`else`
105			`begin`
106			`next_state_fsm = error_reset;`
107			`end`
108
109			`end`
110			`error_wait:`
111			`begin`
112
113			`if(after128us == 12'd1279)`
114			`begin`
115			`next_state_fsm = ready;`
116			`end`
117	40	redbear	`else if(get_rx_error_a \| get_rx_got_fct_a \| get_rx_got_nchar_a \| rx_got_time_code)`
118	5	redbear	`begin`
119			`next_state_fsm = error_reset;`
120			`end`
121
122			`end`
123			`ready:`
124			`begin`
125
126	40	redbear	`if(get_rx_error_a \| get_rx_got_fct_a \| get_rx_got_nchar_a \| get_rx_got_time_code_a)`
127	5	redbear	`begin`
128			`next_state_fsm = error_reset;`
129			`end`
130	40	redbear	`else if(((!link_disable) & (link_start \|(auto_start & get_rx_got_null_a)))==1'b1)`
131	5	redbear	`begin`
132			`next_state_fsm = started;`
133			`end`
134
135			`end`
136			`started:`
137			`begin`
138
139	40	redbear	`if(get_rx_error_a \| get_rx_got_fct_a \| get_rx_got_nchar_a \| get_rx_got_time_code_a \| after128us == 12'd1279)`
140	5	redbear	`begin`
141			`next_state_fsm = error_reset;`
142			`end`
143	40	redbear	`else if((get_rx_got_null_a & rx_got_bit)== 1'b1)`
144	5	redbear	`begin`
145			`next_state_fsm = connecting;`
146			`end`
147
148			`end`
149			`connecting:`
150			`begin`
151
152	40	redbear	`if(get_rx_error_a \| get_rx_got_nchar_a \| get_rx_got_time_code_a \| after128us == 12'd1279)`
153	5	redbear	`begin`
154			`next_state_fsm = error_reset;`
155			`end`
156	40	redbear	`else if(get_rx_got_fct_a)`
157	5	redbear	`begin`
158			`next_state_fsm = run;`
159			`end`
160
161			`end`
162			`run:`
163			`begin`
164
165	40	redbear	`if(get_rx_error_a \| get_rx_credit_error_a \| link_disable \| after850ns == 12'd85)`
166	5	redbear	`begin`
167			`next_state_fsm = error_reset;`
168			`end`
169			`else`
170			`begin`
171			`next_state_fsm = run;`
172			`end`
173
174			`end`
175			`endcase`
176			`end`
177
178	33	redbear	`always@(posedge pclk or negedge resetn)`
179	5	redbear	`begin`
180			`if(!resetn)`
181			`begin`
182			`state_fsm <= error_reset;`
183	33	redbear
184			`rx_resetn <= 1'b0;`
185
186	40	redbear	`enable_tx <= 1'b0;`
187			`send_null_tx <= 1'b0;`
188			`send_fct_tx <= 1'b0;`
189
190			`get_rx_got_fct_a <= 1'b0;`
191			`get_rx_got_fct_b <= 1'b0;`
192			`get_rx_error_a <= 1'b0;`
193			`get_rx_error_b <= 1'b0;`
194			`get_rx_got_null_a <= 1'b0;`
195			`get_rx_got_null_b <= 1'b0;`
196
197
198			`get_rx_got_nchar_a <= 1'b0;`
199			`get_rx_got_nchar_b <= 1'b0;`
200			`get_rx_got_time_code_a <= 1'b0;`
201			`get_rx_got_time_code_b <= 1'b0;`
202			`get_rx_credit_error_a <= 1'b0;`
203			`get_rx_credit_error_b <= 1'b0;`
204
205	5	redbear	`end`
206			`else`
207			`begin`
208
209	40	redbear	`get_rx_got_fct_b <= rx_got_fct;`
210			`get_rx_got_fct_a <= get_rx_got_fct_b;`
211
212			`get_rx_error_b <= rx_error;`
213			`get_rx_error_a <= get_rx_error_b;`
214
215			`get_rx_got_null_b <= rx_got_null;`
216			`get_rx_got_null_a <= get_rx_got_null_b;`
217
218			`get_rx_got_nchar_b <= rx_got_nchar;`
219			`get_rx_got_nchar_a <= get_rx_got_nchar_b;`
220
221			`get_rx_got_time_code_b <= rx_got_time_code;`
222			`get_rx_got_time_code_a <= get_rx_got_time_code_b;`
223
224			`get_rx_credit_error_b <= rx_credit_error;`
225			`get_rx_credit_error_a <= get_rx_credit_error_b;`
226
227	5	redbear	`state_fsm <= next_state_fsm;`
228
229			`case(state_fsm)`
230			`error_reset:`
231			`begin`
232	33	redbear	`enable_tx<= 1'b0;`
233			`send_null_tx<= 1'b0;`
234			`send_fct_tx<= 1'b0;`
235
236			`if(after64us == 12'd639)`
237			`rx_resetn <= 1'b1;`
238			`else`
239			`rx_resetn <= 1'b0;`
240	5	redbear	`end`
241			`error_wait:`
242			`begin`
243	33	redbear	`rx_resetn <= 1'b1;`
244			`enable_tx<= 1'b0;`
245			`send_null_tx<= 1'b0;`
246			`send_fct_tx<= 1'b0;`
247	5	redbear	`end`
248			`ready:`
249			`begin`
250	33	redbear	`rx_resetn <= 1'b1;`
251			`enable_tx<= 1'b1;`
252			`send_null_tx<= 1'b0;`
253			`send_fct_tx<= 1'b0;`
254	5	redbear	`end`
255			`started:`
256			`begin`
257	33	redbear	`rx_resetn <= 1'b1;`
258			`enable_tx<= 1'b1;`
259			`send_null_tx<= 1'b1;`
260			`send_fct_tx<= 1'b0;`
261	5	redbear	`end`
262			`connecting:`
263			`begin`
264	33	redbear	`rx_resetn <= 1'b1;`
265			`enable_tx<= 1'b1;`
266			`send_null_tx<= 1'b1;`
267			`send_fct_tx<= 1'b1;`
268	5	redbear	`end`
269			`run:`
270			`begin`
271	33	redbear	`rx_resetn <= 1'b1;`
272			`enable_tx<= 1'b1;`
273			`send_null_tx<= 1'b1;`
274			`send_fct_tx<= 1'b1;`
275	5	redbear	`end`
276			`endcase`
277	25	redbear
278	5	redbear	`end`
279			`end`
280
281			`always@(posedge pclk)`
282			`begin`
283
284	33	redbear	`if(!resetn \|\| state_fsm == error_reset)`
285	5	redbear	`begin`
286			`after128us <= 12'd0;`
287			`end`
288			`else`
289			`begin`
290	25	redbear
291			`if(next_state_fsm == connecting && state_fsm == started)`
292	5	redbear	`begin`
293	25	redbear	`after128us <= 12'd0;`
294			`end`
295			`else if(state_fsm == error_wait \|\| state_fsm == started \|\| state_fsm == connecting)`
296			`begin`
297	5	redbear	`if(after128us < 12'd1279)`
298			`after128us <= after128us + 12'd1;`
299			`else`
300			`after128us <= 12'd0;`
301			`end`
302			`else`
303			`begin`
304			`after128us <= 12'd0;`
305			`end`
306			`end`
307
308			`end`
309
310			`always@(posedge pclk)`
311			`begin`
312
313			`if(!resetn)`
314			`begin`
315			`after64us <= 12'd0;`
316			`end`
317			`else`
318			`begin`
319			`if(state_fsm == error_reset && (auto_start \| link_start))`
320			`begin`
321			`if(after64us < 12'd639)`
322			`after64us <= after64us + 12'd1;`
323			`else`
324			`after64us <= 12'd0;`
325			`end`
326			`else`
327			`begin`
328			`after64us <= 12'd0;`
329			`end`
330			`end`
331
332			`end`
333
334			`always@(posedge pclk)`
335			`begin`
336	18	redbear	`if(!resetn)`
337	5	redbear	`begin`
338	33	redbear	`got_bit_internal <= 1'b0;`
339			`end`
340			`else`
341			`begin`
342			`if(rx_got_bit)`
343			`got_bit_internal <= 1'b1;`
344			`else`
345			`got_bit_internal <= 1'b0;`
346			`end`
347			`end`
348
349			`always@(posedge pclk)`
350			`begin`
351
352			`if(!resetn \| got_bit_internal)`
353			`begin`
354	5	redbear	`after850ns <= 12'd0;`
355			`end`
356			`else`
357			`begin`
358	25	redbear	`if(state_fsm != run)`
359	18	redbear	`begin`
360			`after850ns <= 12'd0;`
361			`end`
362	5	redbear	`else`
363	18	redbear	`begin`
364	33	redbear	`if(after850ns < 12'd85 && state_fsm == run)`
365			`after850ns <= after850ns + 12'd1;`
366			`else`
367	37	redbear	`after850ns <= after850ns;`
368	33	redbear
369	18	redbear	`end`
370	5	redbear	`end`
371
372			`end`
373
374			`endmodule`

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