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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module RX_SPW (
                        input  rx_din,
                        input  rx_sin,
 
                        input  rx_resetn,
 
                        output rx_error,
 
                        output rx_got_bit,
                        output rx_got_null,
                        output rx_got_nchar,
                        output rx_got_time_code,
                        output reg rx_got_fct,
 
                        output reg [8:0] rx_data_flag,
                        output reg rx_buffer_write,
 
                        output reg [7:0] rx_time_out,
                        output reg rx_tick_out
                 );
 
 
        reg  [4:0] counter_neg;
 
        wire posedge_clk;
        wire negedge_clk;
 
        reg bit_c_0;//N
        reg bit_c_1;//P
        reg bit_c_2;//N
        reg bit_c_3;//P
 
        reg bit_d_0;//N
        reg bit_d_1;//P
        reg bit_d_2;//N
        reg bit_d_3;//P
        reg bit_d_4;//N
        reg bit_d_5;//P
        reg bit_d_6;//N
        reg bit_d_7;//P
        reg bit_d_8;//N
        reg bit_d_9;//P
 
        reg is_control;
        reg is_data;
 
        reg last_is_control;
        reg last_is_data;
        reg last_is_timec;
 
        reg last_was_control;
        reg last_was_data;
        reg last_was_timec;
 
        reg [3:0] control;
        reg [3:0] control_r;
        reg [9:0] data;
        reg [9:0] timecode;
 
        reg [3:0] control_l_r;
        reg [9:0] data_l_r;
 
        reg [9:0] dta_timec;
 
        reg parity_error;
        wire check_c_d;
 
        reg rx_data_take;
 
        reg first_time;
 
        //CLOCK RECOVERY
        assign posedge_clk      = (rx_din ^ rx_sin)?1'b1:1'b0;
        assign negedge_clk      = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
 
        assign check_c_d        = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
 
        assign rx_got_null      = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
        //assign rx_got_fct       = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
 
        assign rx_got_bit       = (posedge_clk)?1'b1:1'b0;
 
        assign rx_error         =  parity_error;
 
        assign rx_got_nchar     = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
        assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_1 <= 1'b0;
                bit_c_3 <= 1'b0;
 
                bit_d_1 <= 1'b0;
                bit_d_3 <= 1'b0;
                bit_d_5 <= 1'b0;
                bit_d_7 <= 1'b0;
                bit_d_9 <= 1'b0;
 
                first_time <= 1'b0;
        end
        else
        begin
                bit_c_1 <= rx_din;
                bit_c_3 <= bit_c_1;
 
                bit_d_1 <= rx_din;
                bit_d_3 <= bit_d_1;
                bit_d_5 <= bit_d_3;
                bit_d_7 <= bit_d_5;
                bit_d_9 <= bit_d_7;
                first_time <= 1'b1;
        end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                bit_c_0 <= 1'b0;
                bit_c_2 <= 1'b0;
 
                bit_d_0 <= 1'b0;
                bit_d_2 <= 1'b0;
                bit_d_4 <= 1'b0;
                bit_d_6 <= 1'b0;
                bit_d_8 <= 1'b0;
        end
        else
        begin
                bit_c_0 <= rx_din;
                bit_c_2 <= bit_c_0;
 
                bit_d_0 <= rx_din;
                bit_d_2 <= bit_d_0;
                bit_d_4 <= bit_d_2;
                bit_d_6 <= bit_d_4;
                bit_d_8 <= bit_d_6;
 
        end
end
 
always@(*)
begin
        rx_got_fct = 1'b0;
 
        if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && check_c_d)
        begin
                rx_got_fct = 1'b1;
        end
end
 
always@(*)
begin
        dta_timec  = 10'd0;
        control_r  = 4'd0;
 
        if(counter_neg == 5'd2)
        begin
                control_r     = {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
        end
        else if(counter_neg == 5'd5)
        begin
                dta_timec   = {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
        end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
        if(!rx_resetn)
        begin
                is_control <= 1'b0;
                is_data    <= 1'b0;
 
                counter_neg <= 5'd0;
        end
        else
        begin
 
                if(counter_neg == 5'd1)
                begin
                        if(bit_c_0)
                        begin
                                is_control <= 1'b1;
                                is_data    <= 1'b0;
                        end
                        else
                        begin
                                is_control <= 1'b0;
                                is_data    <= 1'b1;
                        end
 
                        counter_neg <= counter_neg + 5'd1;
 
                end
                else
                begin
                        if(is_control)
                        begin
                                if(counter_neg == 5'd2)
                                begin
                                        counter_neg <= 5'd1;
                                        is_control  <= 1'b0;
                                end
                                else
                                        counter_neg <= counter_neg + 5'd1;
                        end
                        else if(is_data)
                        begin
                                if(counter_neg == 5'd5)
                                begin
                                        counter_neg <= 5'd1;
                                        is_data     <= 1'b0;
                                end
                                else
                                        counter_neg <= counter_neg + 5'd1;
                        end
                        else
                        begin
                                counter_neg <= counter_neg + 5'd1;
                        end
                end
        end
end
 
 
always@(*)
begin
 
        parity_error = 1'b0;
 
        if(last_is_control)
        begin
                if(last_was_control)
                begin
                        if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_timec)
                begin
                        if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_data)
                begin
                        if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
                        begin
                                parity_error = 1'b1;
                        end
                end
        end
        else if(last_is_data)
        begin
                if(last_was_control)
                begin
                        if(!(data[8]^control[1]^control[0]) != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_timec)
                begin
                        if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7])  != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
                else if(last_was_data)
                begin
                        if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
                        begin
                                parity_error = 1'b1;
                        end
                end
        end
 
end
 
always@(posedge check_c_d or negedge rx_resetn )
begin
 
        if(!rx_resetn)
        begin
 
                control_l_r <= 4'd0;
                control    <= 4'd0;
                data            <= 10'd0;
                data_l_r        <= 10'd0;
                rx_data_flag    <= 9'd0;
                rx_buffer_write <= 1'b0;
                rx_data_take    <= 1'b0;
 
                timecode    <= 10'd0;
                rx_time_out <= 8'd0;
                rx_tick_out <= 1'b0;
 
                last_is_control <=1'b0;
                last_is_data    <=1'b0;
                last_is_timec   <=1'b0;
 
                last_was_control <=1'b0;
                last_was_data    <=1'b0;
                last_was_timec   <=1'b0;
 
        end
        else
        begin
 
                rx_buffer_write <= rx_data_take;
                rx_data_flag <= data[8:0];
 
                rx_time_out <= timecode[7:0];
 
                if((control_r[2:0] != 3'd7 & is_data) == 1'b1)
                begin
 
                        data                    <= dta_timec;
                        data_l_r                <= data;
 
                        rx_data_take <= 1'b1;
                        rx_tick_out  <= 1'b0;
 
                        last_is_control         <=1'b0;
                        last_is_data            <=1'b1;
                        last_is_timec           <=1'b0;
                        last_was_control        <= last_is_control;
                        last_was_data           <= last_is_data ;
                        last_was_timec          <= last_is_timec;
                end
                else if((control_r[2:0] == 3'd7 && is_data) == 1'b1)
                begin
 
                        timecode                 <= dta_timec;
                        rx_tick_out  <= 1'b1;
                        rx_data_take <= 1'b0;
 
                        last_is_control         <= 1'b0;
                        last_is_data            <= 1'b0;
                        last_is_timec           <= 1'b1;
                        last_was_control        <= last_is_control;
                        last_was_data           <= last_is_data ;
                        last_was_timec          <= last_is_timec;
                end
                else if(control_r == 4'd6 || control_r == 4'd13 || control_r == 4'd5 || control_r == 4'd15 || control_r == 4'd7 || control_r == 4'd4 || control_r == 4'd12)
                begin
 
                        control          <= control_r;
                        control_l_r      <= control[3:0];
 
                        if((control_r[2:0] == 3'd6 & is_control) == 1'b1 )
                        begin
                                data <= 10'b0100000001;
                                rx_data_take <= 1'b1;
                        end
                        else if(  (control_r[2:0] == 3'd5 & is_control) == 1'b1 )
                        begin
                                data <= 10'b0100000000;
                                rx_data_take <= 1'b1;
                        end
                        else
                        begin
                                rx_data_take    <= 1'b0;
                        end
 
                        rx_tick_out  <= 1'b0;
 
                        last_is_control          <= 1'b1;
                        last_is_data             <= 1'b0;
                        last_is_timec            <= 1'b0;
                        last_was_control         <= last_is_control;
                        last_was_data            <= last_is_data ;
                        last_was_timec           <= last_is_timec;
                end
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module RX_SPW (`
37			`input rx_din,`
38			`input rx_sin,`
39
40			`input rx_resetn,`
41
42			`output rx_error,`
43
44			`output rx_got_bit,`
45			`output rx_got_null,`
46			`output rx_got_nchar,`
47			`output rx_got_time_code,`
48	23	redbear	`output reg rx_got_fct,`
49	5	redbear
50	19	redbear	`output reg [8:0] rx_data_flag,`
51			`output reg rx_buffer_write,`
52	5	redbear
53	19	redbear	`output reg [7:0] rx_time_out,`
54			`output reg rx_tick_out`
55	5	redbear	`);`
56
57
58			`reg [4:0] counter_neg;`
59
60			`wire posedge_clk;`
61			`wire negedge_clk;`
62
63	14	redbear	`reg bit_c_0;//N`
64			`reg bit_c_1;//P`
65			`reg bit_c_2;//N`
66			`reg bit_c_3;//P`
67	5	redbear
68	14	redbear	`reg bit_d_0;//N`
69			`reg bit_d_1;//P`
70			`reg bit_d_2;//N`
71			`reg bit_d_3;//P`
72			`reg bit_d_4;//N`
73			`reg bit_d_5;//P`
74			`reg bit_d_6;//N`
75			`reg bit_d_7;//P`
76			`reg bit_d_8;//N`
77			`reg bit_d_9;//P`
78	5	redbear
79	14	redbear	`reg is_control;`
80			`reg is_data;`
81	5	redbear
82	14	redbear	`reg last_is_control;`
83			`reg last_is_data;`
84			`reg last_is_timec;`
85	5	redbear
86			`reg last_was_control;`
87			`reg last_was_data;`
88	14	redbear	`reg last_was_timec;`
89	5	redbear
90	14	redbear	`reg [3:0] control;`
91	23	redbear	`reg [3:0] control_r;`
92	14	redbear	`reg [9:0] data;`
93			`reg [9:0] timecode;`
94	5	redbear
95	14	redbear	`reg [3:0] control_l_r;`
96			`reg [9:0] data_l_r;`
97	5	redbear
98	23	redbear	`reg [9:0] dta_timec;`
99
100	14	redbear	`reg parity_error;`
101			`wire check_c_d;`
102	5	redbear
103	19	redbear	`reg rx_data_take;`
104
105	23	redbear	`reg first_time;`
106
107	14	redbear	`//CLOCK RECOVERY`
108			`assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;`
109	23	redbear	`assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;`
110	5	redbear
111	14	redbear	`assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 \| (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 \| (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;`
112	5	redbear
113	14	redbear	`assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;`
114	23	redbear	`//assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;`
115	5	redbear
116			`assign rx_got_bit = (posedge_clk)?1'b1:1'b0;`
117
118	14	redbear	`assign rx_error = parity_error;`
119	5	redbear
120	14	redbear	`assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;`
121			`assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;`
122	5	redbear
123	14	redbear	`always@(posedge posedge_clk or negedge rx_resetn)`
124	5	redbear	`begin`
125	14	redbear
126			`if(!rx_resetn)`
127	5	redbear	`begin`
128	14	redbear	`bit_c_1 <= 1'b0;`
129			`bit_c_3 <= 1'b0;`
130
131			`bit_d_1 <= 1'b0;`
132			`bit_d_3 <= 1'b0;`
133			`bit_d_5 <= 1'b0;`
134			`bit_d_7 <= 1'b0;`
135			`bit_d_9 <= 1'b0;`
136	23	redbear
137			`first_time <= 1'b0;`
138	5	redbear	`end`
139			`else`
140			`begin`
141	14	redbear	`bit_c_1 <= rx_din;`
142			`bit_c_3 <= bit_c_1;`
143
144			`bit_d_1 <= rx_din;`
145			`bit_d_3 <= bit_d_1;`
146			`bit_d_5 <= bit_d_3;`
147			`bit_d_7 <= bit_d_5;`
148			`bit_d_9 <= bit_d_7;`
149	23	redbear	`first_time <= 1'b1;`
150	5	redbear	`end`
151	14	redbear
152	5	redbear	`end`
153
154	14	redbear	`always@(posedge negedge_clk or negedge rx_resetn)`
155	5	redbear	`begin`
156	14	redbear
157			`if(!rx_resetn)`
158	5	redbear	`begin`
159	14	redbear	`bit_c_0 <= 1'b0;`
160			`bit_c_2 <= 1'b0;`
161
162			`bit_d_0 <= 1'b0;`
163			`bit_d_2 <= 1'b0;`
164			`bit_d_4 <= 1'b0;`
165			`bit_d_6 <= 1'b0;`
166			`bit_d_8 <= 1'b0;`
167	5	redbear	`end`
168			`else`
169			`begin`
170	14	redbear	`bit_c_0 <= rx_din;`
171			`bit_c_2 <= bit_c_0;`
172
173			`bit_d_0 <= rx_din;`
174			`bit_d_2 <= bit_d_0;`
175			`bit_d_4 <= bit_d_2;`
176			`bit_d_6 <= bit_d_4;`
177			`bit_d_8 <= bit_d_6;`
178	23	redbear
179			`end`
180			`end`
181	14	redbear
182	23	redbear	`always@(*)`
183			`begin`
184			`rx_got_fct = 1'b0;`
185
186			`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && check_c_d)`
187			`begin`
188			`rx_got_fct = 1'b1;`
189			`end`
190			`end`
191
192			`always@(*)`
193			`begin`
194			`dta_timec = 10'd0;`
195			`control_r = 4'd0;`
196
197			`if(counter_neg == 5'd2)`
198			`begin`
199			`control_r = {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
200			`end`
201			`else if(counter_neg == 5'd5)`
202			`begin`
203			`dta_timec = {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
204			`end`
205			`end`
206
207			`always@(posedge negedge_clk or negedge rx_resetn)`
208			`begin`
209
210			`if(!rx_resetn)`
211			`begin`
212			`is_control <= 1'b0;`
213			`is_data <= 1'b0;`
214
215			`counter_neg <= 5'd0;`
216			`end`
217			`else`
218			`begin`
219
220	14	redbear	`if(counter_neg == 5'd1)`
221	5	redbear	`begin`
222	14	redbear	`if(bit_c_0)`
223			`begin`
224			`is_control <= 1'b1;`
225			`is_data <= 1'b0;`
226			`end`
227			`else`
228			`begin`
229			`is_control <= 1'b0;`
230			`is_data <= 1'b1;`
231			`end`
232
233			`counter_neg <= counter_neg + 5'd1;`
234
235	5	redbear	`end`
236			`else`
237			`begin`
238	14	redbear	`if(is_control)`
239			`begin`
240			`if(counter_neg == 5'd2)`
241			`begin`
242			`counter_neg <= 5'd1;`
243			`is_control <= 1'b0;`
244			`end`
245			`else`
246			`counter_neg <= counter_neg + 5'd1;`
247			`end`
248			`else if(is_data)`
249			`begin`
250			`if(counter_neg == 5'd5)`
251			`begin`
252			`counter_neg <= 5'd1;`
253			`is_data <= 1'b0;`
254			`end`
255			`else`
256			`counter_neg <= counter_neg + 5'd1;`
257			`end`
258			`else`
259			`begin`
260			`counter_neg <= counter_neg + 5'd1;`
261			`end`
262			`end`
263	5	redbear	`end`
264			`end`
265
266	23	redbear
267	5	redbear	`always@(*)`
268			`begin`
269
270			`parity_error = 1'b0;`
271
272	14	redbear	`if(last_is_control)`
273	5	redbear	`begin`
274	14	redbear	`if(last_was_control)`
275	5	redbear	`begin`
276	14	redbear	`if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])`
277			`begin`
278			`parity_error = 1'b1;`
279			`end`
280	5	redbear	`end`
281	14	redbear	`else if(last_was_timec)`
282	5	redbear	`begin`
283	14	redbear	`if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])`
284			`begin`
285			`parity_error = 1'b1;`
286			`end`
287	5	redbear	`end`
288	14	redbear	`else if(last_was_data)`
289	5	redbear	`begin`
290	14	redbear	`if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])`
291			`begin`
292			`parity_error = 1'b1;`
293			`end`
294	5	redbear	`end`
295			`end`
296	14	redbear	`else if(last_is_data)`
297	5	redbear	`begin`
298	14	redbear	`if(last_was_control)`
299	5	redbear	`begin`
300	14	redbear	`if(!(data[8]^control[1]^control[0]) != data[9])`
301			`begin`
302			`parity_error = 1'b1;`
303			`end`
304	5	redbear	`end`
305	14	redbear	`else if(last_was_timec)`
306	5	redbear	`begin`
307	14	redbear	`if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])`
308			`begin`
309			`parity_error = 1'b1;`
310			`end`
311	5	redbear	`end`
312	14	redbear	`else if(last_was_data)`
313	5	redbear	`begin`
314	14	redbear	`if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])`
315			`begin`
316			`parity_error = 1'b1;`
317			`end`
318	5	redbear	`end`
319			`end`
320	14	redbear
321	5	redbear	`end`
322
323	14	redbear	`always@(posedge check_c_d or negedge rx_resetn )`
324	5	redbear	`begin`
325
326	14	redbear	`if(!rx_resetn)`
327	5	redbear	`begin`
328	23	redbear
329	14	redbear	`control_l_r <= 4'd0;`
330	23	redbear	`control <= 4'd0;`
331	19	redbear	`data <= 10'd0;`
332			`data_l_r <= 10'd0;`
333			`rx_data_flag <= 9'd0;`
334			`rx_buffer_write <= 1'b0;`
335			`rx_data_take <= 1'b0;`
336	5	redbear
337	14	redbear	`timecode <= 10'd0;`
338	19	redbear	`rx_time_out <= 8'd0;`
339			`rx_tick_out <= 1'b0;`
340	5	redbear
341	14	redbear	`last_is_control <=1'b0;`
342			`last_is_data <=1'b0;`
343			`last_is_timec <=1'b0;`
344	5	redbear
345	14	redbear	`last_was_control <=1'b0;`
346			`last_was_data <=1'b0;`
347			`last_was_timec <=1'b0;`
348	5	redbear
349			`end`
350			`else`
351			`begin`
352	19	redbear
353			`rx_buffer_write <= rx_data_take;`
354			`rx_data_flag <= data[8:0];`
355
356	23	redbear	`rx_time_out <= timecode[7:0];`
357	19	redbear
358	23	redbear	`if((control_r[2:0] != 3'd7 & is_data) == 1'b1)`
359	14	redbear	`begin`
360	5	redbear
361	23	redbear	`data <= dta_timec;`
362	14	redbear	`data_l_r <= data;`
363	19	redbear
364			`rx_data_take <= 1'b1;`
365			`rx_tick_out <= 1'b0;`
366	5	redbear
367	14	redbear	`last_is_control <=1'b0;`
368			`last_is_data <=1'b1;`
369			`last_is_timec <=1'b0;`
370			`last_was_control <= last_is_control;`
371			`last_was_data <= last_is_data ;`
372			`last_was_timec <= last_is_timec;`
373			`end`
374	23	redbear	`else if((control_r[2:0] == 3'd7 && is_data) == 1'b1)`
375	14	redbear	`begin`
376
377	23	redbear	`timecode <= dta_timec;`
378	19	redbear	`rx_tick_out <= 1'b1;`
379			`rx_data_take <= 1'b0;`
380	14	redbear
381			`last_is_control <= 1'b0;`
382			`last_is_data <= 1'b0;`
383			`last_is_timec <= 1'b1;`
384			`last_was_control <= last_is_control;`
385			`last_was_data <= last_is_data ;`
386			`last_was_timec <= last_is_timec;`
387			`end`
388	23	redbear	`else if(control_r == 4'd6 \|\| control_r == 4'd13 \|\| control_r == 4'd5 \|\| control_r == 4'd15 \|\| control_r == 4'd7 \|\| control_r == 4'd4 \|\| control_r == 4'd12)`
389	14	redbear	`begin`
390
391	23	redbear	`control <= control_r;`
392	14	redbear	`control_l_r <= control[3:0];`
393	19	redbear
394	23	redbear	`if((control_r[2:0] == 3'd6 & is_control) == 1'b1 )`
395	14	redbear	`begin`
396	19	redbear	`data <= 10'b0100000001;`
397			`rx_data_take <= 1'b1;`
398	14	redbear	`end`
399	23	redbear	`else if( (control_r[2:0] == 3'd5 & is_control) == 1'b1 )`
400	19	redbear	`begin`
401			`data <= 10'b0100000000;`
402			`rx_data_take <= 1'b1;`
403			`end`
404			`else`
405			`begin`
406			`rx_data_take <= 1'b0;`
407			`end`
408
409			`rx_tick_out <= 1'b0;`
410
411	14	redbear	`last_is_control <= 1'b1;`
412			`last_is_data <= 1'b0;`
413			`last_is_timec <= 1'b0;`
414			`last_was_control <= last_is_control;`
415			`last_was_data <= last_is_data ;`
416			`last_was_timec <= last_is_timec;`
417			`end`
418	5	redbear	`end`
419			`end`
420
421			`endmodule`

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