OpenCores
URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [spw_ulight_con_top_x.v] - Blame information for rev 40

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 34 redbear 
//+FHDR------------------------------------------------------------------------
2 
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
3 
//GLADIC Open Source RTL
4 
//-----------------------------------------------------------------------------
5 
//FILE NAME      :
6 
//DEPARTMENT     : IC Design / Verification
7 
//AUTHOR         : Felipe Fernandes da Costa
8 
//AUTHOR’S EMAIL :
9 
//-----------------------------------------------------------------------------
10 
//RELEASE HISTORY
11 
//VERSION DATE AUTHOR DESCRIPTION
12 
//1.0 YYYY-MM-DD name
13 
//-----------------------------------------------------------------------------
14 
//KEYWORDS : General file searching keywords, leave blank if none.
15 
//-----------------------------------------------------------------------------
16 
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
17 
//-----------------------------------------------------------------------------
18 
//PARAMETERS
19 
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
20 
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
21 
//-----------------------------------------------------------------------------
22 
//REUSE ISSUES
23 
//Reset Strategy        :
24 
//Clock Domains         :
25 
//Critical Timing       :
26 
//Test Features         :
27 
//Asynchronous I/F      :
28 
//Scan Methodology      :
29 
//Instantiations        :
30 
//Synthesizable (y/n)   :
31 
//Other                 :
32 
//-FHDR------------------------------------------------------------------------
33 40 redbear 
 
34 
`timescale 1ns/1ns
35 
 
36 33 redbear 
module spw_ulight_con_top_x(
37 
                                input ppll_100_MHZ,
38 
                                input ppllclk,
39 
                                input reset_spw_n_b,
40 40 redbear 
 
41 33 redbear 
                                input top_sin,
42 
                                input top_din,
43 
 
44 
                                input top_auto_start,
45 
                                input top_link_start,
46 
                                input top_link_disable,
47 
 
48 
                                input top_tx_write,
49 
                                input [8:0] top_tx_data,
50 
 
51 
                                input top_tx_tick,
52 
                                input [7:0] top_tx_time,
53 
 
54 
                                input read_rx_fifo_en,
55 
 
56 
                                output [8:0] datarx_flag,
57 
 
58 
                                output tick_out,
59 
                                output [7:0] time_out,
60 
 
61 
                                output top_dout,
62 
                                output top_sout,
63 
 
64 
                                output f_full,
65 
                                output f_empty,
66 
                                output f_full_rx,
67 
                                output f_empty_rx,
68 
                                output top_tx_ready_tick,
69 
 
70 
                                output [5:0]top_fsm,
71 
 
72 
                                output [5:0]counter_fifo_tx,
73 
                                output [5:0]counter_fifo_rx
74 
                                //output [13:0] data_info
75 
                        );
76 
 
77 
 
78 
 
79 
        wire [8:0] datarx_flag_axi;
80 
        wire [8:0] datarx_flag_w;
81 
        wire buffer_write_w;
82 
 
83 40 redbear 
        //wire [7:0] time_out_axi;
84 33 redbear 
 
85 40 redbear 
        //wire [13:0] monitor_x_axi;
86 
        //wire [13:0] data_x;
87 
        //wire rx_buffer_write_mon_x;
88 33 redbear 
 
89 
        wire credit_error_rx_w,top_send_fct_now_w;
90 
 
91 
        wire top_tx_write_w,top_tx_ready_w;
92 
        wire [8:0] top_tx_data_w;
93 
        wire tx_reset_n;
94 
 
95 40 redbear 
        assign tx_reset_n = (!reset_spw_n_b | top_fsm != 6'd16)?1'b0:1'b1;
96 33 redbear 
 
97 
        //assign time_out = time_out_w;
98 
        assign datarx_flag = datarx_flag_axi;
99 
        //assign data_info = data_x;
100 
 
101 
        top_spw_ultra_light SPW(
102 
 
103 
                                        .pclk(ppll_100_MHZ),
104 
                                        .ppllclk(ppllclk),
105 
                                        .resetn(reset_spw_n_b),
106 
 
107 
                                        .top_sin(top_sin),
108 
                                        .top_din(top_din),
109 
 
110 
                                        .top_auto_start(top_auto_start),
111 
                                        .top_link_start(top_link_start),
112 
                                        .top_link_disable(top_link_disable),
113 
 
114 
                                        .top_tx_write(top_tx_write_w),
115 
                                        .top_tx_data(top_tx_data_w),
116 
 
117 
                                        .top_tx_tick(top_tx_tick),
118 
                                        .top_tx_time(top_tx_time),
119 
 
120 
                                        .credit_error_rx(credit_error_rx_w),
121 
                                        .top_send_fct_now(top_send_fct_now_w),
122 
 
123 
                                        .datarx_flag(datarx_flag_w),
124 
                                        .buffer_write(buffer_write_w),
125 
 
126 
                                        .time_out(time_out),
127 
                                        .tick_out(tick_out),
128 
 
129 
                                        .top_dout(top_dout),
130 
                                        .top_sout(top_sout),
131 
 
132 
                                        .top_tx_ready(top_tx_ready_w),
133 
                                        .top_tx_ready_tick(top_tx_ready_tick),
134 
 
135 
                                        .top_fsm(top_fsm)
136 
                                );
137 
 
138 
 
139 
                        fifo_rx  rx_data(
140 
                                         .clock(ppll_100_MHZ),
141 
                                         .reset(tx_reset_n),
142 
                                         .wr_en(buffer_write_w),
143 
                                         .rd_en(read_rx_fifo_en),
144 
                                         .data_in(datarx_flag_w),
145 
                                         .f_full(f_full_rx),
146 
                                         .f_empty(f_empty_rx),
147 
                                         .open_slot_fct(top_send_fct_now_w),
148 
                                         .overflow_credit_error(credit_error_rx_w),
149 
                                         .data_out(datarx_flag_axi),
150 
                                         .counter(counter_fifo_rx)
151 
                                         );
152 
 
153 
 
154 
                        fifo_tx tx_data(
155 
                                         .clock(ppll_100_MHZ),
156 
                                         .reset(tx_reset_n),
157 
                                         .wr_en(top_tx_write),
158 
                                         .rd_en(top_tx_ready_w),
159 
                                         .data_in(top_tx_data),
160 
                                         .f_full(f_full),
161 
                                         .f_empty(f_empty),
162 
                                         .write_tx(top_tx_write_w),
163 
                                         .data_out(top_tx_data_w),
164 
                                         .counter(counter_fifo_tx)
165 
                                         );
166 
 
167 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.