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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [tx_spw.v] - Blame information for rev 40

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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME      :
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//DEPARTMENT     : IC Design / Verification
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//AUTHOR         : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy        :
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//Clock Domains         :
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//Critical Timing       :
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//Test Features         :
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//Asynchronous I/F      :
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//Scan Methodology      :
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//Instantiations        :
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//Synthesizable (y/n)   :
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//Other                 :
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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module TX_SPW (
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                input pclk_tx,
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                //
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                input [8:0] data_tx_i,
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                input txwrite_tx,
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                //
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                input [7:0] timecode_tx_i,
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                input tickin_tx,
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                //
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                input enable_tx,
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                input send_null_tx,
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                input send_fct_tx,
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                //
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                input gotfct_tx,
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                input send_fct_now,
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                //
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                //
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                output ready_tx_data,
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                output ready_tx_timecode,
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                output tx_dout_e,
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                output tx_sout_e
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                );
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        wire [13:0] timecode_s;
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        wire [5:0]  last_type;
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        wire txdata_flagctrl_tx_last;
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        wire [8:0]  tx_data_in;
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        wire [8:0]  tx_data_in_0;
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        wire process_data;
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        wire process_data_0;
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        wire last_timein_control_flag_tx;
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        wire [7:0]  tx_tcode_in;
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        wire tcode_rdy_trnsp;
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        wire fct_counter_p;
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        wire [2:0] fct_flag_p;
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        wire get_data;
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        wire get_data_0;
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        wire char_sent;
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        wire fct_sent;
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        wire tx_dout;
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        wire tx_sout;
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tx_fsm_m  tx_fsm(
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                .pclk_tx(pclk_tx),
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                .enable_tx(enable_tx),
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                .send_null_tx(send_null_tx),
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                .send_fct_tx(send_fct_tx),
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                .get_data(get_data),
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                .get_data_0(get_data_0),
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                .tx_data_in(tx_data_in),
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                .tx_data_in_0(tx_data_in_0),
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                .process_data(process_data),
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                .process_data_0(process_data_0),
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                .tx_tcode_in(tx_tcode_in),
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                .tcode_rdy_trnsp(tcode_rdy_trnsp),
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                .ready_tx_data(ready_tx_data),
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                .ready_tx_timecode(ready_tx_timecode),
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                .fct_great_than_zero(fct_counter_p),
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                .gotfct_tx(gotfct_tx),
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                .send_fct_now(send_fct_now),
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                .tx_dout_e(tx_dout_e),
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                .tx_sout_e(tx_sout_e)
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        );
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tx_data_send tx_data_snd(
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                        .pclk_tx(pclk_tx),
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                        .send_null_tx(send_null_tx),
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                        .enable_tx(enable_tx),
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                        .get_data(get_data),
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                        .get_data_0(get_data_0),
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                        .timecode_tx_i(timecode_tx_i),
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                        .tickin_tx(tickin_tx),
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                        .data_tx_i(data_tx_i),
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                        .txwrite_tx(txwrite_tx),
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                        .fct_counter_p(fct_counter_p),
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                        .tx_data_in(tx_data_in),
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                        .tx_data_in_0(tx_data_in_0),
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                        .process_data(process_data),
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                        .process_data_0(process_data_0),
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                        .tx_tcode_in(tx_tcode_in),
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                        .tcode_rdy_trnsp(tcode_rdy_trnsp)
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);
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endmodule

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