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1 29 redbear 
//+FHDR------------------------------------------------------------------------
2 
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
3 
//GLADIC Open Source RTL
4 
//-----------------------------------------------------------------------------
5 
//FILE NAME      :
6 
//DEPARTMENT     : IC Design / Verification
7 
//AUTHOR         : Felipe Fernandes da Costa
8 
//AUTHOR’S EMAIL :
9 
//-----------------------------------------------------------------------------
10 
//RELEASE HISTORY
11 
//VERSION DATE AUTHOR DESCRIPTION
12 
//1.0 YYYY-MM-DD name
13 
//-----------------------------------------------------------------------------
14 
//KEYWORDS : General file searching keywords, leave blank if none.
15 
//-----------------------------------------------------------------------------
16 
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
17 
//-----------------------------------------------------------------------------
18 
//PARAMETERS
19 
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
20 
//e.g.DATA_WIDTH        [32,16] : width of the DATA : 32:
21 
//-----------------------------------------------------------------------------
22 
//REUSE ISSUES
23 
//Reset Strategy        :
24 
//Clock Domains         :
25 
//Critical Timing       :
26 
//Test Features         :
27 
//Asynchronous I/F      :
28 
//Scan Methodology      :
29 
//Instantiations        :
30 
//Synthesizable (y/n)   :
31 
//Other                 :
32 
//-FHDR------------------------------------------------------------------------
33 
#include <systemc.h>
34 
#include <stdio.h>
35 
#include <vector>
36 
#include <string>
37 
#include <stdlib.h>
38 
#include <gtkmm.h>
39 
#include <random>
40 
#include <boost/thread.hpp>
41 
 
42 
using namespace std;
43 
using namespace Gtk;
44 
using namespace boost;
45 
 
46 
#include "../gladicapi/data_recorder.h"
47 
#include "../gladicapi/data_check.h"
48 
 
49 
bool enable_null;
50 
bool enable_fct;
51 
bool enable_time_code;
52 
bool enable_n_char;
53 
 
54 
bool EEP_EOP;
55 
 
56 
unsigned int finish = 0;
57 
bool link_start = false;
58 
bool link_disable = false;
59 
bool auto_start = false;
60 
 
61 
//systemc and verilog
62 
bool global_reset = false;
63 
 
64 
//verilog variables
65 
bool verilog_link_start = false;
66 
bool verilog_link_disable = false;
67 
bool verilog_auto_start = false;
68 
int frquency_nano_second = 500;
69 
 
70 
vector<string> data_col_store;
71 
data_recorder *REC_TX_SPW;
72 
data_check    *COMPARE_SPW;
73 
 
74 
vector<string> data_col_store0;
75 
data_recorder *REC_TX_SPWSC;
76 
data_check    *COMPARE_SPW_RX;
77 
 
78 
unsigned long int a = 0;
79 
int clock_systemc   = 2;
80 
 
81 
//send data systemC
82 
 
83 
bool start_send_data_verilog  = false;
84 
bool enable_time_code_verilog = false;
85 
 
86 
bool start_send_data = false;
87 
bool start_tick_data = false;
88 
 
89 
vector<sc_uint<9> > data_generated_sc;
90 
sc_uint<9> intermediate_systemc;
91 
sc_uint<9> intermediate_sc;
92 
unsigned int data_iteration_sc_aux = 0;
93 
unsigned int data_iteration_sc = 0;
94 
 
95 
vector<sc_uint<9> > data_generated_verilog;
96 
sc_uint<9> intermediate;
97 
sc_uint<9> intermediate_verilog;
98 
 
99 
unsigned int data_iteration = 0;
100 
unsigned int data_iteration_vlog = 0;
101 
sc_uint<9> intermediate_data;
102 
 
103 
#include "top_spw.h"
104 
 
105 
//Data generation
106 
unsigned long int max_data = 100;
107 
 
108 
std::random_device rd;
109 
std::uniform_int_distribution<unsigned long int> data_in(0,255);
110 
std::uniform_int_distribution<unsigned long int> nchar(1,max_data-1);//eop-eep
111 
 
112 
class sc_TOP_SPW;
113 
 
114 
SC_MODULE(sc_TOP_SPW)
115 
{
116 
 
117 
        sc_clock CLOCK;
118 
        sc_signal<bool>  RESET;
119 
        sc_signal<bool> LINK_START;
120 
        sc_signal<bool> LINK_DISABLE;
121 
        sc_signal<bool> AUTO_START;
122 
        sc_signal<sc_uint<4> > FSM_SPW_OUT;
123 
        sc_signal<sc_uint<4> > FSM_TX;
124 
 
125 
        sc_signal<sc_uint<10> > CLOCK_GEN;
126 
        sc_signal<bool> E_SEND_DATA;
127 
        //sc_signal<bool> TICKIN_TX;
128 
        //sc_signal<sc_uint<8> > TIMEIN_CONTROL_FLAG_TX;
129 
 
130 
        //sc_signal<bool> TXWRITE_TX;
131 
        //sc_signal<sc_uint<9> > TXDATA_FLAGCTRL_TX;
132 
 
133 
        //sc_signal<bool> READY_TX;
134 
        //sc_signal<bool> READY_TICK;
135 
 
136 
        sc_signal<bool> BUFFER_READY;
137 
        sc_signal<sc_uint<9> > DATARX_FLAG;
138 
        sc_signal<bool> BUFFER_WRITE;
139 
 
140 
        sc_signal<sc_uint<8> > TIME_OUT;
141 
        sc_signal<bool> TICK_OUT;
142 
        sc_signal<bool> CONTROL_FLAG_OUT;
143 
 
144 
        sc_signal<uint> DOUT;
145 
        sc_signal<uint> SOUT;
146 
        sc_signal<uint>  DIN;
147 
        sc_signal<uint>  SIN;
148 
 
149 
        sc_TOP DUT;
150 
 
151 
        SC_CTOR(sc_TOP_SPW) :CLOCK("CLOCK",20,SC_NS),
152 
                           RESET("RESET"),
153 
                           LINK_DISABLE("LINK_DISABLE"),
154 
                           LINK_START("LINK_START"),
155 
                           AUTO_START("AUTO_START"),
156 
                           FSM_SPW_OUT("FSM_SPW_OUT"),
157 
                           CLOCK_GEN("CLOCK_GEN"),
158 
                           E_SEND_DATA("E_SEND_DATA"),
159 
                           //TICKIN_TX("TICKIN_TX"),
160 
                           //TIMEIN_CONTROL_FLAG_TX("TIMEIN_CONTROL_FLAG_TX"),
161 
                           //TXWRITE_TX("TXWRITE_TX"),
162 
                           //TXDATA_FLAGCTRL_TX("TXDATA_FLAGCTRL_TX"),
163 
 
164 
                           //READY_TX("READY_TX"),
165 
                          //READY_TICK("READY_TICK"),
166 
                           DOUT("DOUT"),
167 
                           SOUT("SOUT"),
168 
 
169 
                           FSM_TX("FSM_TX"),
170 
                           DIN("DIN"),
171 
                           SIN("SIN"),
172 
                           BUFFER_READY("BUFFER_READY"),
173 
                           DATARX_FLAG("DATARX_FLAG"),
174 
                           BUFFER_WRITE("BUFFER_WRITE"),
175 
                           TIME_OUT("TIME_OUT"),
176 
                           TICK_OUT("TICK_OUT"),
177 
                           CONTROL_FLAG_OUT("CONTROL_FLAG_OUT"),
178 
 
179 
 
180 
        DUT("DUT") {
181 
        DUT.CLOCK(CLOCK);
182 
        DUT.RESET(RESET);
183 
        DUT.LINK_DISABLE(LINK_DISABLE);
184 
        DUT.AUTO_START(AUTO_START);
185 
        DUT.LINK_START(LINK_START);
186 
        DUT.FSM_SPW_OUT(FSM_SPW_OUT);
187 
        DUT.CLOCK_GEN(CLOCK_GEN);
188 
        DUT.E_SEND_DATA(E_SEND_DATA);
189 
        //DUT.TICKIN_TX(TICKIN_TX);
190 
        //DUT.TIMEIN_CONTROL_FLAG_TX(TIMEIN_CONTROL_FLAG_TX);
191 
        //DUT.TXWRITE_TX(TXWRITE_TX);
192 
        //DUT.TXDATA_FLAGCTRL_TX(TXDATA_FLAGCTRL_TX);
193 
        DUT.FSM_TX(FSM_TX);
194 
        //DUT.READY_TX(READY_TX);
195 
        //DUT.READY_TICK(READY_TICK);
196 
        DUT.DOUT(DOUT);
197 
        DUT.SOUT(SOUT);
198 
 
199 
        DUT.DIN(DIN);
200 
        DUT.SIN(SIN);
201 
        DUT.BUFFER_READY(BUFFER_READY);
202 
        DUT.DATARX_FLAG(DATARX_FLAG);
203 
        DUT.BUFFER_WRITE(BUFFER_WRITE);
204 
        DUT.TIME_OUT(TIME_OUT);
205 
        DUT.TICK_OUT(TICK_OUT);
206 
        DUT.CONTROL_FLAG_OUT(CONTROL_FLAG_OUT);
207 
 
208 
        cout << "SC_CTOR(sc_TOP_SPW)" << endl;
209 
        }
210 
 
211 
};
212 
 
213 
Glib::RefPtr<Gtk::Builder> builder;
214 
 
215 
Gtk::Window *window;
216 
 
217 
Gtk::Button *BtnFinsihSimulation;
218 
Gtk::Button *BtnLinkEnable;
219 
Gtk::Button *BtnLinkDisable;
220 
Gtk::Button *BtnAutoStart;
221 
Gtk::Button *BtnReset;
222 
 
223 
Gtk::Button *BtnSpaceWireVerilog;
224 
Gtk::CheckButton *CheckbtnLinkEnable;
225 
Gtk::CheckButton *CheckbtnAutoStart;
226 
Gtk::CheckButton *CheckbtnLinkDisable;
227 
 
228 
//Execute test
229 
Gtk::Button *BtnSimpleTest;
230 
Gtk::CheckButton *CheckBtnEop;
231 
Gtk::CheckButton *CheckBtnEep;
232 
Gtk::CheckButton *CheckBtnTimeCode;
233 
 
234 
//Generate data
235 
Gtk::Button *BtnGenerationDataVerilog;
236 
Gtk::CheckButton *CheckBtnEopGenVerilog;
237 
Gtk::CheckButton *CheckBtnEepGenVerilog;
238 
Gtk::CheckButton *CheckBtnTimeCodeGenVerilog;
239 
 
240 
Gtk::Button *BtnTxFrequency;
241 
Gtk::Entry  *EntryFrequency;
242 
 
243 
Gtk::Button *BtnChangeFrequencyVerilog;
244 
Gtk::Entry  *EntryFrequencyVerilog;
245 
 
246 
Gtk::Button *BtnSendDataScTx;
247 
Gtk::Button *BtnTimeCodeScTx;
248 
Gtk::Button *BtnGenerateDataSc;
249 
 
250 
Gtk::CheckButton *CheckBtnEepGenSystemC;
251 
Gtk::CheckButton *CheckBtnEopGenSystemC;
252 
 
253 
 
254 
Gtk::Label *lblStatus;
255 
 
256 
 
257 
sc_TOP_SPW *sn_top;
258 
 
259 
extern "C" Control_SC* create_object()
260 
{
261 
  return new Control_SC;
262 
}
263 
 
264 
extern "C" void destroy_object( Control_SC* object )
265 
{
266 
  delete object;
267 
}
268 
 
269 
/*GTKMM CONTROL*/
270 
void on_BtnFinsihSimulation_clicked()
271 
{
272 
        cout<< "End Simulation" <<endl;
273 
        Gtk::Main::quit();
274 
        finish = 1;
275 
        REC_TX_SPW->endsimulation();
276 
        REC_TX_SPWSC->endsimulation();
277 
}
278 
 
279 
void on_BtnLinkEnable_clicked()
280 
{
281 
        link_start = !link_start;
282 
}
283 
 
284 
void on_BtnLinkDisable_clicked()
285 
{
286 
        link_disable = !link_disable;
287 
}
288 
 
289 
void on_BtnAutoStart_clicked()
290 
{
291 
        auto_start = !auto_start;
292 
}
293 
 
294 
void on_BtnReset_clicked()
295 
{
296 
        global_reset = !global_reset;
297 
}
298 
 
299 
 
300 
void on_BtnSpaceWireVerilog_clicked()
301 
{
302 
 
303 
 
304 
        if(!CheckbtnLinkEnable->get_active())
305 
        {
306 
                verilog_link_start = false;
307 
                lblStatus->set_text("LINKENABLE VERILOG IS OFF");
308 
        }
309 
 
310 
        if(!CheckbtnAutoStart->get_active())
311 
        {
312 
                verilog_auto_start = false;
313 
                lblStatus->set_text("AUTOSTART VERILOG IS OFF");
314 
        }
315 
 
316 
        if(!CheckbtnLinkDisable->get_active())
317 
        {
318 
                verilog_link_disable = false;
319 
                lblStatus->set_text("AUTOSTART VERILOG IS OFF");
320 
        }
321 
 
322 
        if(CheckbtnLinkEnable->get_active())
323 
        {
324 
                verilog_link_start = true;
325 
                lblStatus->set_text("LINKENABLE VERILOG IS ON");
326 
        }
327 
 
328 
        if(CheckbtnAutoStart->get_active())
329 
        {
330 
                verilog_auto_start = true;
331 
                lblStatus->set_text("AUTOSTART VERILOG IS ON");
332 
        }
333 
 
334 
        if(CheckbtnLinkDisable->get_active())
335 
        {
336 
                verilog_link_disable = true;
337 
                lblStatus->set_text("LINKDISABLE VERILOG IS ON");
338 
        }
339 
 
340 
}
341 
 
342 
 
343 
void on_BtnSimpleTest_clicked()
344 
{
345 
 
346 
        if(CheckBtnEopGenVerilog->get_active())
347 
        {
348 
                start_send_data_verilog = true;
349 
        }
350 
        else
351 
        {
352 
                start_send_data_verilog = false;
353 
        }
354 
 
355 
        if(CheckBtnTimeCodeGenVerilog->get_active())
356 
        {
357 
                enable_time_code_verilog = true;
358 
        }
359 
        else
360 
        {
361 
                enable_time_code_verilog = false;
362 
        }
363 
 
364 
        /*
365 
        data_generated.clear();
366 
        data_iteration=0;
367 
        data_iteration_vlog=0;
368 
        if(CheckBtnEop->get_active())
369 
        {
370 
                for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
371 
                {
372 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
373 
                        {
374 
                                intermediate(8,8) = 1;
375 
                                intermediate(7,0) = 0;
376 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
377 
                        {
378 
                                intermediate(7,0) = data_in(rd);
379 
                                intermediate(8,8) = 0;
380 
                        }
381 
                        data_generated.push_back(intermediate);
382 
                }
383 
                start_send_data_verilog = true;
384 
        }else if(CheckBtnEep->get_active())
385 
        {
386 
                for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
387 
                {
388 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
389 
                        {
390 
                                intermediate(8,8) = 1;
391 
                                intermediate(7,0) = 1;
392 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
393 
                        {
394 
                                intermediate(7,0) = data_in(rd);
395 
                                intermediate(8,8) = 0;
396 
                        }
397 
                        data_generated.push_back(intermediate);
398 
                }
399 
                intermediate(7,0) = 1;
400 
                intermediate(8,8) = 1;
401 
                data_generated[nchar(rd)] = intermediate;
402 
                start_send_data_verilog = true;
403 
        }
404 
 
405 
        if(CheckBtnTimeCode->get_active())
406 
        {
407 
                enable_time_code_verilog = true;
408 
        }
409 
        */
410 
 
411 
 
412 
}
413 
 
414 
void on_BtnGenerationDataVerilog_clicked()
415 
{
416 
        data_generated_verilog.clear();
417 
        data_iteration=0;
418 
        data_iteration_vlog=0;
419 
        if(CheckBtnEopGenVerilog->get_active())
420 
        {
421 
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
422 
                {
423 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
424 
                        {
425 
                                intermediate_verilog(8,8) = 1;
426 
                                intermediate_verilog(7,0) = 0;
427 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
428 
                        {
429 
                                intermediate_verilog(7,0) = data_in(rd);
430 
                                intermediate_verilog(8,8) = 0;
431 
                        }
432 
                        data_generated_verilog.push_back(intermediate_verilog);
433 
                }
434 
        }else if(CheckBtnEepGenVerilog->get_active())
435 
        {
436 
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
437 
                {
438 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
439 
                        {
440 
                                intermediate_verilog(8,8) = 1;
441 
                                intermediate_verilog(7,0) = 1;
442 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
443 
                        {
444 
                                intermediate_verilog(7,0) = data_in(rd);
445 
                                intermediate_verilog(8,8) = 0;
446 
                        }
447 
                        data_generated_verilog.push_back(intermediate_verilog);
448 
                }
449 
                intermediate_verilog(7,0) = 1;
450 
                intermediate_verilog(8,8) = 1;
451 
                data_generated_verilog[nchar(rd)] = intermediate_verilog;
452 
        }
453 
}
454 
 
455 
void on_BtnTxFrequency_clicked()
456 
{
457 
 
458 
        string aux = EntryFrequency->get_text();
459 
        switch(atoi(aux.c_str()))
460 
        {
461 
                case 2:
462 
                        sn_top->CLOCK_GEN = 1;
463 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 2MHz");
464 
                break;
465 
                case 10:
466 
                        sn_top->CLOCK_GEN = 2;
467 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 10MHz");
468 
                break;
469 
                case 20:
470 
                        sn_top->CLOCK_GEN = 4;
471 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 20MHz");
472 
                break;
473 
                case 50:
474 
                        sn_top->CLOCK_GEN = 8;
475 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 50MHz");
476 
                break;
477 
                case 100:
478 
                        sn_top->CLOCK_GEN = 16;
479 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 100MHz");
480 
                break;
481 
                case 150:
482 
                        sn_top->CLOCK_GEN = 32;
483 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 150MHz");
484 
                break;
485 
                case 200:
486 
                        sn_top->CLOCK_GEN = 64;
487 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 200MHz");
488 
                break;
489 
                case 201:
490 
                        sn_top->CLOCK_GEN = 128;
491 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 201MHz");
492 
                break;
493 
                case 250:
494 
                        sn_top->CLOCK_GEN = 256;
495 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 250MHz");
496 
                break;
497 
                case 280:
498 
                        sn_top->CLOCK_GEN = 512;
499 
                        lblStatus->set_text("TX CLOCK SYSTEMC SET IN 280MHz");
500 
                break;
501 
        }
502 
 
503 
}
504 
 
505 
void on_BtnTimeCodeScTx_clicked()
506 
{
507 
        start_tick_data = !start_tick_data;
508 
        if(start_tick_data)
509 
        {lblStatus->set_text("TIME CODE ENABLED ON TX SYSTEMC");}
510 
        else
511 
        {lblStatus->set_text("TIME CODE DISABLED ON TX SYSTEMC");}
512 
}
513 
 
514 
void on_BtnSendDataScTx_clicked()
515 
{
516 
        start_send_data = !start_send_data;
517 
        if(start_send_data)
518 
        {lblStatus->set_text("SEND DATA ENABLED TX SYSTEMC");}
519 
        else
520 
        {lblStatus->set_text("SEND DATA DISABLED TX SYSTEMC");}
521 
}
522 
 
523 
void on_BtnGenerateDataSc_clicked()
524 
{
525 
        data_generated_sc.clear();
526 
        data_iteration_sc_aux=0;
527 
        data_iteration_sc=0;
528 
        if(CheckBtnEopGenSystemC->get_active())
529 
        {
530 
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
531 
                {
532 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
533 
                        {
534 
                                intermediate_sc(8,8) = 1;
535 
                                intermediate_sc(7,0) = 0;
536 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
537 
                        {
538 
                                intermediate_sc(7,0) = data_in(rd);
539 
                                intermediate_sc(8,8) = 0;
540 
                        }
541 
                        data_generated_sc.push_back(intermediate_sc);
542 
                }
543 
        }else if(CheckBtnEepGenSystemC->get_active())
544 
        {
545 
                for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
546 
                {
547 
                        if(cnt_max_data == 0 || cnt_max_data == max_data)
548 
                        {
549 
                                intermediate_sc(8,8) = 1;
550 
                                intermediate_sc(7,0) = 1;
551 
                        }else if(cnt_max_data > 0 && cnt_max_data < max_data)
552 
                        {
553 
                                intermediate_sc(7,0) = data_in(rd);
554 
                                intermediate_sc(8,8) = 0;
555 
                        }
556 
                        data_generated_sc.push_back(intermediate_sc);
557 
                }
558 
                intermediate_sc(7,0) = 1;
559 
                intermediate_sc(8,8) = 1;
560 
                data_generated_sc[nchar(rd)] = intermediate_sc;
561 
        }
562 
}
563 
 
564 
 
565 
void on_BtnChangeFrequencyVerilog_clicked()
566 
{
567 
        string aux = EntryFrequencyVerilog->get_text();
568 
 
569 
        switch(atoi(aux.c_str()))
570 
        {
571 
                case 2:
572 
                        frquency_nano_second = 500;
573 
                break;
574 
                case 10:
575 
                        frquency_nano_second = 100;
576 
                break;
577 
                case 20:
578 
                        frquency_nano_second = 50;
579 
                break;
580 
                case 50:
581 
                        frquency_nano_second = 20;
582 
                break;
583 
                case 100:
584 
                        frquency_nano_second = 10;
585 
                break;
586 
                case 150:
587 
                        frquency_nano_second = 7;
588 
                break;
589 
                case 200:
590 
                        frquency_nano_second = 5;
591 
                break;
592 
                case 201:
593 
                        frquency_nano_second = 4;
594 
                break;
595 
                case 250:
596 
                        frquency_nano_second = 4;
597 
                break;
598 
                case 280:
599 
                        frquency_nano_second = 3;
600 
                break;
601 
                default:
602 
                        frquency_nano_second = 500;
603 
                break;
604 
        }
605 
 
606 
}
607 
 
608 
void thread_gtkmm_run()
609 
{
610 
        //GRAPHICAL INTERFACE
611 
        Main Application(true);
612 
        builder = Gtk::Builder::create_from_file("SpaceWrireTestSuit.glade");
613 
 
614 
        builder->get_widget("SpaceWireTestStress", window);
615 
        builder->get_widget("BtnFinsihSimulation", BtnFinsihSimulation);
616 
        builder->get_widget("BtnLinkEnable", BtnLinkEnable);
617 
        builder->get_widget("BtnLinkDisable", BtnLinkDisable);
618 
        builder->get_widget("BtnAutoStart", BtnAutoStart);
619 
        builder->get_widget("BtnReset", BtnReset);
620 
 
621 
        builder->get_widget("BtnSpaceWireVerilog", BtnSpaceWireVerilog);
622 
        builder->get_widget("CheckbtnLinkDisable", CheckbtnLinkDisable);
623 
        builder->get_widget("CheckbtnAutoStart", CheckbtnAutoStart);
624 
        builder->get_widget("CheckbtnLinkEnable", CheckbtnLinkEnable);
625 
 
626 
        builder->get_widget("BtnGenerationDataVerilog", BtnGenerationDataVerilog);
627 
        builder->get_widget("BtnSimpleTest", BtnSimpleTest);
628 
        builder->get_widget("CheckBtnEopGenVerilog", CheckBtnEopGenVerilog);
629 
        builder->get_widget("CheckBtnEepGenVerilog", CheckBtnEepGenVerilog);
630 
        builder->get_widget("CheckBtnTimeCodeGenVerilog", CheckBtnTimeCodeGenVerilog);
631 
 
632 
        builder->get_widget("BtnChangeFrequencyVerilog", BtnChangeFrequencyVerilog);
633 
        builder->get_widget("EntryFrequencyVerilog", EntryFrequencyVerilog);
634 
 
635 
        builder->get_widget("BtnTxFrequency", BtnTxFrequency);
636 
        builder->get_widget("EntryFrequency", EntryFrequency);
637 
 
638 
        builder->get_widget("BtnSendDataScTx", BtnSendDataScTx);
639 
        builder->get_widget("BtnTimeCodeScTx", BtnTimeCodeScTx);
640 
        builder->get_widget("BtnGenerateDataSc", BtnGenerateDataSc);
641 
        builder->get_widget("CheckBtnEepGenSystemC", CheckBtnEepGenSystemC);
642 
        builder->get_widget("CheckBtnEopGenSystemC", CheckBtnEopGenSystemC);
643 
 
644 
        builder->get_widget("lblStatus",lblStatus);
645 
 
646 
        BtnFinsihSimulation->signal_clicked().connect(sigc::ptr_fun(&on_BtnFinsihSimulation_clicked));
647 
        BtnLinkEnable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkEnable_clicked));
648 
        BtnLinkDisable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkDisable_clicked));
649 
        BtnAutoStart->signal_clicked().connect(sigc::ptr_fun(&on_BtnAutoStart_clicked));
650 
        BtnReset->signal_clicked().connect(sigc::ptr_fun(&on_BtnReset_clicked));
651 
 
652 
        BtnSpaceWireVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnSpaceWireVerilog_clicked));
653 
 
654 
        BtnSimpleTest->signal_clicked().connect(sigc::ptr_fun(&on_BtnSimpleTest_clicked));
655 
 
656 
        BtnChangeFrequencyVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnChangeFrequencyVerilog_clicked));
657 
 
658 
        BtnGenerationDataVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerationDataVerilog_clicked));
659 
 
660 
        BtnTxFrequency->signal_clicked().connect(sigc::ptr_fun(&on_BtnTxFrequency_clicked));
661 
 
662 
        BtnSendDataScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnSendDataScTx_clicked));
663 
        BtnTimeCodeScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnTimeCodeScTx_clicked));
664 
        BtnGenerateDataSc->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerateDataSc_clicked));
665 
 
666 
        window->set_title("GLADIC SPACEWIRE TEST TOOL");
667 
 
668 
        Application.run(*window);
669 
}
670 
 
671 
Control_SC::Control_SC()
672 
{
673 
        clock_systemc  = 2;
674 
        sn_top = new sc_TOP_SPW("sc_TOP_SPW");
675 
        boost::thread workerThreadGTKMM(thread_gtkmm_run);
676 
 
677 
        data_col_store.push_back("CONTROL TYPE");
678 
        data_col_store.push_back("NUMBER GENERATED");
679 
        data_col_store.push_back("NUMBER RECEIVED");
680 
        data_col_store.push_back("COMPARE");
681 
        data_col_store.push_back("TIME STAMP");
682 
        REC_TX_SPW = new data_recorder("test_suit_vlog_sc.html",data_col_store,"test_suit_vlog_sc.html","TX VERILOG 2 RX SYSTEMC");
683 
        REC_TX_SPW->initialize();
684 
        COMPARE_SPW = new data_check();
685 
        data_col_store.clear();
686 
 
687 
        data_col_store0.push_back("CONTROL TYPE");
688 
        data_col_store0.push_back("NUMBER GENERATED");
689 
        data_col_store0.push_back("NUMBER RECEIVED");
690 
        data_col_store0.push_back("COMPARE");
691 
        data_col_store0.push_back("TIME STAMP");
692 
        REC_TX_SPWSC = new data_recorder("test_suit_sc_vlog.html",data_col_store0,"test_suit_sc_vlog.html","TX SYSTEMC 2 RX VERILOG");
693 
        COMPARE_SPW_RX = new data_check();
694 
        REC_TX_SPWSC->initialize();
695 
        data_col_store0.clear();
696 
}
697 
 
698 
void Control_SC::init()
699 
{
700 
 
701 
        sn_top->RESET     = true;
702 
 
703 
        sn_top->LINK_DISABLE  = false;
704 
        sn_top->LINK_START    = false;
705 
        sn_top->AUTO_START = false;
706 
 
707 
        sn_top->E_SEND_DATA = false;
708 
 
709 
        sn_top->CLOCK_GEN = 1;
710 
        frquency_nano_second = 500;
711 
        //sn_top->TICKIN_TX = false;
712 
        //sn_top->TIMEIN_CONTROL_FLAG_TX = 0;
713 
 
714 
        //sn_top->TXWRITE_TX = false;
715 
        //sn_top->TXDATA_FLAGCTRL_TX = 0;
716 
}
717 
 
718 
void autostart()
719 
{
720 
        if(auto_start)
721 
        {
722 
                sn_top->AUTO_START = true;
723 
                //lblStatus->set_text("AUTOSTART ENABLED ON TX SYSTEMC");
724 
        }
725 
        else
726 
        {
727 
                sn_top->AUTO_START = false;
728 
                //lblStatus->set_text("AUTOSTART DISABLED ON TX SYSTEMC");
729 
        }
730 
}
731 
 
732 
void linkstart()
733 
{
734 
        if(link_start)
735 
        {
736 
                sn_top->LINK_START = true;
737 
                //lblStatus->set_text("LINKSTART ENABLED ON TX SYSTEMC");
738 
        }
739 
        else
740 
        {
741 
                sn_top->LINK_START = false;
742 
                //lblStatus->set_text("LINKSTART DISABLED ON TX SYSTEMC");
743 
        }
744 
}
745 
 
746 
void linkdisable()
747 
{
748 
        if(link_disable)
749 
        {
750 
                sn_top->LINK_DISABLE = true;
751 
                //lblStatus->set_text("LINKDISABLE ENABLED ON TX SYSTEMC");
752 
        }
753 
        else
754 
        {
755 
                sn_top->LINK_DISABLE = false;
756 
                //lblStatus->set_text("LINKDISABLE DISABLED ON TX SYSTEMC");
757 
        }
758 
}
759 
 
760 
void send_data_tx_sc()
761 
{
762 
        if(start_send_data)
763 
        {
764 
                sn_top->E_SEND_DATA = true;
765 
        }
766 
        else
767 
        {
768 
                sn_top->E_SEND_DATA = false;
769 
        }
770 
 
771 
}
772 
 
773 
void Control_SC::run_sim()
774 
{
775 
 
776 
        autostart();
777 
        linkstart();
778 
        linkdisable();
779 
        send_data_tx_sc();
780 
 
781 
        sc_start(clock_systemc,SC_NS);
782 
 
783 
}
784 
 
785 
/*        END OF SIMULATION      */
786 
void Control_SC::stop_sim()
787 
{
788 
        sc_stop();
789 
}
790 
 
791 
/*         RESET HIGH           */
792 
bool Control_SC::reset_set()
793 
{
794 
 
795 
        if(global_reset)
796 
        {
797 
                sn_top->RESET = false;
798 
        }else
799 
        {
800 
                sn_top->RESET = true;
801 
        }
802 
 
803 
        return sn_top->RESET;
804 
}
805 
 
806 
unsigned int Control_SC::get_value_dout()
807 
{
808 
        return sn_top->DOUT.read();
809 
}
810 
 
811 
unsigned int Control_SC::get_value_sout()
812 
{
813 
        return sn_top->SOUT.read();
814 
}
815 
 
816 
void Control_SC::set_rx_sin(unsigned int strobe)
817 
{
818 
        sn_top->SIN = strobe;
819 
}
820 
 
821 
void Control_SC::set_rx_din(unsigned int data)
822 
{
823 
        sn_top->DIN = data;
824 
}
825 
 
826 
unsigned int Control_SC::get_spw_fsm()
827 
{
828 
        return sn_top->FSM_SPW_OUT.read();
829 
}
830 
 
831 
unsigned int  Control_SC::finish_simulation()
832 
{
833 
        return finish;
834 
}
835 
 
836 
//verilog variables
837 
bool Control_SC::verilog_linkenable()
838 
{
839 
        return verilog_link_start;
840 
}
841 
 
842 
bool Control_SC::verilog_autostart()
843 
{
844 
        return verilog_auto_start;
845 
}
846 
 
847 
bool Control_SC::verilog_linkdisable()
848 
{
849 
        return verilog_link_disable;
850 
}
851 
 
852 
float Control_SC::verilog_frequency()
853 
{
854 
        return frquency_nano_second;
855 
}
856 
 
857 
//Test verilog
858 
bool Control_SC::start_tx_test()
859 
{
860 
        return start_send_data_verilog;
861 
}
862 
 
863 
bool Control_SC::enable_time_code_tx_test()
864 
{
865 
        return enable_time_code_verilog;
866 
}
867 
 
868 
void Control_SC::end_tx_test()
869 
{
870 
        start_send_data_verilog = enable_time_code_verilog = false;
871 
}
872 
 
873 
int Control_SC::size_data_test()
874 
{
875 
        return data_generated_verilog.size()-1;
876 
}
877 
 
878 
unsigned int Control_SC::take_data(unsigned int a)
879 
{
880 
        intermediate = data_generated_verilog[a];
881 
        return intermediate(8,0);
882 
}
883 
 
884 
void Control_SC::data_o(unsigned int data, unsigned int pos)
885 
{
886 
                sc_uint<9> intermediate = data;
887 
 
888 
                data_col_store0.clear();
889 
                if(data_iteration_sc <= data_generated_sc.size()-1)
890 
                {
891 
                        data_col_store0.push_back("DATA");
892 
 
893 
                        intermediate_sc=data_generated_sc[pos];
894 
                        data_col_store0.push_back(intermediate_sc.to_string(SC_HEX));
895 
 
896 
                        data_col_store0.push_back(intermediate.to_string(SC_HEX));
897 
 
898 
                        data_col_store0.push_back(" ");
899 
                        COMPARE_SPW_RX->compare_test(&data_col_store0);
900 
 
901 
                        data_col_store0.push_back(sc_time_stamp().to_string());
902 
                        REC_TX_SPWSC->storedata(data_col_store0);
903 
                        data_iteration_sc++;
904 
                }else
905 
                {
906 
                        data_iteration_sc = 0;
907 
                }
908 
}
909 
 
910 
unsigned int Control_SC::clock_tx()
911 
{
912 
        return sn_top->DUT.CLOCK_TX_OUT.read();
913 
}
914 
 

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