OpenCores
URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

Subversion Repositories sparc64soc

[/] [sparc64soc/] [trunk/] [OC-Ethernet/] [eth_crc.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dmitryr
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_crc.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46
// Revision 1.2  2001/10/19 08:43:51  mohor
47
// eth_timescale.v changed to timescale.v This is done because of the
48
// simulation of the few cores in a one joined project.
49
//
50
// Revision 1.1  2001/08/06 14:44:29  mohor
51
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
52
// Include files fixed to contain no path.
53
// File names and module names changed ta have a eth_ prologue in the name.
54
// File eth_timescale.v is used to define timescale
55
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
56
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
57
// and Mdo_OE. The bidirectional signal must be created on the top level. This
58
// is done due to the ASIC tools.
59
//
60
// Revision 1.1  2001/07/30 21:23:42  mohor
61
// Directory structure changed. Files checked and joind together.
62
//
63
// Revision 1.3  2001/06/19 18:16:40  mohor
64
// TxClk changed to MTxClk (as discribed in the documentation).
65
// Crc changed so only one file can be used instead of two.
66
//
67
// Revision 1.2  2001/06/19 10:38:07  mohor
68
// Minor changes in header.
69
//
70
// Revision 1.1  2001/06/19 10:27:57  mohor
71
// TxEthMAC initial release.
72
//
73
//
74
//
75
 
76
 
77
`include "timescale.v"
78
 
79
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
80
 
81
 
82
parameter Tp = 1;
83
 
84
input Clk;
85
input Reset;
86
input [3:0] Data;
87
input Enable;
88
input Initialize;
89
 
90
output [31:0] Crc;
91
output CrcError;
92
 
93
reg  [31:0] Crc;
94
 
95
wire [31:0] CrcNext;
96
 
97
 
98
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
99
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
100
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
101
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
102
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
103
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
104
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
105
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
106
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
107
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
108
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
109
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
110
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
111
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
112
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
113
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
114
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
115
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
116
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
117
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
118
assign CrcNext[20] = Crc[16];
119
assign CrcNext[21] = Crc[17];
120
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
121
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
122
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
123
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
124
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
125
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
126
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
127
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
128
assign CrcNext[30] = Crc[26];
129
assign CrcNext[31] = Crc[27];
130
 
131
 
132
always @ (posedge Clk or posedge Reset)
133
begin
134
  if (Reset)
135
    Crc <= #1 32'hffffffff;
136
  else
137
  if(Initialize)
138
    Crc <= #Tp 32'hffffffff;
139
  else
140
    Crc <= #Tp CrcNext;
141
end
142
 
143
assign CrcError = Crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
144
 
145
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.