OpenCores
URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

Subversion Repositories sparc64soc

[/] [sparc64soc/] [trunk/] [OC-Ethernet/] [eth_txstatem.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dmitryr
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_txstatem.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46
// Revision 1.5  2002/10/30 12:54:50  mohor
47
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
48
//
49
// Revision 1.4  2002/01/23 10:28:16  mohor
50
// Link in the header changed.
51
//
52
// Revision 1.3  2001/10/19 08:43:51  mohor
53
// eth_timescale.v changed to timescale.v This is done because of the
54
// simulation of the few cores in a one joined project.
55
//
56
// Revision 1.2  2001/09/11 14:17:00  mohor
57
// Few little NCSIM warnings fixed.
58
//
59
// Revision 1.1  2001/08/06 14:44:29  mohor
60
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
61
// Include files fixed to contain no path.
62
// File names and module names changed ta have a eth_ prologue in the name.
63
// File eth_timescale.v is used to define timescale
64
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
65
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
66
// and Mdo_OE. The bidirectional signal must be created on the top level. This
67
// is done due to the ASIC tools.
68
//
69
// Revision 1.1  2001/07/30 21:23:42  mohor
70
// Directory structure changed. Files checked and joind together.
71
//
72
// Revision 1.3  2001/06/19 18:16:40  mohor
73
// TxClk changed to MTxClk (as discribed in the documentation).
74
// Crc changed so only one file can be used instead of two.
75
//
76
// Revision 1.2  2001/06/19 10:38:07  mohor
77
// Minor changes in header.
78
//
79
// Revision 1.1  2001/06/19 10:27:57  mohor
80
// TxEthMAC initial release.
81
//
82
//
83
//
84
//
85
 
86
 
87
`include "timescale.v"
88
 
89
 
90
module eth_txstatem  (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
91
                      IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
92
                      StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
93
                      NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
94
                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
95
                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
96
                      StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
97
                     );
98
 
99
parameter Tp = 1;
100
 
101
input MTxClk;
102
input Reset;
103
input ExcessiveDefer;
104
input CarrierSense;
105
input [6:0] NibCnt;
106
input [6:0] IPGT;
107
input [6:0] IPGR1;
108
input [6:0] IPGR2;
109
input FullD;
110
input TxStartFrm;
111
input TxEndFrm;
112
input TxUnderRun;
113
input Collision;
114
input UnderRun;
115
input StartTxDone;
116
input TooBig;
117
input NibCntEq7;
118
input NibCntEq15;
119
input MaxFrame;
120
input Pad;
121
input CrcEn;
122
input NibbleMinFl;
123
input RandomEq0;
124
input ColWindow;
125
input RetryMax;
126
input NoBckof;
127
input RandomEqByteCnt;
128
 
129
 
130
output StateIdle;         // Idle state
131
output StateIPG;          // IPG state
132
output StatePreamble;     // Preamble state
133
output [1:0] StateData;   // Data state
134
output StatePAD;          // PAD state
135
output StateFCS;          // FCS state
136
output StateJam;          // Jam state
137
output StateJam_q;        // Delayed Jam state
138
output StateBackOff;      // Backoff state
139
output StateDefer;        // Defer state
140
 
141
output StartFCS;          // FCS state will be activated in next clock
142
output StartJam;          // Jam state will be activated in next clock
143
output StartBackoff;      // Backoff state will be activated in next clock
144
output StartDefer;        // Defer state will be activated in next clock
145
output DeferIndication;
146
output StartPreamble;     // Preamble state will be activated in next clock
147
output [1:0] StartData;   // Data state will be activated in next clock
148
output StartIPG;          // IPG state will be activated in next clock
149
 
150
wire StartIdle;           // Idle state will be activated in next clock
151
wire StartPAD;            // PAD state will be activated in next clock
152
 
153
 
154
reg StateIdle;
155
reg StateIPG;
156
reg StatePreamble;
157
reg [1:0] StateData;
158
reg StatePAD;
159
reg StateFCS;
160
reg StateJam;
161
reg StateJam_q;
162
reg StateBackOff;
163
reg StateDefer;
164
reg Rule1;
165
 
166
 
167
// Defining the next state
168
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
169
 
170
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
171
 
172
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
173
 
174
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
175
 
176
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
177
 
178
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
179
 
180
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
181
                | ~Collision & StatePAD & NibbleMinFl & CrcEn;
182
 
183
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
184
 
185
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
186
 
187
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
188
                  | StateIdle & CarrierSense
189
                  | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
190
                  | StateBackOff & (TxUnderRun | RandomEqByteCnt)
191
                  | StartTxDone | TooBig;
192
 
193
assign DeferIndication = StateIdle & CarrierSense;
194
 
195
// Tx State Machine
196
always @ (posedge MTxClk or posedge Reset)
197
begin
198
  if(Reset)
199
    begin
200
      StateIPG        <= #Tp 1'b0;
201
      StateIdle       <= #Tp 1'b0;
202
      StatePreamble   <= #Tp 1'b0;
203
      StateData[1:0]  <= #Tp 2'b0;
204
      StatePAD        <= #Tp 1'b0;
205
      StateFCS        <= #Tp 1'b0;
206
      StateJam        <= #Tp 1'b0;
207
      StateJam_q      <= #Tp 1'b0;
208
      StateBackOff    <= #Tp 1'b0;
209
      StateDefer      <= #Tp 1'b1;
210
    end
211
  else
212
    begin
213
      StateData[1:0] <= #Tp StartData[1:0];
214
      StateJam_q <= #Tp StateJam;
215
 
216
      if(StartDefer | StartIdle)
217
        StateIPG <= #Tp 1'b0;
218
      else
219
      if(StartIPG)
220
        StateIPG <= #Tp 1'b1;
221
 
222
      if(StartDefer | StartPreamble)
223
        StateIdle <= #Tp 1'b0;
224
      else
225
      if(StartIdle)
226
        StateIdle <= #Tp 1'b1;
227
 
228
      if(StartData[0] | StartJam)
229
        StatePreamble <= #Tp 1'b0;
230
      else
231
      if(StartPreamble)
232
        StatePreamble <= #Tp 1'b1;
233
 
234
      if(StartFCS | StartJam)
235
        StatePAD <= #Tp 1'b0;
236
      else
237
      if(StartPAD)
238
        StatePAD <= #Tp 1'b1;
239
 
240
      if(StartJam | StartDefer)
241
        StateFCS <= #Tp 1'b0;
242
      else
243
      if(StartFCS)
244
        StateFCS <= #Tp 1'b1;
245
 
246
      if(StartBackoff | StartDefer)
247
        StateJam <= #Tp 1'b0;
248
      else
249
      if(StartJam)
250
        StateJam <= #Tp 1'b1;
251
 
252
      if(StartDefer)
253
        StateBackOff <= #Tp 1'b0;
254
      else
255
      if(StartBackoff)
256
        StateBackOff <= #Tp 1'b1;
257
 
258
      if(StartIPG)
259
        StateDefer <= #Tp 1'b0;
260
      else
261
      if(StartDefer)
262
        StateDefer <= #Tp 1'b1;
263
    end
264
end
265
 
266
 
267
// This sections defines which interpack gap rule to use
268
always @ (posedge MTxClk or posedge Reset)
269
begin
270
  if(Reset)
271
    Rule1 <= #Tp 1'b0;
272
  else
273
    begin
274
      if(StateIdle | StateBackOff)
275
        Rule1 <= #Tp 1'b0;
276
      else
277
      if(StatePreamble | FullD)
278
        Rule1 <= #Tp 1'b1;
279
    end
280
end
281
 
282
 
283
 
284
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.