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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_in2_gt_in1_3to1.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// Reduce three fpu_in2_gt_in1_*b results to one set of results.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_in2_gt_in1_3to1 (
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din2_neq_din1_hi,
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din2_gt_din1_hi,
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din2_neq_din1_mid,
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din2_gt_din1_mid,
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din2_neq_din1_lo,
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din2_gt_din1_lo,
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din2_neq_din1,
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din2_gt_din1
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);
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input din2_neq_din1_hi; // input 2 != input 1- high 3 bits
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input din2_gt_din1_hi; // input 2 > input 1- high 3 bits
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input din2_neq_din1_mid; // input 2 != input 1- middle 3 bits
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input din2_gt_din1_mid; // input 2 > input 1- middle 3 bits
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input din2_neq_din1_lo; // input 2 != input 1- low 3 bits
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input din2_gt_din1_lo; // input 2 > input 1- low 3 bits
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output din2_neq_din1; // input 2 doesn't equal input 1
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output din2_gt_din1; // input 2 is greater than input 1
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wire din2_neq_din1;
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wire din2_gt_din1;
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assign din2_neq_din1= din2_neq_din1_hi || din2_neq_din1_mid || din2_neq_din1_lo;
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assign din2_gt_din1= (din2_neq_din1_hi && din2_gt_din1_hi)
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|| ((!din2_neq_din1_hi) && din2_neq_din1_mid
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&& din2_gt_din1_mid)
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|| ((!din2_neq_din1_hi) && (!din2_neq_din1_mid)
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&& din2_gt_din1_lo);
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endmodule
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