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1 2 dmitryr 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: swrvr_clib.v
4 
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
9 
// License version 2 as published by the Free Software Foundation.
10 
//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
17 
// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 
///////////////////////////////////////////////////////////////////////
22 
/*
23 
//
24 
//  Module Name: swrvr_clib.v
25 
//      Description: Design control behavioural library
26 
*/
27 
 
28 
`ifdef FPGA_SYN
29 
`define NO_SCAN
30 
`endif
31 
 
32 
// POSITVE-EDGE TRIGGERED FLOP with SCAN
33 
module dff_s (din, clk, q, se, si, so);
34 
// synopsys template
35 
 
36 
parameter SIZE = 1;
37 
 
38 
input   [SIZE-1:0]       din ;   // data in
39 
input                   clk ;   // clk or scan clk
40 
 
41 
output  [SIZE-1:0]       q ;     // output
42 
 
43 
input                   se ;    // scan-enable
44 
input   [SIZE-1:0]       si ;    // scan-input
45 
output  [SIZE-1:0]       so ;    // scan-output
46 
 
47 
reg     [SIZE-1:0]       q ;
48 
 
49 
`ifdef NO_SCAN
50 
always @ (posedge clk)
51 
  q[SIZE-1:0]  <= din[SIZE-1:0] ;
52 
`else
53 
 
54 
always @ (posedge clk)
55 
 
56 
        q[SIZE-1:0]  <= (se) ? si[SIZE-1:0]  : din[SIZE-1:0] ;
57 
 
58 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
59 
 
60 
`endif
61 
 
62 
endmodule // dff_s
63 
 
64 
// POSITVE-EDGE TRIGGERED FLOP with SCAN for Shadow-scan
65 
module dff_sscan (din, clk, q, se, si, so);
66 
// synopsys template
67 
 
68 
parameter SIZE = 1;
69 
 
70 
input   [SIZE-1:0]       din ;   // data in
71 
input                   clk ;   // clk or scan clk
72 
 
73 
output  [SIZE-1:0]       q ;     // output
74 
 
75 
input                   se ;    // scan-enable
76 
input   [SIZE-1:0]       si ;    // scan-input
77 
output  [SIZE-1:0]       so ;    // scan-output
78 
 
79 
reg     [SIZE-1:0]       q ;
80 
 
81 
`ifdef CONNECT_SHADOW_SCAN
82 
 
83 
always @ (posedge clk)
84 
 
85 
        q[SIZE-1:0]  <= (se) ? si[SIZE-1:0]  : din[SIZE-1:0] ;
86 
 
87 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
88 
 
89 
`else
90 
always @ (posedge clk)
91 
  q[SIZE-1:0]  <= din[SIZE-1:0] ;
92 
 
93 
assign so={SIZE{1'b0}};
94 
`endif
95 
 
96 
endmodule // dff_sscan
97 
 
98 
// POSITVE-EDGE TRIGGERED FLOP without SCAN
99 
module dff_ns (din, clk, q);
100 
// synopsys template
101 
 
102 
parameter SIZE = 1;
103 
 
104 
input   [SIZE-1:0]       din ;   // data in
105 
input                   clk ;   // clk
106 
 
107 
output  [SIZE-1:0]       q ;     // output
108 
 
109 
reg     [SIZE-1:0]       q ;
110 
 
111 
always @ (posedge clk)
112 
 
113 
        q[SIZE-1:0]  <= din[SIZE-1:0] ;
114 
 
115 
endmodule // dff_ns
116 
 
117 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET
118 
module dffr_s (din, clk, rst, q, se, si, so);
119 
// synopsys template
120 
 
121 
parameter SIZE = 1;
122 
 
123 
input   [SIZE-1:0]       din ;   // data in
124 
input                   clk ;   // clk or scan clk
125 
input                   rst ;   // reset
126 
 
127 
output  [SIZE-1:0]       q ;     // output
128 
 
129 
input                   se ;    // scan-enable
130 
input   [SIZE-1:0]       si ;    // scan-input
131 
output  [SIZE-1:0]       so ;    // scan-output
132 
 
133 
reg     [SIZE-1:0]       q ;
134 
 
135 
`ifdef NO_SCAN
136 
always @ (posedge clk)
137 
        q[SIZE-1:0]  <= ((rst) ? {SIZE{1'b0}}  : din[SIZE-1:0] );
138 
`else
139 
 
140 
// Scan-Enable dominates
141 
always @ (posedge clk)
142 
 
143 
        q[SIZE-1:0]  <= se ? si[SIZE-1:0] : ((rst) ? {SIZE{1'b0}}  : din[SIZE-1:0] );
144 
 
145 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
146 
`endif
147 
 
148 
endmodule // dffr_s
149 
 
150 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET_L
151 
module dffrl_s (din, clk, rst_l, q, se, si, so);
152 
// synopsys template
153 
 
154 
parameter SIZE = 1;
155 
 
156 
input   [SIZE-1:0]       din ;   // data in
157 
input                   clk ;   // clk or scan clk
158 
input                   rst_l ; // reset
159 
 
160 
output  [SIZE-1:0]       q ;     // output
161 
 
162 
input                   se ;    // scan-enable
163 
input   [SIZE-1:0]       si ;    // scan-input
164 
output  [SIZE-1:0]       so ;    // scan-output
165 
 
166 
reg     [SIZE-1:0]       q ;
167 
 
168 
`ifdef NO_SCAN
169 
always @ (posedge clk)
170 
        q[SIZE-1:0]  <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
171 
`else
172 
 
173 
// Reset dominates
174 
always @ (posedge clk)
175 
 
176 
        q[SIZE-1:0]  <= rst_l ? ((se) ? si[SIZE-1:0]  : din[SIZE-1:0] ) : {SIZE{1'b0}};
177 
 
178 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
179 
`endif
180 
 
181 
endmodule // dffrl_s
182 
 
183 
// POSITIVE-EDGE TRIGGERED FLOP with RESET, without SCAN
184 
module dffr_ns (din, clk, rst, q);
185 
// synopsys template
186 
 
187 
parameter SIZE = 1;
188 
 
189 
input   [SIZE-1:0]       din ;   // data in
190 
input                   clk ;   // clk
191 
input                   rst ;   // reset
192 
 
193 
output  [SIZE-1:0]       q ;     // output
194 
 
195 
reg     [SIZE-1:0]       q ;
196 
 
197 
// synopsys sync_set_reset "rst"
198 
always @ (posedge clk)
199 
  q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
200 
 
201 
endmodule // dffr_ns
202 
 
203 
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, without SCAN
204 
module dffrl_ns (din, clk, rst_l, q);
205 
// synopsys template
206 
 
207 
parameter SIZE = 1;
208 
 
209 
input   [SIZE-1:0]       din ;   // data in
210 
input                   clk ;   // clk
211 
input                   rst_l ; // reset
212 
 
213 
output  [SIZE-1:0]       q ;     // output
214 
 
215 
reg     [SIZE-1:0]       q ;
216 
 
217 
// synopsys sync_set_reset "rst_l"
218 
always @ (posedge clk)
219 
  q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
220 
 
221 
endmodule // dffrl_ns
222 
 
223 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN and FUNCTIONAL ENABLE
224 
module dffe_s (din, en, clk, q, se, si, so);
225 
// synopsys template
226 
 
227 
parameter SIZE = 1;
228 
 
229 
input   [SIZE-1:0]       din ;   // data in
230 
input                   en ;    // functional enable
231 
input                   clk ;   // clk or scan clk
232 
 
233 
output  [SIZE-1:0]       q ;     // output
234 
 
235 
input                   se ;    // scan-enable
236 
input   [SIZE-1:0]       si ;    // scan-input
237 
output  [SIZE-1:0]       so ;    // scan-output
238 
 
239 
reg     [SIZE-1:0]       q ;
240 
 
241 
// Enable Interpretation. Ultimate interpretation depends on design
242 
//
243 
// en   se      out
244 
//------------------
245 
// x    1       sin ; scan dominates
246 
// 1    0        din
247 
// 0    0        q
248 
//
249 
 
250 
`ifdef NO_SCAN
251 
always @ (posedge clk)
252 
        q[SIZE-1:0]  <= ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
253 
`else
254 
 
255 
always @ (posedge clk)
256 
 
257 
        q[SIZE-1:0]  <= (se) ? si[SIZE-1:0]  : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
258 
 
259 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
260 
`endif
261 
 
262 
endmodule // dffe_s
263 
 
264 
// POSITIVE-EDGE TRIGGERED FLOP with enable, without SCAN
265 
module dffe_ns (din, en, clk, q);
266 
// synopsys template
267 
 
268 
parameter SIZE = 1;
269 
 
270 
input   [SIZE-1:0]       din ;   // data in
271 
input                   en ;    // functional enable
272 
input                   clk ;   // clk
273 
 
274 
output  [SIZE-1:0]       q ;     // output
275 
 
276 
reg     [SIZE-1:0]       q ;
277 
 
278 
always @ (posedge clk)
279 
  q[SIZE-1:0] <= en ? din[SIZE-1:0] : q[SIZE-1:0];
280 
 
281 
endmodule // dffe_ns
282 
 
283 
// POSITIVE-EDGE TRIGGERED FLOP with RESET, FUNCTIONAL ENABLE, SCAN.
284 
module dffre_s (din, rst, en, clk, q, se, si, so);
285 
// synopsys template
286 
 
287 
parameter SIZE = 1;
288 
 
289 
input   [SIZE-1:0]       din ;   // data in
290 
input                   en ;    // functional enable
291 
input                   rst ;   // reset
292 
input                   clk ;   // clk or scan clk
293 
 
294 
output  [SIZE-1:0]       q ;     // output
295 
 
296 
input                   se ;    // scan-enable
297 
input   [SIZE-1:0]       si ;    // scan-input
298 
output  [SIZE-1:0]       so ;    // scan-output
299 
 
300 
reg     [SIZE-1:0]       q ;
301 
 
302 
// Enable Interpretation. Ultimate interpretation depends on design
303 
//
304 
// rst  en      se      out
305 
//------------------
306 
// 1    x       x       0   ; reset dominates
307 
// 0    x       1       sin ; scan dominates
308 
// 0    1       0        din
309 
// 0    0       0        q
310 
//
311 
 
312 
`ifdef NO_SCAN
313 
always @ (posedge clk)
314 
        q[SIZE-1:0]  <= (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
315 
`else
316 
 
317 
always @ (posedge clk)
318 
 
319 
//      q[SIZE-1:0]  <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0]  : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
320 
        q[SIZE-1:0]  <= se ? si[SIZE-1:0]  : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
321 
 
322 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
323 
 
324 
`endif
325 
 
326 
endmodule // dffre_s
327 
 
328 
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, FUNCTIONAL ENABLE, SCAN.
329 
module dffrle_s (din, rst_l, en, clk, q, se, si, so);
330 
// synopsys template
331 
 
332 
parameter SIZE = 1;
333 
 
334 
input   [SIZE-1:0]       din ;   // data in
335 
input                   en ;    // functional enable
336 
input                   rst_l ; // reset
337 
input                   clk ;   // clk or scan clk
338 
 
339 
output  [SIZE-1:0]       q ;     // output
340 
 
341 
input                   se ;    // scan-enable
342 
input   [SIZE-1:0]       si ;    // scan-input
343 
output  [SIZE-1:0]       so ;    // scan-output
344 
 
345 
reg     [SIZE-1:0]       q ;
346 
 
347 
// Enable Interpretation. Ultimate interpretation depends on design
348 
//
349 
// rst  en      se      out
350 
//------------------
351 
// 0    x       x       0   ; reset dominates
352 
// 1    x       1       sin ; scan dominates
353 
// 1    1       0        din
354 
// 1    0       0        q
355 
//
356 
 
357 
`ifdef NO_SCAN
358 
always @ (posedge clk)
359 
         q[SIZE-1:0]  <= (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
360 
`else
361 
 
362 
always @ (posedge clk)
363 
 
364 
//      q[SIZE-1:0]  <= rst_l ? ((se) ? si[SIZE-1:0]  : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : {SIZE{1'b0}} ;
365 
        q[SIZE-1:0]  <= se ? si[SIZE-1:0]  : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
366 
 
367 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
368 
`endif
369 
 
370 
endmodule // dffrle_s
371 
 
372 
// POSITIVE-EDGE TRIGGERED FLOP with RESET, ENABLE, without SCAN.
373 
module dffre_ns (din, rst, en, clk, q);
374 
// synopsys template
375 
 
376 
parameter SIZE = 1;
377 
 
378 
input   [SIZE-1:0]       din ;   // data in
379 
input                   en ;    // functional enable
380 
input                   rst ;   // reset
381 
input                   clk ;   // clk
382 
 
383 
output  [SIZE-1:0]       q ;     // output
384 
 
385 
reg     [SIZE-1:0]       q ;
386 
 
387 
// Enable Interpretation. Ultimate interpretation depends on design
388 
//
389 
// rst  en      out
390 
//------------------
391 
// 1    x       0   ; reset dominates
392 
// 0    1       din
393 
// 0    0       q
394 
//
395 
 
396 
// synopsys sync_set_reset "rst"
397 
always @ (posedge clk)
398 
  q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
399 
 
400 
endmodule // dffre_ns
401 
 
402 
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, ENABLE, without SCAN.
403 
module dffrle_ns (din, rst_l, en, clk, q);
404 
// synopsys template
405 
 
406 
parameter SIZE = 1;
407 
 
408 
input   [SIZE-1:0]       din ;   // data in
409 
input                   en ;    // functional enable
410 
input                   rst_l ; // reset
411 
input                   clk ;   // clk
412 
 
413 
output  [SIZE-1:0]       q ;     // output
414 
 
415 
reg     [SIZE-1:0]       q ;
416 
 
417 
// Enable Interpretation. Ultimate interpretation depends on design
418 
//
419 
// rst  en      out
420 
//------------------
421 
// 0    x       0   ; reset dominates
422 
// 1    1       din
423 
// 1    0       q
424 
//
425 
 
426 
// synopsys sync_set_reset "rst_l"
427 
always @ (posedge clk)
428 
  q[SIZE-1:0] <= rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}} ;
429 
 
430 
endmodule // dffrle_ns
431 
 
432 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET
433 
module dffr_async (din, clk, rst, q, se, si, so);
434 
// synopsys template
435 
 
436 
parameter SIZE = 1;
437 
 
438 
input   [SIZE-1:0]      din ;   // data in
439 
input                   clk ;   // clk or scan clk
440 
input                   rst ;   // reset
441 
 
442 
output  [SIZE-1:0]      q ;     // output
443 
 
444 
input                   se ;    // scan-enable
445 
input   [SIZE-1:0]      si ;    // scan-input
446 
output  [SIZE-1:0]      so ;    // scan-output
447 
 
448 
reg     [SIZE-1:0]      q ;
449 
 
450 
`ifdef NO_SCAN
451 
always @ (posedge clk or posedge rst)
452 
        q[SIZE-1:0]  <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
453 
`else
454 
 
455 
// Reset dominates
456 
always @ (posedge clk or posedge rst)
457 
  q[SIZE-1:0]  <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0]  : din[SIZE-1:0] );
458 
 
459 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
460 
 
461 
`endif
462 
 
463 
endmodule // dffr_async
464 
 
465 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET_L
466 
module dffrl_async (din, clk, rst_l, q, se, si, so);
467 
// synopsys template
468 
 
469 
parameter SIZE = 1;
470 
 
471 
input   [SIZE-1:0]      din ;   // data in
472 
input                   clk ;   // clk or scan clk
473 
input                   rst_l ;   // reset
474 
 
475 
output  [SIZE-1:0]      q ;     // output
476 
 
477 
input                   se ;    // scan-enable
478 
input   [SIZE-1:0]      si ;    // scan-input
479 
output  [SIZE-1:0]      so ;    // scan-output
480 
 
481 
reg     [SIZE-1:0]      q ;
482 
 
483 
`ifdef NO_SCAN
484 
always @ (posedge clk or negedge rst_l)
485 
        q[SIZE-1:0]  <= (!rst_l) ? {SIZE{1'b0}} : din[SIZE-1:0];
486 
`else
487 
 
488 
// Reset dominates
489 
always @ (posedge clk or negedge rst_l)
490 
  q[SIZE-1:0]  <= (!rst_l) ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0]  : din[SIZE-1:0] );
491 
 
492 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
493 
 
494 
`endif
495 
 
496 
endmodule // dffrl_async
497 
 
498 
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET, without SCAN
499 
//module dffr_async_ns (din, clk, rst, q);
500 
//// synopsys template
501 
//parameter SIZE = 1;
502 
//input   [SIZE-1:0]      din ;   // data in
503 
//input                   clk ;   // clk or scan clk
504 
//input                   rst ;   // reset
505 
//output  [SIZE-1:0]      q ;     // output
506 
//reg     [SIZE-1:0]      q ;
507 
// Reset dominates
508 
//// synopsys async_set_reset "rst"
509 
//always @ (posedge clk or posedge rst)
510 
//        if(rst) q[SIZE-1:0]  <= {SIZE{1'b0}};
511 
//        else if(clk) q[SIZE-1:0]  <= din[SIZE-1:0];
512 
//endmodule // dffr_async_ns
513 
 
514 
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET_L, without SCAN
515 
module dffrl_async_ns (din, clk, rst_l, q);
516 
// synopsys template
517 
 
518 
parameter SIZE = 1;
519 
 
520 
input   [SIZE-1:0]      din ;   // data in
521 
input                   clk ;   // clk or scan clk
522 
input                   rst_l ;   // reset
523 
 
524 
output  [SIZE-1:0]      q ;     // output
525 
 
526 
// Reset dominates
527 
// synopsys async_set_reset "rst_l"
528 
 reg [SIZE-1:0] q;
529 
always @ (posedge clk or negedge rst_l)
530 
  q[SIZE-1:0] <= ~rst_l ?  {SIZE{1'b0}} : ({SIZE{rst_l}} & din[SIZE-1:0]);
531 
 
532 
//   reg  [SIZE-1:0]   qm, qs, qm_l, qs_l, qm_f, qs_f;
533 
//   wire              s_l;
534 
//   assign            s_l = 1'b1;
535 
//
536 
//   always @ (rst_l or qm)   qm_l = ~(qm & {SIZE{rst_l}});
537 
//   always @ (s_l or qs)   qs_l = ~(qs & {SIZE{s_l}});
538 
//   always @ (s_l or qm_l) qm_f = ~(qm_l & {SIZE{s_l}});
539 
//   always @ (rst_l or qs_l) qs_f = ~(qs_l & {SIZE{rst_l}});
540 
//
541 
//   always @ (clk or din or qm_f)
542 
//      qm <= clk ? qm_f : din;
543 
//
544 
//   always @ (clk or qm_l or qs_f)
545 
//      qs <= clk ? qm_l : qs_f;
546 
//
547 
//   assign q  = ~qs;
548 
 
549 
endmodule // dffrl_async_ns
550 
 
551 
// 2:1 MUX WITH DECODED SELECTS
552 
module mux2ds (dout, in0, in1, sel0, sel1) ;
553 
// synopsys template
554 
 
555 
parameter SIZE = 1;
556 
 
557 
output  [SIZE-1:0]       dout;
558 
input   [SIZE-1:0]       in0;
559 
input   [SIZE-1:0]       in1;
560 
input                   sel0;
561 
input                   sel1;
562 
 
563 
// reg declaration does not imply state being maintained
564 
// across cycles. Used to construct case statement and
565 
// always updated by inputs every cycle.
566 
reg     [SIZE-1:0]       dout ;
567 
 
568 
// priority encoding takes care of mutex'ing selects.
569 
`ifdef VERPLEX
570 
   $constraint cl_1h_chk2 ($one_hot ({sel1,sel0}));
571 
`endif
572 
 
573 
wire [1:0] sel = {sel1, sel0}; // 0in one_hot
574 
 
575 
always @ (sel0 or sel1 or in0 or in1)
576 
 
577 
        case ({sel1,sel0}) // synopsys infer_mux
578 
                2'b01 : dout = in0 ;
579 
                2'b10 : dout = in1 ;
580 
                2'b11 : dout = {SIZE{1'bx}} ;
581 
                2'b00 : dout = {SIZE{1'bx}} ;
582 
                        // 2'b00 : // E.g. 4state vs. 2state modelling.
583 
                        // begin
584 
                        //      `ifdef FOUR_STATE
585 
                        //              dout = {SIZE{1'bx}};
586 
                        //      `else
587 
                        //              begin
588 
                        //              dout = {SIZE{1'b0}};
589 
                        //              $error();
590 
                        //              end
591 
                        //      `endif
592 
                        // end
593 
                default : dout = {SIZE{1'bx}};
594 
        endcase
595 
 
596 
endmodule // mux2ds
597 
 
598 
// 3:1 MUX WITH DECODED SELECTS
599 
module mux3ds (dout, in0, in1, in2, sel0, sel1, sel2) ;
600 
// synopsys template
601 
 
602 
parameter SIZE = 1;
603 
 
604 
output  [SIZE-1:0]       dout;
605 
input   [SIZE-1:0]       in0;
606 
input   [SIZE-1:0]       in1;
607 
input   [SIZE-1:0]       in2;
608 
input                   sel0;
609 
input                   sel1;
610 
input                   sel2;
611 
 
612 
// reg declaration does not imply state being maintained
613 
// across cycles. Used to construct case statement and
614 
// always updated by inputs every cycle.
615 
reg     [SIZE-1:0]       dout ;
616 
 
617 
`ifdef VERPLEX
618 
   $constraint cl_1h_chk3 ($one_hot ({sel2,sel1,sel0}));
619 
`endif
620 
 
621 
wire [2:0] sel = {sel2,sel1,sel0}; // 0in one_hot
622 
 
623 
// priority encoding takes care of mutex'ing selects.
624 
always @ (sel0 or sel1 or sel2 or in0 or in1 or in2)
625 
 
626 
        case ({sel2,sel1,sel0})
627 
                3'b001 : dout = in0 ;
628 
                3'b010 : dout = in1 ;
629 
                3'b100 : dout = in2 ;
630 
                3'b000 : dout = {SIZE{1'bx}} ;
631 
                3'b011 : dout = {SIZE{1'bx}} ;
632 
                3'b101 : dout = {SIZE{1'bx}} ;
633 
                3'b110 : dout = {SIZE{1'bx}} ;
634 
                3'b111 : dout = {SIZE{1'bx}} ;
635 
                default : dout = {SIZE{1'bx}};
636 
                        // two state vs four state modelling will be added.
637 
        endcase
638 
 
639 
endmodule // mux3ds
640 
 
641 
// 4:1 MUX WITH DECODED SELECTS
642 
module mux4ds (dout, in0, in1, in2, in3, sel0, sel1, sel2, sel3) ;
643 
// synopsys template
644 
 
645 
parameter SIZE = 1;
646 
 
647 
output  [SIZE-1:0]       dout;
648 
input   [SIZE-1:0]       in0;
649 
input   [SIZE-1:0]       in1;
650 
input   [SIZE-1:0]       in2;
651 
input   [SIZE-1:0]       in3;
652 
input                   sel0;
653 
input                   sel1;
654 
input                   sel2;
655 
input                   sel3;
656 
 
657 
// reg declaration does not imply state being maintained
658 
// across cycles. Used to construct case statement and
659 
// always updated by inputs every cycle.
660 
reg     [SIZE-1:0]       dout ;
661 
 
662 
`ifdef VERPLEX
663 
   $constraint cl_1h_chk4 ($one_hot ({sel3,sel2,sel1,sel0}));
664 
`endif
665 
 
666 
wire [3:0] sel = {sel3,sel2,sel1,sel0}; // 0in one_hot
667 
 
668 
// priority encoding takes care of mutex'ing selects.
669 
always @ (sel0 or sel1 or sel2 or sel3 or in0 or in1 or in2 or in3)
670 
 
671 
        case ({sel3,sel2,sel1,sel0})
672 
                4'b0001 : dout = in0 ;
673 
                4'b0010 : dout = in1 ;
674 
                4'b0100 : dout = in2 ;
675 
                4'b1000 : dout = in3 ;
676 
                4'b0000 : dout = {SIZE{1'bx}} ;
677 
                4'b0011 : dout = {SIZE{1'bx}} ;
678 
                4'b0101 : dout = {SIZE{1'bx}} ;
679 
                4'b0110 : dout = {SIZE{1'bx}} ;
680 
                4'b0111 : dout = {SIZE{1'bx}} ;
681 
                4'b1001 : dout = {SIZE{1'bx}} ;
682 
                4'b1010 : dout = {SIZE{1'bx}} ;
683 
                4'b1011 : dout = {SIZE{1'bx}} ;
684 
                4'b1100 : dout = {SIZE{1'bx}} ;
685 
                4'b1101 : dout = {SIZE{1'bx}} ;
686 
                4'b1110 : dout = {SIZE{1'bx}} ;
687 
                4'b1111 : dout = {SIZE{1'bx}} ;
688 
                default : dout = {SIZE{1'bx}};
689 
                        // two state vs four state modelling will be added.
690 
        endcase
691 
 
692 
endmodule // mux4ds
693 
 
694 
// SINK FOR UNLOADED INPUT PORTS
695 
module sink (in);
696 
// synopsys template
697 
 
698 
parameter SIZE = 1;
699 
 
700 
input [SIZE-1:0] in;
701 
 
702 
`ifdef FPGA_SYN
703 
   // As of version 8.2 XST does not remove this module without the
704 
   // following additional dead code
705 
 
706 
   wire    a;
707 
 
708 
   assign               a = | in;
709 
 
710 
`endif
711 
 
712 
endmodule //sink
713 
 
714 
// SOURCE FOR UNDRIVEN OUTPUT PORTS
715 
module source (out) ;
716 
// synopsys template
717 
 
718 
parameter SIZE = 1;
719 
 
720 
output  [SIZE-1:0] out;
721 
//
722 
// Once 4state/2state model established
723 
// then enable check.
724 
// `ifdef FOUR_STATE
725 
// leda check for x_or_z_in rhs_of assign turned off
726 
// assign  out = {SIZE{1'bx}};
727 
//`else
728 
assign  out = {SIZE{1'b0}};
729 
//`endif
730 
 
731 
endmodule //source
732 
 
733 
// 2:1 MUX WITH PRIORITY ENCODED SELECTS
734 
//module mux2es (dout, in0, in1, sel0, sel1) ;
735 
//
736 
//parameter SIZE = 1;
737 
//
738 
//output        [SIZE-1:0]      dout;
739 
//input [SIZE-1:0]      in0;
740 
//input [SIZE-1:0]      in1;
741 
//input                 sel0;
742 
//input                 sel1;
743 
//
744 
//// reg declaration does not imply state being maintained
745 
//// across cycles. Used to construct case statement and
746 
//// always updated by inputs every cycle.
747 
//reg   [SIZE-1:0]      dout ;
748 
//
749 
//// must take into account lack of mutex selects.
750 
//// there is no reason for handling of x and z conditions.
751 
//// This will be dictated by design.
752 
//always @ (sel0 or sel1 or in0 or in1)
753 
//
754 
//      case ({sel1,sel0})
755 
//              2'b1x : dout = in1 ; // 10(in1),11(z)
756 
//              2'b0x : dout = in0 ; // 01(in0),00(x)
757 
//      endcase
758 
//
759 
//endmodule // mux2es
760 
 
761 
// CLK Header for gating off the clock of
762 
// a FF.
763 
// clk - output of the clk header
764 
// rclk - input clk
765 
// enb_l - Active low clock enable
766 
// tmb_l  - Active low clock enable ( in scan mode, this input is !se )
767 
 
768 
module clken_buf (clk, rclk, enb_l, tmb_l);
769 
output clk;
770 
input  rclk, enb_l, tmb_l;
771 
reg    clken;
772 
 
773 
`ifdef FPGA_SYN
774 
   assign clk = rclk;
775 
`else
776 
  always @ (rclk or enb_l or tmb_l)
777 
    if (!rclk)  //latch opens on rclk low phase
778 
      clken = !enb_l | !tmb_l;
779 
  assign clk = clken & rclk;
780 
`endif
781 
endmodule
782 
 
783 
 
784 
 
785 
// The following flops are maintained and used in ENET , MAC IP  ONLY
786 
// -- Mimi X61467
787 
 
788 
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
789 
 
790 
module dffsl_ns (din, clk, set_l, q);
791 
// synopsys template
792 
parameter SIZE = 1;
793 
 
794 
input   [SIZE-1:0]      din ;   // data in
795 
input                   clk ;   // clk or scan clk
796 
input                   set_l ; // set
797 
 
798 
output  [SIZE-1:0]      q ;     // output
799 
 
800 
reg     [SIZE-1:0]      q ;
801 
 
802 
// synopsys sync_set_reset "set_l"
803 
always @ (posedge clk)
804 
  q[SIZE-1:0] <= set_l ? din[SIZE-1:0] : {SIZE{1'b1}};
805 
 
806 
endmodule // dffsl_ns
807 
 
808 
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
809 
 
810 
module dffsl_async_ns (din, clk, set_l, q);
811 
// synopsys template
812 
parameter SIZE = 1;
813 
 
814 
input   [SIZE-1:0]      din ;   // data in
815 
input                   clk ;   // clk or scan clk
816 
input                   set_l ; // set
817 
 
818 
output  [SIZE-1:0]      q ;     // output
819 
 
820 
reg     [SIZE-1:0]      q ;
821 
 
822 
// synopsys async_set_reset "set_l"
823 
always @ (posedge clk or negedge set_l)
824 
  q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | din[SIZE-1:0]);
825 
 
826 
endmodule // dffsl_async_ns
827 
 
828 
// POSITIVE-EDGE TRIGGERED FLOP WITH SET_H , without SCAN.
829 
 
830 
module dffr_ns_r1 (din, clk, rst, q);
831 
// synopsys template
832 
parameter SIZE = 1;
833 
 
834 
input   [SIZE-1:0]      din ;   // data in
835 
input                   clk ;   // clk or scan clk
836 
input                   rst ;   // reset
837 
 
838 
output  [SIZE-1:0]      q ;     // output
839 
 
840 
reg     [SIZE-1:0]      q ;
841 
 
842 
// Set to 1
843 
// synopsys sync_set_reset "rst"
844 
always @ (posedge clk)
845 
  q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
846 
 
847 
endmodule // dffr_ns_r1
848 
 
849 
// POSITIVE-EDGE TRIGGERED ASYNC RESET_H FLOP , without SCAN.
850 
 
851 
module dffr_async_ns (din, clk, rst, q);
852 
// synopsys template
853 
 
854 
parameter SIZE = 1;
855 
 
856 
input   [SIZE-1:0]      din ;   // data in
857 
input                   clk ;   // clk or scan clk
858 
input                   rst;   // reset
859 
 
860 
output  [SIZE-1:0]      q ;     // output
861 
 
862 
reg     [SIZE-1:0]      q ;
863 
 
864 
// Reset dominates
865 
// synopsys async_set_reset "rst"
866 
always @ (posedge clk or posedge rst)
867 
  q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
868 
 
869 
endmodule // dffr_async_ns
870 
 
871 
// POSITIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
872 
 
873 
module dffr_async_ns_r1 (din, clk, rst, q);
874 
// synopsys template
875 
 
876 
parameter SIZE = 1;
877 
 
878 
input   [SIZE-1:0]      din ;   // data in
879 
input                   clk ;   // clk or scan clk
880 
input                   rst;   // reset
881 
 
882 
output  [SIZE-1:0]      q ;     // output
883 
 
884 
reg     [SIZE-1:0]      q ;
885 
 
886 
// Reset to 1
887 
// synopsys async_set_reset "rst"
888 
always @ (posedge clk or posedge rst)
889 
  q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
890 
 
891 
endmodule // dffr_async_ns_r1
892 
 
893 
 
894 
// NEGATIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
895 
 
896 
module dffr_async_ns_cl_r1 (din, clkl, rst, q);
897 
// synopsys template
898 
parameter SIZE = 1;
899 
 
900 
input   [SIZE-1:0]      din ;   // data in
901 
input                   clkl ;  // clk or scan clk
902 
input                   rst ;   // reset
903 
 
904 
output  [SIZE-1:0]      q ;     // output
905 
 
906 
reg     [SIZE-1:0]      q ;
907 
 
908 
// Set to 1
909 
// synopsys sync_set_reset "rst"
910 
always @ (negedge clkl or posedge rst)
911 
  q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
912 
 
913 
endmodule // dffr_async_ns_cl_r1
914 
 

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